xref: /llvm-project/llvm/test/CodeGen/Thumb2/thumb2-rev16.ll (revision dad5f00e3b4d437fc1247d2d84efee924ae13201) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=thumbv7m-none-eabi -o - |  FileCheck %s
3
4; 0xff00ff00 = 4278255360
5; 0x00ff00ff = 16711935
6define i32 @rev16(i32 %a) {
7; CHECK-LABEL: rev16:
8; CHECK:       @ %bb.0:
9; CHECK-NEXT:    rev16 r0, r0
10; CHECK-NEXT:    bx lr
11    %l8 = shl i32 %a, 8
12    %r8 = lshr i32 %a, 8
13    %mask_l8 = and i32 %l8, 4278255360
14    %mask_r8 = and i32 %r8, 16711935
15    %tmp = or i32 %mask_l8, %mask_r8
16    ret i32 %tmp
17}
18
19define i32 @not_rev16(i32 %a) {
20; CHECK-LABEL: not_rev16:
21; CHECK:       @ %bb.0:
22; CHECK-NEXT:    mov.w r1, #65280
23; CHECK-NEXT:    and.w r1, r1, r0, lsr #8
24; CHECK-NEXT:    and r0, r0, #65280
25; CHECK-NEXT:    orr.w r0, r1, r0, lsl #8
26; CHECK-NEXT:    bx lr
27    %l8 = shl i32 %a, 8
28    %r8 = lshr i32 %a, 8
29    %mask_r8 = and i32 %r8, 4278255360
30    %mask_l8 = and i32 %l8, 16711935
31    %tmp = or i32 %mask_r8, %mask_l8
32    ret i32 %tmp
33}
34
35define i32 @extra_maskop_uses2(i32 %a) {
36; CHECK-LABEL: extra_maskop_uses2:
37; CHECK:       @ %bb.0:
38; CHECK-NEXT:    mov.w r1, #-16711936
39; CHECK-NEXT:    mov.w r2, #16711935
40; CHECK-NEXT:    and.w r1, r1, r0, lsl #8
41; CHECK-NEXT:    and.w r0, r2, r0, lsr #8
42; CHECK-NEXT:    adds r2, r0, r1
43; CHECK-NEXT:    muls r0, r1, r0
44; CHECK-NEXT:    muls r0, r2, r0
45; CHECK-NEXT:    bx lr
46  %l8 = shl i32 %a, 8
47  %r8 = lshr i32 %a, 8
48  %mask_l8 = and i32 %l8, 4278255360
49  %mask_r8 = and i32 %r8, 16711935
50  %or = or i32 %mask_r8, %mask_l8
51  %mul = mul i32 %mask_r8, %mask_l8   ; another use of the mask ops
52  %r = mul i32 %mul, %or              ; and use that result
53  ret i32 %r
54}
55
56
57define i32 @bswap_ror_commuted(i32 %a) {
58; CHECK-LABEL: bswap_ror_commuted:
59; CHECK:       @ %bb.0:
60; CHECK-NEXT:    rev16 r0, r0
61; CHECK-NEXT:    bx lr
62    %l8 = shl i32 %a, 8
63    %r8 = lshr i32 %a, 8
64    %mask_l8 = and i32 %l8, 4278255360
65    %mask_r8 = and i32 %r8, 16711935
66    %tmp = or i32 %mask_r8, %mask_l8
67    ret i32 %tmp
68}
69
70define i32 @different_shift_amount(i32 %a) {
71; CHECK-LABEL: different_shift_amount:
72; CHECK:       @ %bb.0:
73; CHECK-NEXT:    mov.w r1, #16711935
74; CHECK-NEXT:    movw r2, #65024
75; CHECK-NEXT:    and.w r1, r1, r0, lsr #8
76; CHECK-NEXT:    movt r2, #65280
77; CHECK-NEXT:    and.w r0, r2, r0, lsl #9
78; CHECK-NEXT:    add r0, r1
79; CHECK-NEXT:    bx lr
80    %l8 = shl i32 %a, 9
81    %r8 = lshr i32 %a, 8
82    %mask_l8 = and i32 %l8, 4278255360
83    %mask_r8 = and i32 %r8, 16711935
84    %tmp = or i32 %mask_l8, %mask_r8
85    ret i32 %tmp
86}
87
88define i32 @different_constant(i32 %a) {
89; CHECK-LABEL: different_constant:
90; CHECK:       @ %bb.0:
91; CHECK-NEXT:    mov.w r1, #16711935
92; CHECK-NEXT:    and.w r0, r1, r0, lsr #8
93; CHECK-NEXT:    bx lr
94    %l8 = shl i32 %a, 8
95    %r8 = lshr i32 %a, 8
96    %mask_l8 = and i32 %l8, 42
97    %mask_r8 = and i32 %r8, 16711935
98    %tmp = or i32 %mask_l8, %mask_r8
99    ret i32 %tmp
100}
101
102define i32 @different_op(i32 %a) {
103; CHECK-LABEL: different_op:
104; CHECK:       @ %bb.0:
105; CHECK-NEXT:    mov.w r1, #16711935
106; CHECK-NEXT:    movw r2, #256
107; CHECK-NEXT:    and.w r1, r1, r0, lsr #8
108; CHECK-NEXT:    movt r2, #255
109; CHECK-NEXT:    add.w r0, r2, r0, lsl #8
110; CHECK-NEXT:    orrs r0, r1
111; CHECK-NEXT:    bx lr
112    %l8 = shl i32 %a, 8
113    %r8 = lshr i32 %a, 8
114    %mask_l8 = sub i32 %l8, 4278255360
115    %mask_r8 = and i32 %r8, 16711935
116    %tmp = or i32 %mask_l8, %mask_r8
117    ret i32 %tmp
118}
119
120define i32 @different_vars(i32 %a, i32 %b) {
121; CHECK-LABEL: different_vars:
122; CHECK:       @ %bb.0:
123; CHECK-NEXT:    mov.w r2, #16711935
124; CHECK-NEXT:    and.w r1, r2, r1, lsr #8
125; CHECK-NEXT:    mov.w r2, #-16711936
126; CHECK-NEXT:    and.w r0, r2, r0, lsl #8
127; CHECK-NEXT:    add r0, r1
128; CHECK-NEXT:    bx lr
129    %l8 = shl i32 %a, 8
130    %r8 = lshr i32 %b, 8
131    %mask_l8 = and i32 %l8, 4278255360
132    %mask_r8 = and i32 %r8, 16711935
133    %tmp = or i32 %mask_l8, %mask_r8
134    ret i32 %tmp
135}
136
137
138; FIXME: this rev16 pattern is not matching
139
140; 0xff000000 = 4278190080
141; 0x00ff0000 = 16711680
142; 0x0000ff00 = 65280
143; 0x000000ff = 255
144define i32 @f2(i32 %a) {
145; CHECK-LABEL: f2:
146; CHECK:       @ %bb.0:
147; CHECK-NEXT:    mov.w r1, #16711680
148; CHECK-NEXT:    and r2, r0, #16711680
149; CHECK-NEXT:    and.w r1, r1, r0, lsr #8
150; CHECK-NEXT:    orr.w r1, r1, r2, lsl #8
151; CHECK-NEXT:    ubfx r2, r0, #8, #8
152; CHECK-NEXT:    bfi r2, r0, #8, #8
153; CHECK-NEXT:    adds r0, r2, r1
154; CHECK-NEXT:    bx lr
155    %l8 = shl i32 %a, 8
156    %r8 = lshr i32 %a, 8
157    %masklo_l8 = and i32 %l8, 65280
158    %maskhi_l8 = and i32 %l8, 4278190080
159    %masklo_r8 = and i32 %r8, 255
160    %maskhi_r8 = and i32 %r8, 16711680
161    %tmp1 = or i32 %masklo_l8, %masklo_r8
162    %tmp2 = or i32 %maskhi_l8, %maskhi_r8
163    %tmp = or i32 %tmp1, %tmp2
164    ret i32 %tmp
165}
166