1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv7m-none-eabi -mcpu=cortex-m7 -run-pass=pipeliner --pipeliner-force-issue-width=10 -o - %s | FileCheck %s --check-prefix=CHECK 3 4# This test checks that too much register pressure will cause the modulo 5# schedule to be rejected and that a test with the same resource usage 6# but without register pressure is not rejected. 7 8--- | 9 define hidden float @high_pressure(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, i32 noundef %sz) local_unnamed_addr #0 { 10 entry: 11 %cmp8 = icmp sgt i32 %sz, 0 12 br i1 %cmp8, label %for.body.preheader, label %for.end 13 14 for.body.preheader: ; preds = %entry 15 %scevgep = getelementptr float, ptr %b, i32 -1 16 %scevgep4 = getelementptr float, ptr %a, i32 -1 17 br label %for.body 18 19 for.body: ; preds = %for.body.preheader, %for.body 20 %lsr.iv5 = phi ptr [ %scevgep4, %for.body.preheader ], [ %scevgep6, %for.body ] 21 %lsr.iv1 = phi ptr [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ] 22 %lsr.iv = phi i32 [ %sz, %for.body.preheader ], [ %lsr.iv.next, %for.body ] 23 %sum.010 = phi float [ %add, %for.body ], [ 0.000000e+00, %for.body.preheader ] 24 %scevgep7 = getelementptr float, ptr %lsr.iv5, i32 1 25 %0 = load float, ptr %scevgep7, align 4 26 %scevgep3 = getelementptr float, ptr %lsr.iv1, i32 1 27 %1 = load float, ptr %scevgep3, align 4 28 %mul = fmul fast float %1, %0 29 %add = fadd fast float %mul, %sum.010 30 %lsr.iv.next = add i32 %lsr.iv, -1 31 %scevgep2 = getelementptr float, ptr %lsr.iv1, i32 1 32 %scevgep6 = getelementptr float, ptr %lsr.iv5, i32 1 33 %exitcond.not = icmp eq i32 %lsr.iv.next, 0 34 br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0 35 36 for.end: ; preds = %for.body, %entry 37 %sum.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ] 38 ret float %sum.0.lcssa 39 } 40 41 !0 = distinct !{!0, !1, !2, !3} 42 !1 = !{!"llvm.loop.mustprogress"} 43 !2 = !{!"llvm.loop.unroll.disable"} 44 !3 = !{!"llvm.loop.pipeline.initiationinterval", i32 3} 45 46 47 define hidden float @low_pressure(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, i32 noundef %sz) local_unnamed_addr #0 { 48 entry: 49 %cmp8 = icmp sgt i32 %sz, 0 50 br i1 %cmp8, label %for.body.preheader, label %for.end 51 52 for.body.preheader: ; preds = %entry 53 %scevgep = getelementptr float, ptr %b, i32 -1 54 %scevgep4 = getelementptr float, ptr %a, i32 -1 55 br label %for.body 56 57 for.body: ; preds = %for.body.preheader, %for.body 58 %lsr.iv5 = phi ptr [ %scevgep4, %for.body.preheader ], [ %scevgep6, %for.body ] 59 %lsr.iv1 = phi ptr [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ] 60 %lsr.iv = phi i32 [ %sz, %for.body.preheader ], [ %lsr.iv.next, %for.body ] 61 %sum.010 = phi float [ %add, %for.body ], [ 0.000000e+00, %for.body.preheader ] 62 %scevgep7 = getelementptr float, ptr %lsr.iv5, i32 1 63 %0 = load float, ptr %scevgep7, align 4 64 %scevgep3 = getelementptr float, ptr %lsr.iv1, i32 1 65 %1 = load float, ptr %scevgep3, align 4 66 %mul = fmul fast float %1, %0 67 %add = fadd fast float %mul, %sum.010 68 %lsr.iv.next = add i32 %lsr.iv, -1 69 %scevgep2 = getelementptr float, ptr %lsr.iv1, i32 1 70 %scevgep6 = getelementptr float, ptr %lsr.iv5, i32 1 71 %exitcond.not = icmp eq i32 %lsr.iv.next, 0 72 br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !4 73 74 for.end: ; preds = %for.body, %entry 75 %sum.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ] 76 ret float %sum.0.lcssa 77 } 78 79 !4 = distinct !{!4, !5, !6, !7} 80 !5 = !{!"llvm.loop.mustprogress"} 81 !6 = !{!"llvm.loop.unroll.disable"} 82 !7 = !{!"llvm.loop.pipeline.initiationinterval", i32 3} 83 84... 85--- 86name: high_pressure 87alignment: 2 88tracksRegLiveness: true 89constants: 90 - id: 0 91 value: 'float 0.000000e+00' 92 alignment: 4 93 isTargetSpecific: false 94body: | 95 ; CHECK-LABEL: name: high_pressure 96 ; CHECK: bb.0.entry: 97 ; CHECK-NEXT: successors: %bb.2(0x50000000), %bb.1(0x30000000) 98 ; CHECK-NEXT: liveins: $r0, $r1, $r2 99 ; CHECK-NEXT: {{ $}} 100 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r2 101 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1 102 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnopc = COPY $r0 103 ; CHECK-NEXT: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 104 ; CHECK-NEXT: t2Bcc %bb.2, 10 /* CC::ge */, $cpsr 105 ; CHECK-NEXT: {{ $}} 106 ; CHECK-NEXT: bb.1: 107 ; CHECK-NEXT: successors: %bb.4(0x80000000) 108 ; CHECK-NEXT: {{ $}} 109 ; CHECK-NEXT: [[VLDRS:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) 110 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg 111 ; CHECK-NEXT: {{ $}} 112 ; CHECK-NEXT: bb.2.for.body.preheader: 113 ; CHECK-NEXT: successors: %bb.3(0x80000000) 114 ; CHECK-NEXT: {{ $}} 115 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[COPY1]], 4, 14 /* CC::al */, $noreg, $noreg 116 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY [[t2SUBri]] 117 ; CHECK-NEXT: [[t2SUBri1:%[0-9]+]]:rgpr = t2SUBri [[COPY2]], 4, 14 /* CC::al */, $noreg, $noreg 118 ; CHECK-NEXT: [[VLDRS1:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) 119 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[t2SUBri1]] 120 ; CHECK-NEXT: {{ $}} 121 ; CHECK-NEXT: bb.3.for.body: 122 ; CHECK-NEXT: successors: %bb.4(0x04000000), %bb.3(0x7c000000) 123 ; CHECK-NEXT: {{ $}} 124 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %10, %bb.3 125 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gprnopc = PHI [[COPY3]], %bb.2, %12, %bb.3 126 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gprnopc = PHI [[COPY]], %bb.2, %14, %bb.3 127 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.2, %16, %bb.3 128 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %18, %bb.3 129 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %20, %bb.3 130 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %22, %bb.3 131 ; CHECK-NEXT: [[PHI7:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %24, %bb.3 132 ; CHECK-NEXT: [[PHI8:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %26, %bb.3 133 ; CHECK-NEXT: [[PHI9:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %28, %bb.3 134 ; CHECK-NEXT: [[PHI10:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %30, %bb.3 135 ; CHECK-NEXT: [[PHI11:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %32, %bb.3 136 ; CHECK-NEXT: [[PHI12:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %34, %bb.3 137 ; CHECK-NEXT: [[PHI13:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %36, %bb.3 138 ; CHECK-NEXT: [[PHI14:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %38, %bb.3 139 ; CHECK-NEXT: [[PHI15:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %40, %bb.3 140 ; CHECK-NEXT: [[PHI16:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %42, %bb.3 141 ; CHECK-NEXT: [[PHI17:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %44, %bb.3 142 ; CHECK-NEXT: [[PHI18:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %46, %bb.3 143 ; CHECK-NEXT: [[PHI19:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %48, %bb.3 144 ; CHECK-NEXT: [[PHI20:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %50, %bb.3 145 ; CHECK-NEXT: [[PHI21:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %52, %bb.3 146 ; CHECK-NEXT: [[PHI22:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.2, %54, %bb.3 147 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[PHI]], 4, 14 /* CC::al */, $noreg, $noreg 148 ; CHECK-NEXT: [[VLDRS2:%[0-9]+]]:spr = VLDRS [[PHI]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) 149 ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 4, 14 /* CC::al */, $noreg, $noreg 150 ; CHECK-NEXT: [[VLDRS3:%[0-9]+]]:spr = VLDRS [[PHI1]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) 151 ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg 152 ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS]], [[PHI3]], 14 /* CC::al */, $noreg 153 ; CHECK-NEXT: [[t2SUBri2:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 1, 14 /* CC::al */, $noreg, def $cpsr 154 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY [[t2SUBri2]] 155 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY [[t2ADDri1]] 156 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr = COPY [[t2ADDri]] 157 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:rgpr = COPY [[PHI4]] 158 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:rgpr = COPY [[PHI5]] 159 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:rgpr = COPY [[PHI6]] 160 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:rgpr = COPY [[PHI7]] 161 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:rgpr = COPY [[PHI8]] 162 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:rgpr = COPY [[PHI9]] 163 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:rgpr = COPY [[PHI10]] 164 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:rgpr = COPY [[PHI11]] 165 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:rgpr = COPY [[PHI12]] 166 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:rgpr = COPY [[PHI13]] 167 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:rgpr = COPY [[PHI14]] 168 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:rgpr = COPY [[PHI15]] 169 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:rgpr = COPY [[PHI16]] 170 ; CHECK-NEXT: [[COPY21:%[0-9]+]]:rgpr = COPY [[PHI17]] 171 ; CHECK-NEXT: [[COPY22:%[0-9]+]]:rgpr = COPY [[PHI18]] 172 ; CHECK-NEXT: [[COPY23:%[0-9]+]]:rgpr = COPY [[PHI19]] 173 ; CHECK-NEXT: [[COPY24:%[0-9]+]]:rgpr = COPY [[PHI20]] 174 ; CHECK-NEXT: [[COPY25:%[0-9]+]]:rgpr = COPY [[PHI21]] 175 ; CHECK-NEXT: [[COPY26:%[0-9]+]]:rgpr = COPY [[PHI22]] 176 ; CHECK-NEXT: t2Bcc %bb.3, 1 /* CC::ne */, $cpsr 177 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg 178 ; CHECK-NEXT: {{ $}} 179 ; CHECK-NEXT: bb.4.for.end: 180 ; CHECK-NEXT: [[PHI23:%[0-9]+]]:spr = PHI [[VLDRS]], %bb.1, [[VADDS]], %bb.3 181 ; CHECK-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS [[PHI23]], 14 /* CC::al */, $noreg 182 ; CHECK-NEXT: $r0 = COPY [[VMOVRS]] 183 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 184 bb.0.entry: 185 successors: %bb.1(0x50000000), %bb.4(0x30000000) 186 liveins: $r0, $r1, $r2 187 188 %13:gprnopc = COPY $r2 189 %12:gprnopc = COPY $r1 190 %11:gprnopc = COPY $r0 191 t2CMPri %13, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 192 t2Bcc %bb.1, 10 /* CC::ge */, $cpsr 193 194 bb.4: 195 successors: %bb.3(0x80000000) 196 197 %14:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) 198 t2B %bb.3, 14 /* CC::al */, $noreg 199 200 bb.1.for.body.preheader: 201 successors: %bb.2(0x80000000) 202 203 %16:rgpr = t2SUBri %12, 4, 14 /* CC::al */, $noreg, $noreg 204 %0:gpr = COPY %16 205 %17:rgpr = t2SUBri %11, 4, 14 /* CC::al */, $noreg, $noreg 206 %15:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) 207 %1:gpr = COPY %17 208 209 bb.2.for.body: 210 successors: %bb.3(0x04000000), %bb.2(0x7c000000) 211 212 %2:gprnopc = PHI %1, %bb.1, %9, %bb.2 213 %3:gprnopc = PHI %0, %bb.1, %8, %bb.2 214 %4:gprnopc = PHI %13, %bb.1, %7, %bb.2 215 %5:spr = PHI %15, %bb.1, %6, %bb.2 216 %101:gprnopc = PHI %1, %bb.1, %201, %bb.2 217 %102:gprnopc = PHI %1, %bb.1, %202, %bb.2 218 %103:gprnopc = PHI %1, %bb.1, %203, %bb.2 219 %104:gprnopc = PHI %1, %bb.1, %204, %bb.2 220 %105:gprnopc = PHI %1, %bb.1, %205, %bb.2 221 %106:gprnopc = PHI %1, %bb.1, %206, %bb.2 222 %107:gprnopc = PHI %1, %bb.1, %207, %bb.2 223 %108:gprnopc = PHI %1, %bb.1, %208, %bb.2 224 %109:gprnopc = PHI %1, %bb.1, %209, %bb.2 225 %110:gprnopc = PHI %1, %bb.1, %210, %bb.2 226 %111:gprnopc = PHI %1, %bb.1, %211, %bb.2 227 %112:gprnopc = PHI %1, %bb.1, %212, %bb.2 228 %113:gprnopc = PHI %1, %bb.1, %213, %bb.2 229 %114:gprnopc = PHI %1, %bb.1, %214, %bb.2 230 %115:gprnopc = PHI %1, %bb.1, %215, %bb.2 231 %116:gprnopc = PHI %1, %bb.1, %216, %bb.2 232 %117:gprnopc = PHI %1, %bb.1, %217, %bb.2 233 %118:gprnopc = PHI %1, %bb.1, %218, %bb.2 234 %119:gprnopc = PHI %1, %bb.1, %219, %bb.2 235 %18:rgpr = t2ADDri %2, 4, 14 /* CC::al */, $noreg, $noreg 236 %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) 237 %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg 238 %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) 239 %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg 240 %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg 241 %23:rgpr = t2SUBri %4, 1, 14 /* CC::al */, $noreg, def $cpsr 242 %7:gpr = COPY %23 243 %8:gpr = COPY %20 244 %9:gpr = COPY %18 245 %201:rgpr = COPY %101 246 %202:rgpr = COPY %102 247 %203:rgpr = COPY %103 248 %204:rgpr = COPY %104 249 %205:rgpr = COPY %105 250 %206:rgpr = COPY %106 251 %207:rgpr = COPY %107 252 %208:rgpr = COPY %108 253 %209:rgpr = COPY %109 254 %210:rgpr = COPY %110 255 %211:rgpr = COPY %111 256 %212:rgpr = COPY %112 257 %213:rgpr = COPY %113 258 %214:rgpr = COPY %114 259 %215:rgpr = COPY %115 260 %216:rgpr = COPY %116 261 %217:rgpr = COPY %117 262 %218:rgpr = COPY %118 263 %219:rgpr = COPY %119 264 t2Bcc %bb.2, 1 /* CC::ne */, $cpsr 265 t2B %bb.3, 14 /* CC::al */, $noreg 266 267 bb.3.for.end: 268 %10:spr = PHI %14, %bb.4, %6, %bb.2 269 %24:gpr = VMOVRS %10, 14 /* CC::al */, $noreg 270 $r0 = COPY %24 271 tBX_RET 14 /* CC::al */, $noreg, implicit $r0 272 273 274... 275--- 276name: low_pressure 277alignment: 2 278tracksRegLiveness: true 279constants: 280 - id: 0 281 value: 'float 0.000000e+00' 282 alignment: 4 283 isTargetSpecific: false 284body: | 285 ; CHECK-LABEL: name: low_pressure 286 ; CHECK: bb.0.entry: 287 ; CHECK-NEXT: successors: %bb.2(0x50000000), %bb.1(0x30000000) 288 ; CHECK-NEXT: liveins: $r0, $r1, $r2 289 ; CHECK-NEXT: {{ $}} 290 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r2 291 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1 292 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnopc = COPY $r0 293 ; CHECK-NEXT: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 294 ; CHECK-NEXT: t2Bcc %bb.2, 10 /* CC::ge */, $cpsr 295 ; CHECK-NEXT: {{ $}} 296 ; CHECK-NEXT: bb.1: 297 ; CHECK-NEXT: successors: %bb.4(0x80000000) 298 ; CHECK-NEXT: {{ $}} 299 ; CHECK-NEXT: [[VLDRS:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) 300 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg 301 ; CHECK-NEXT: {{ $}} 302 ; CHECK-NEXT: bb.2.for.body.preheader: 303 ; CHECK-NEXT: successors: %bb.5(0x80000000) 304 ; CHECK-NEXT: {{ $}} 305 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[COPY1]], 4, 14 /* CC::al */, $noreg, $noreg 306 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprnopc = COPY [[t2SUBri]] 307 ; CHECK-NEXT: [[t2SUBri1:%[0-9]+]]:rgpr = t2SUBri [[COPY2]], 4, 14 /* CC::al */, $noreg, $noreg 308 ; CHECK-NEXT: [[VLDRS1:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) 309 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprnopc = COPY [[t2SUBri1]] 310 ; CHECK-NEXT: {{ $}} 311 ; CHECK-NEXT: bb.5.for.body: 312 ; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.9(0x40000000) 313 ; CHECK-NEXT: {{ $}} 314 ; CHECK-NEXT: [[t2SUBri2:%[0-9]+]]:rgpr = t2SUBri [[COPY]], 1, 14 /* CC::al */, $noreg, def $cpsr 315 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprnopc = COPY [[t2SUBri2]] 316 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:rgpr = COPY [[COPY4]] 317 ; CHECK-NEXT: dead %66:rgpr = COPY [[COPY4]] 318 ; CHECK-NEXT: dead %67:rgpr = COPY [[COPY4]] 319 ; CHECK-NEXT: dead %68:rgpr = COPY [[COPY4]] 320 ; CHECK-NEXT: dead %69:rgpr = COPY [[COPY4]] 321 ; CHECK-NEXT: dead %70:rgpr = COPY [[COPY4]] 322 ; CHECK-NEXT: dead %71:rgpr = COPY [[COPY4]] 323 ; CHECK-NEXT: dead %72:rgpr = COPY [[COPY4]] 324 ; CHECK-NEXT: dead %73:rgpr = COPY [[COPY4]] 325 ; CHECK-NEXT: dead %74:rgpr = COPY [[COPY4]] 326 ; CHECK-NEXT: dead %75:rgpr = COPY [[COPY4]] 327 ; CHECK-NEXT: dead %76:rgpr = COPY [[COPY4]] 328 ; CHECK-NEXT: dead %77:rgpr = COPY [[COPY4]] 329 ; CHECK-NEXT: dead %78:rgpr = COPY [[COPY4]] 330 ; CHECK-NEXT: dead %79:rgpr = COPY [[COPY4]] 331 ; CHECK-NEXT: dead %80:rgpr = COPY [[COPY4]] 332 ; CHECK-NEXT: dead %81:rgpr = COPY [[COPY4]] 333 ; CHECK-NEXT: dead %82:rgpr = COPY [[COPY4]] 334 ; CHECK-NEXT: dead %83:rgpr = COPY [[COPY4]] 335 ; CHECK-NEXT: t2Bcc %bb.9, 0 /* CC::eq */, $cpsr 336 ; CHECK-NEXT: t2B %bb.6, 14 /* CC::al */, $noreg 337 ; CHECK-NEXT: {{ $}} 338 ; CHECK-NEXT: bb.6.for.body: 339 ; CHECK-NEXT: successors: %bb.7(0x80000000), %bb.8(0x00000000) 340 ; CHECK-NEXT: {{ $}} 341 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY4]], 4, 14 /* CC::al */, $noreg, $noreg 342 ; CHECK-NEXT: [[VLDRS2:%[0-9]+]]:spr = VLDRS [[COPY4]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) 343 ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[COPY3]], 4, 14 /* CC::al */, $noreg, $noreg 344 ; CHECK-NEXT: [[VLDRS3:%[0-9]+]]:spr = VLDRS [[COPY3]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) 345 ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg 346 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr = COPY [[t2ADDri1]] 347 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY [[t2ADDri]] 348 ; CHECK-NEXT: [[t2SUBri3:%[0-9]+]]:rgpr = t2SUBri [[COPY5]], 1, 14 /* CC::al */, $noreg, def $cpsr 349 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:gpr = COPY [[t2SUBri3]] 350 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:rgpr = COPY [[COPY6]] 351 ; CHECK-NEXT: dead %94:rgpr = COPY [[COPY6]] 352 ; CHECK-NEXT: dead %95:rgpr = COPY [[COPY6]] 353 ; CHECK-NEXT: dead %96:rgpr = COPY [[COPY6]] 354 ; CHECK-NEXT: dead %97:rgpr = COPY [[COPY6]] 355 ; CHECK-NEXT: dead %98:rgpr = COPY [[COPY6]] 356 ; CHECK-NEXT: dead %99:rgpr = COPY [[COPY6]] 357 ; CHECK-NEXT: dead %100:rgpr = COPY [[COPY6]] 358 ; CHECK-NEXT: dead %101:rgpr = COPY [[COPY6]] 359 ; CHECK-NEXT: dead %102:rgpr = COPY [[COPY6]] 360 ; CHECK-NEXT: dead %103:rgpr = COPY [[COPY6]] 361 ; CHECK-NEXT: dead %104:rgpr = COPY [[COPY6]] 362 ; CHECK-NEXT: dead %105:rgpr = COPY [[COPY6]] 363 ; CHECK-NEXT: dead %106:rgpr = COPY [[COPY6]] 364 ; CHECK-NEXT: dead %107:rgpr = COPY [[COPY6]] 365 ; CHECK-NEXT: dead %108:rgpr = COPY [[COPY6]] 366 ; CHECK-NEXT: dead %109:rgpr = COPY [[COPY6]] 367 ; CHECK-NEXT: dead %110:rgpr = COPY [[COPY6]] 368 ; CHECK-NEXT: dead %111:rgpr = COPY [[COPY6]] 369 ; CHECK-NEXT: t2Bcc %bb.8, 0 /* CC::eq */, $cpsr 370 ; CHECK-NEXT: t2B %bb.7, 14 /* CC::al */, $noreg 371 ; CHECK-NEXT: {{ $}} 372 ; CHECK-NEXT: bb.7.for.body: 373 ; CHECK-NEXT: successors: %bb.8(0x04000000), %bb.7(0x7c000000) 374 ; CHECK-NEXT: {{ $}} 375 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gprnopc = PHI [[COPY8]], %bb.6, %116, %bb.7 376 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gprnopc = PHI [[COPY7]], %bb.6, %117, %bb.7 377 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gprnopc = PHI [[COPY9]], %bb.6, %140, %bb.7 378 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, %137, %bb.7 379 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:gprnopc = PHI [[COPY10]], %bb.6, %139, %bb.7 380 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, %118, %bb.7 381 ; CHECK-NEXT: [[VLDRS4:%[0-9]+]]:spr = VLDRS [[PHI1]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4) 382 ; CHECK-NEXT: [[VLDRS5:%[0-9]+]]:spr = VLDRS [[PHI]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) 383 ; CHECK-NEXT: [[t2ADDri2:%[0-9]+]]:rgpr = t2ADDri [[PHI]], 4, 14 /* CC::al */, $noreg, $noreg 384 ; CHECK-NEXT: [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 4, 14 /* CC::al */, $noreg, $noreg 385 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:gpr = COPY [[t2ADDri2]] 386 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:gpr = COPY [[t2ADDri3]] 387 ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS4]], [[VLDRS5]], 14 /* CC::al */, $noreg 388 ; CHECK-NEXT: dead %119:rgpr = COPY [[PHI4]] 389 ; CHECK-NEXT: dead %120:rgpr = COPY [[PHI4]] 390 ; CHECK-NEXT: dead %121:rgpr = COPY [[PHI4]] 391 ; CHECK-NEXT: dead %122:rgpr = COPY [[PHI4]] 392 ; CHECK-NEXT: dead %123:rgpr = COPY [[PHI4]] 393 ; CHECK-NEXT: dead %124:rgpr = COPY [[PHI4]] 394 ; CHECK-NEXT: dead %125:rgpr = COPY [[PHI4]] 395 ; CHECK-NEXT: dead %126:rgpr = COPY [[PHI4]] 396 ; CHECK-NEXT: dead %127:rgpr = COPY [[PHI4]] 397 ; CHECK-NEXT: dead %128:rgpr = COPY [[PHI4]] 398 ; CHECK-NEXT: dead %129:rgpr = COPY [[PHI4]] 399 ; CHECK-NEXT: dead %130:rgpr = COPY [[PHI4]] 400 ; CHECK-NEXT: dead %131:rgpr = COPY [[PHI4]] 401 ; CHECK-NEXT: dead %132:rgpr = COPY [[PHI4]] 402 ; CHECK-NEXT: dead %133:rgpr = COPY [[PHI4]] 403 ; CHECK-NEXT: dead %134:rgpr = COPY [[PHI4]] 404 ; CHECK-NEXT: dead %135:rgpr = COPY [[PHI4]] 405 ; CHECK-NEXT: dead %136:rgpr = COPY [[PHI4]] 406 ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI5]], [[PHI3]], 14 /* CC::al */, $noreg 407 ; CHECK-NEXT: [[t2SUBri4:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 1, 14 /* CC::al */, $noreg, def $cpsr 408 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:rgpr = COPY [[PHI4]] 409 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:gpr = COPY [[t2SUBri4]] 410 ; CHECK-NEXT: t2Bcc %bb.7, 1 /* CC::ne */, $cpsr 411 ; CHECK-NEXT: t2B %bb.8, 14 /* CC::al */, $noreg 412 ; CHECK-NEXT: {{ $}} 413 ; CHECK-NEXT: bb.8: 414 ; CHECK-NEXT: successors: %bb.9(0x80000000) 415 ; CHECK-NEXT: {{ $}} 416 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:gprnopc = PHI [[COPY8]], %bb.6, [[COPY11]], %bb.7 417 ; CHECK-NEXT: [[PHI7:%[0-9]+]]:gprnopc = PHI [[COPY7]], %bb.6, [[COPY12]], %bb.7 418 ; CHECK-NEXT: [[PHI8:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, [[VADDS]], %bb.7 419 ; CHECK-NEXT: [[PHI9:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[VMULS1]], %bb.7 420 ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI9]], [[PHI8]], 14 /* CC::al */, $noreg 421 ; CHECK-NEXT: {{ $}} 422 ; CHECK-NEXT: bb.9: 423 ; CHECK-NEXT: successors: %bb.4(0x80000000) 424 ; CHECK-NEXT: {{ $}} 425 ; CHECK-NEXT: [[PHI10:%[0-9]+]]:gprnopc = PHI [[COPY4]], %bb.5, [[PHI6]], %bb.8 426 ; CHECK-NEXT: [[PHI11:%[0-9]+]]:gprnopc = PHI [[COPY3]], %bb.5, [[PHI7]], %bb.8 427 ; CHECK-NEXT: [[PHI12:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS1]], %bb.8 428 ; CHECK-NEXT: [[VLDRS6:%[0-9]+]]:spr = VLDRS [[PHI10]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) 429 ; CHECK-NEXT: [[VLDRS7:%[0-9]+]]:spr = VLDRS [[PHI11]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4) 430 ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS7]], [[VLDRS6]], 14 /* CC::al */, $noreg 431 ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS2]], [[PHI12]], 14 /* CC::al */, $noreg 432 ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg 433 ; CHECK-NEXT: {{ $}} 434 ; CHECK-NEXT: bb.4.for.end: 435 ; CHECK-NEXT: [[PHI13:%[0-9]+]]:spr = PHI [[VLDRS]], %bb.1, [[VADDS2]], %bb.9 436 ; CHECK-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS [[PHI13]], 14 /* CC::al */, $noreg 437 ; CHECK-NEXT: $r0 = COPY [[VMOVRS]] 438 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 439 bb.0.entry: 440 successors: %bb.1(0x50000000), %bb.4(0x30000000) 441 liveins: $r0, $r1, $r2 442 443 %13:gprnopc = COPY $r2 444 %12:gprnopc = COPY $r1 445 %11:gprnopc = COPY $r0 446 t2CMPri %13, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 447 t2Bcc %bb.1, 10 /* CC::ge */, $cpsr 448 449 bb.4: 450 successors: %bb.3(0x80000000) 451 452 %14:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) 453 t2B %bb.3, 14 /* CC::al */, $noreg 454 455 bb.1.for.body.preheader: 456 successors: %bb.2(0x80000000) 457 458 %16:rgpr = t2SUBri %12, 4, 14 /* CC::al */, $noreg, $noreg 459 %0:gpr = COPY %16 460 %17:rgpr = t2SUBri %11, 4, 14 /* CC::al */, $noreg, $noreg 461 %15:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) 462 %1:gpr = COPY %17 463 464 bb.2.for.body: 465 successors: %bb.3(0x04000000), %bb.2(0x7c000000) 466 467 %2:gprnopc = PHI %1, %bb.1, %9, %bb.2 468 %3:gprnopc = PHI %0, %bb.1, %8, %bb.2 469 %4:gprnopc = PHI %13, %bb.1, %7, %bb.2 470 %5:spr = PHI %15, %bb.1, %6, %bb.2 471 %101:gprnopc = PHI %1, %bb.1, %201, %bb.2 472 %102:gprnopc = PHI %1, %bb.1, %201, %bb.2 473 %103:gprnopc = PHI %1, %bb.1, %201, %bb.2 474 %104:gprnopc = PHI %1, %bb.1, %201, %bb.2 475 %105:gprnopc = PHI %1, %bb.1, %201, %bb.2 476 %106:gprnopc = PHI %1, %bb.1, %201, %bb.2 477 %107:gprnopc = PHI %1, %bb.1, %201, %bb.2 478 %108:gprnopc = PHI %1, %bb.1, %201, %bb.2 479 %109:gprnopc = PHI %1, %bb.1, %201, %bb.2 480 %110:gprnopc = PHI %1, %bb.1, %201, %bb.2 481 %111:gprnopc = PHI %1, %bb.1, %201, %bb.2 482 %112:gprnopc = PHI %1, %bb.1, %201, %bb.2 483 %113:gprnopc = PHI %1, %bb.1, %201, %bb.2 484 %114:gprnopc = PHI %1, %bb.1, %201, %bb.2 485 %115:gprnopc = PHI %1, %bb.1, %201, %bb.2 486 %116:gprnopc = PHI %1, %bb.1, %201, %bb.2 487 %117:gprnopc = PHI %1, %bb.1, %201, %bb.2 488 %118:gprnopc = PHI %1, %bb.1, %201, %bb.2 489 %119:gprnopc = PHI %1, %bb.1, %201, %bb.2 490 %18:rgpr = t2ADDri %2, 4, 14 /* CC::al */, $noreg, $noreg 491 %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) 492 %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg 493 %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) 494 %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg 495 %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg 496 %23:rgpr = t2SUBri %4, 1, 14 /* CC::al */, $noreg, def $cpsr 497 %7:gpr = COPY %23 498 %8:gpr = COPY %20 499 %9:gpr = COPY %18 500 %201:rgpr = COPY %101 501 %202:rgpr = COPY %101 502 %203:rgpr = COPY %101 503 %204:rgpr = COPY %101 504 %205:rgpr = COPY %101 505 %206:rgpr = COPY %101 506 %207:rgpr = COPY %101 507 %208:rgpr = COPY %101 508 %209:rgpr = COPY %101 509 %210:rgpr = COPY %101 510 %211:rgpr = COPY %101 511 %212:rgpr = COPY %101 512 %213:rgpr = COPY %101 513 %214:rgpr = COPY %101 514 %215:rgpr = COPY %101 515 %216:rgpr = COPY %101 516 %217:rgpr = COPY %101 517 %218:rgpr = COPY %101 518 %219:rgpr = COPY %101 519 t2Bcc %bb.2, 1 /* CC::ne */, $cpsr 520 t2B %bb.3, 14 /* CC::al */, $noreg 521 522 bb.3.for.end: 523 %10:spr = PHI %14, %bb.4, %6, %bb.2 524 %24:gpr = VMOVRS %10, 14 /* CC::al */, $noreg 525 $r0 = COPY %24 526 tBX_RET 14 /* CC::al */, $noreg, implicit $r0 527 528... 529