1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - -verify-machineinstrs | FileCheck %s 3 4--- | 5 define ptr @t2LDRi12(ptr %x, i32 %y) { unreachable } 6 define ptr @t2LDRHi12(ptr %x, i32 %y) { unreachable } 7 define ptr @t2LDRSHi12(ptr %x, i32 %y) { unreachable } 8 define ptr @t2LDRBi12(ptr %x, i32 %y) { unreachable } 9 define ptr @t2LDRSBi12(ptr %x, i32 %y) { unreachable } 10 define ptr @t2STRi12(ptr %x, i32 %y) { unreachable } 11 define ptr @t2STRHi12(ptr %x, i32 %y) { unreachable } 12 define ptr @t2STRBi12(ptr %x, i32 %y) { unreachable } 13 14 define ptr @storedadd(ptr %x, i32 %y) { unreachable } 15 define ptr @minsize2(ptr %x, i32 %y) minsize optsize { unreachable } 16 define ptr @minsize3(ptr %x, i32 %y) minsize optsize { unreachable } 17 18 define ptr @t2LDRi12_posoff(ptr %x, i32 %y) { unreachable } 19 define ptr @t2LDRHi12_posoff(ptr %x, i32 %y) { unreachable } 20 define ptr @t2LDRBi12_posoff(ptr %x, i32 %y) { unreachable } 21 define ptr @t2STRi12_posoff(ptr %x, i32 %y) { unreachable } 22 define ptr @t2STRHi12_posoff(ptr %x, i32 %y) { unreachable } 23 define ptr @t2STRBi12_posoff(ptr %x, i32 %y) { unreachable } 24 define ptr @t2LDRi12_negoff(ptr %x, i32 %y) { unreachable } 25 define ptr @t2LDRHi12_negoff(ptr %x, i32 %y) { unreachable } 26 define ptr @t2LDRBi12_negoff(ptr %x, i32 %y) { unreachable } 27 define ptr @t2STRi12_negoff(ptr %x, i32 %y) { unreachable } 28 define ptr @t2STRHi12_negoff(ptr %x, i32 %y) { unreachable } 29 define ptr @t2STRBi12_negoff(ptr %x, i32 %y) { unreachable } 30 31... 32--- 33name: t2LDRi12 34tracksRegLiveness: true 35registers: 36 - { id: 0, class: gprnopc, preferred-register: '' } 37 - { id: 1, class: rgpr, preferred-register: '' } 38 - { id: 2, class: rgpr, preferred-register: '' } 39liveins: 40 - { reg: '$r0', virtual-reg: '%0' } 41body: | 42 bb.0: 43 liveins: $r0 44 45 ; CHECK-LABEL: name: t2LDRi12 46 ; CHECK: liveins: $r0 47 ; CHECK-NEXT: {{ $}} 48 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 49 ; CHECK-NEXT: [[t2LDRi12_:%[0-9]+]]:rgpr = t2LDRi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32)) 50 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 51 ; CHECK-NEXT: $r0 = COPY [[t2ADDri]] 52 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 53 %0:gprnopc = COPY $r0 54 %1:rgpr = t2LDRi12 %0, 0, 14, $noreg :: (load (s32), align 4) 55 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 56 $r0 = COPY %2 57 tBX_RET 14, $noreg, implicit $r0 58 59... 60--- 61name: t2LDRHi12 62tracksRegLiveness: true 63registers: 64 - { id: 0, class: gprnopc, preferred-register: '' } 65 - { id: 1, class: rgpr, preferred-register: '' } 66 - { id: 2, class: rgpr, preferred-register: '' } 67liveins: 68 - { reg: '$r0', virtual-reg: '%0' } 69body: | 70 bb.0: 71 liveins: $r0 72 73 ; CHECK-LABEL: name: t2LDRHi12 74 ; CHECK: liveins: $r0 75 ; CHECK-NEXT: {{ $}} 76 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 77 ; CHECK-NEXT: [[t2LDRH_POST:%[0-9]+]]:rgpr, [[t2LDRH_POST1:%[0-9]+]]:rgpr = t2LDRH_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load (s32)) 78 ; CHECK-NEXT: $r0 = COPY [[t2LDRH_POST1]] 79 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 80 %0:gprnopc = COPY $r0 81 %1:rgpr = t2LDRHi12 %0, 0, 14, $noreg :: (load (s32), align 4) 82 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 83 $r0 = COPY %2 84 tBX_RET 14, $noreg, implicit $r0 85 86... 87--- 88name: t2LDRSHi12 89tracksRegLiveness: true 90registers: 91 - { id: 0, class: gprnopc, preferred-register: '' } 92 - { id: 1, class: rgpr, preferred-register: '' } 93 - { id: 2, class: rgpr, preferred-register: '' } 94liveins: 95 - { reg: '$r0', virtual-reg: '%0' } 96body: | 97 bb.0: 98 liveins: $r0 99 100 ; CHECK-LABEL: name: t2LDRSHi12 101 ; CHECK: liveins: $r0 102 ; CHECK-NEXT: {{ $}} 103 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 104 ; CHECK-NEXT: [[t2LDRSH_POST:%[0-9]+]]:rgpr, [[t2LDRSH_POST1:%[0-9]+]]:rgpr = t2LDRSH_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load (s32)) 105 ; CHECK-NEXT: $r0 = COPY [[t2LDRSH_POST1]] 106 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 107 %0:gprnopc = COPY $r0 108 %1:rgpr = t2LDRSHi12 %0, 0, 14, $noreg :: (load (s32), align 4) 109 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 110 $r0 = COPY %2 111 tBX_RET 14, $noreg, implicit $r0 112 113... 114--- 115name: t2LDRBi12 116tracksRegLiveness: true 117registers: 118 - { id: 0, class: gprnopc, preferred-register: '' } 119 - { id: 1, class: rgpr, preferred-register: '' } 120 - { id: 2, class: rgpr, preferred-register: '' } 121liveins: 122 - { reg: '$r0', virtual-reg: '%0' } 123body: | 124 bb.0: 125 liveins: $r0 126 127 ; CHECK-LABEL: name: t2LDRBi12 128 ; CHECK: liveins: $r0 129 ; CHECK-NEXT: {{ $}} 130 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 131 ; CHECK-NEXT: [[t2LDRB_POST:%[0-9]+]]:rgpr, [[t2LDRB_POST1:%[0-9]+]]:rgpr = t2LDRB_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load (s32)) 132 ; CHECK-NEXT: $r0 = COPY [[t2LDRB_POST1]] 133 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 134 %0:gprnopc = COPY $r0 135 %1:rgpr = t2LDRBi12 %0, 0, 14, $noreg :: (load (s32), align 4) 136 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 137 $r0 = COPY %2 138 tBX_RET 14, $noreg, implicit $r0 139 140... 141--- 142name: t2LDRSBi12 143tracksRegLiveness: true 144registers: 145 - { id: 0, class: gprnopc, preferred-register: '' } 146 - { id: 1, class: rgpr, preferred-register: '' } 147 - { id: 2, class: rgpr, preferred-register: '' } 148liveins: 149 - { reg: '$r0', virtual-reg: '%0' } 150body: | 151 bb.0: 152 liveins: $r0 153 154 ; CHECK-LABEL: name: t2LDRSBi12 155 ; CHECK: liveins: $r0 156 ; CHECK-NEXT: {{ $}} 157 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 158 ; CHECK-NEXT: [[t2LDRSB_POST:%[0-9]+]]:rgpr, [[t2LDRSB_POST1:%[0-9]+]]:rgpr = t2LDRSB_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load (s32)) 159 ; CHECK-NEXT: $r0 = COPY [[t2LDRSB_POST1]] 160 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 161 %0:gprnopc = COPY $r0 162 %1:rgpr = t2LDRSBi12 %0, 0, 14, $noreg :: (load (s32), align 4) 163 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 164 $r0 = COPY %2 165 tBX_RET 14, $noreg, implicit $r0 166 167... 168--- 169name: t2STRi12 170tracksRegLiveness: true 171registers: 172 - { id: 0, class: gprnopc, preferred-register: '' } 173 - { id: 1, class: rgpr, preferred-register: '' } 174 - { id: 2, class: rgpr, preferred-register: '' } 175liveins: 176 - { reg: '$r0', virtual-reg: '%0' } 177 - { reg: '$r1', virtual-reg: '%1' } 178body: | 179 bb.0: 180 liveins: $r0, $r1 181 182 ; CHECK-LABEL: name: t2STRi12 183 ; CHECK: liveins: $r0, $r1 184 ; CHECK-NEXT: {{ $}} 185 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 186 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 187 ; CHECK-NEXT: t2STRi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32)) 188 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 189 ; CHECK-NEXT: $r0 = COPY [[t2ADDri]] 190 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 191 %0:gprnopc = COPY $r0 192 %1:rgpr = COPY $r1 193 t2STRi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4) 194 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 195 $r0 = COPY %2 196 tBX_RET 14, $noreg, implicit $r0 197 198... 199--- 200name: t2STRHi12 201tracksRegLiveness: true 202registers: 203 - { id: 0, class: gprnopc, preferred-register: '' } 204 - { id: 1, class: rgpr, preferred-register: '' } 205 - { id: 2, class: rgpr, preferred-register: '' } 206liveins: 207 - { reg: '$r0', virtual-reg: '%0' } 208 - { reg: '$r1', virtual-reg: '%1' } 209body: | 210 bb.0: 211 liveins: $r0, $r1 212 213 ; CHECK-LABEL: name: t2STRHi12 214 ; CHECK: liveins: $r0, $r1 215 ; CHECK-NEXT: {{ $}} 216 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 217 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 218 ; CHECK-NEXT: early-clobber %2:rgpr = t2STRH_POST [[COPY1]], [[COPY]], 32, 14 /* CC::al */, $noreg :: (store (s32)) 219 ; CHECK-NEXT: $r0 = COPY %2 220 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 221 %0:gprnopc = COPY $r0 222 %1:rgpr = COPY $r1 223 t2STRHi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4) 224 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 225 $r0 = COPY %2 226 tBX_RET 14, $noreg, implicit $r0 227 228... 229--- 230name: t2STRBi12 231tracksRegLiveness: true 232registers: 233 - { id: 0, class: gprnopc, preferred-register: '' } 234 - { id: 1, class: rgpr, preferred-register: '' } 235 - { id: 2, class: rgpr, preferred-register: '' } 236liveins: 237 - { reg: '$r0', virtual-reg: '%0' } 238 - { reg: '$r1', virtual-reg: '%1' } 239body: | 240 bb.0: 241 liveins: $r0, $r1 242 243 ; CHECK-LABEL: name: t2STRBi12 244 ; CHECK: liveins: $r0, $r1 245 ; CHECK-NEXT: {{ $}} 246 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 247 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 248 ; CHECK-NEXT: early-clobber %2:rgpr = t2STRB_POST [[COPY1]], [[COPY]], 32, 14 /* CC::al */, $noreg :: (store (s32)) 249 ; CHECK-NEXT: $r0 = COPY %2 250 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 251 %0:gprnopc = COPY $r0 252 %1:rgpr = COPY $r1 253 t2STRBi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4) 254 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 255 $r0 = COPY %2 256 tBX_RET 14, $noreg, implicit $r0 257 258... 259--- 260name: storedadd 261tracksRegLiveness: true 262registers: 263 - { id: 0, class: gprnopc, preferred-register: '' } 264 - { id: 1, class: rgpr, preferred-register: '' } 265liveins: 266 - { reg: '$r0', virtual-reg: '%0' } 267body: | 268 bb.0: 269 liveins: $r0 270 271 ; CHECK-LABEL: name: storedadd 272 ; CHECK: liveins: $r0 273 ; CHECK-NEXT: {{ $}} 274 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 275 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 276 ; CHECK-NEXT: t2STRi12 [[t2ADDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32)) 277 ; CHECK-NEXT: $r0 = COPY [[t2ADDri]] 278 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 279 %0:gprnopc = COPY $r0 280 %1:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 281 t2STRi12 %1, %0, 0, 14, $noreg :: (store (s32), align 4) 282 $r0 = COPY %1 283 tBX_RET 14, $noreg, implicit $r0 284 285... 286--- 287name: minsize2 288tracksRegLiveness: true 289registers: 290 - { id: 0, class: gprnopc, preferred-register: '' } 291 - { id: 1, class: rgpr, preferred-register: '' } 292 - { id: 2, class: rgpr, preferred-register: '' } 293 - { id: 3, class: rgpr, preferred-register: '' } 294liveins: 295 - { reg: '$r0', virtual-reg: '%0' } 296body: | 297 bb.0: 298 liveins: $r0 299 300 ; CHECK-LABEL: name: minsize2 301 ; CHECK: liveins: $r0 302 ; CHECK-NEXT: {{ $}} 303 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 304 ; CHECK-NEXT: [[t2LDRB_POST:%[0-9]+]]:rgpr, [[t2LDRB_POST1:%[0-9]+]]:rgpr = t2LDRB_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load (s32)) 305 ; CHECK-NEXT: [[t2LDRBi8_:%[0-9]+]]:rgpr = t2LDRBi8 [[t2LDRB_POST1]], -30, 14 /* CC::al */, $noreg :: (load (s32)) 306 ; CHECK-NEXT: $r0 = COPY [[t2LDRB_POST1]] 307 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 308 %0:gprnopc = COPY $r0 309 %1:rgpr = t2LDRBi12 %0, 0, 14, $noreg :: (load (s32), align 4) 310 %3:rgpr = t2LDRBi12 %0, 2, 14, $noreg :: (load (s32), align 4) 311 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 312 $r0 = COPY %2 313 tBX_RET 14, $noreg, implicit $r0 314 315... 316--- 317name: minsize3 318tracksRegLiveness: true 319registers: 320 - { id: 0, class: gprnopc, preferred-register: '' } 321 - { id: 1, class: rgpr, preferred-register: '' } 322 - { id: 2, class: rgpr, preferred-register: '' } 323 - { id: 3, class: rgpr, preferred-register: '' } 324 - { id: 4, class: rgpr, preferred-register: '' } 325liveins: 326 - { reg: '$r0', virtual-reg: '%0' } 327body: | 328 bb.0: 329 liveins: $r0 330 331 ; CHECK-LABEL: name: minsize3 332 ; CHECK: liveins: $r0 333 ; CHECK-NEXT: {{ $}} 334 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 335 ; CHECK-NEXT: [[t2LDRBi12_:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32)) 336 ; CHECK-NEXT: [[t2LDRBi12_1:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 2, 14 /* CC::al */, $noreg :: (load (s32)) 337 ; CHECK-NEXT: [[t2LDRBi12_2:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 4, 14 /* CC::al */, $noreg :: (load (s32)) 338 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 339 ; CHECK-NEXT: $r0 = COPY [[t2ADDri]] 340 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 341 %0:gprnopc = COPY $r0 342 %1:rgpr = t2LDRBi12 %0, 0, 14, $noreg :: (load (s32), align 4) 343 %3:rgpr = t2LDRBi12 %0, 2, 14, $noreg :: (load (s32), align 4) 344 %4:rgpr = t2LDRBi12 %0, 4, 14, $noreg :: (load (s32), align 4) 345 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 346 $r0 = COPY %2 347 tBX_RET 14, $noreg, implicit $r0 348 349... 350--- 351name: t2LDRi12_posoff 352tracksRegLiveness: true 353registers: 354 - { id: 0, class: gprnopc, preferred-register: '' } 355 - { id: 1, class: rgpr, preferred-register: '' } 356 - { id: 2, class: rgpr, preferred-register: '' } 357 - { id: 3, class: rgpr, preferred-register: '' } 358 - { id: 4, class: rgpr, preferred-register: '' } 359liveins: 360 - { reg: '$r0', virtual-reg: '%0' } 361body: | 362 bb.0: 363 liveins: $r0 364 365 ; CHECK-LABEL: name: t2LDRi12_posoff 366 ; CHECK: liveins: $r0 367 ; CHECK-NEXT: {{ $}} 368 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 369 ; CHECK-NEXT: [[t2LDRDi8_:%[0-9]+]]:rgpr, [[t2LDRDi8_1:%[0-9]+]]:rgpr = t2LDRDi8 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32)) 370 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 371 ; CHECK-NEXT: [[t2LDRi8_:%[0-9]+]]:rgpr = t2LDRi8 [[COPY]], -8, 14 /* CC::al */, $noreg :: (load (s32)) 372 ; CHECK-NEXT: $r0 = COPY [[t2ADDri]] 373 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 374 %0:gprnopc = COPY $r0 375 %1:rgpr = t2LDRi12 %0, 0, 14, $noreg :: (load (s32), align 4) 376 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 377 %3:rgpr = t2LDRi12 %0, 4, 14, $noreg :: (load (s32), align 4) 378 %4:rgpr = t2LDRi8 %0, -8, 14, $noreg :: (load (s32), align 4) 379 $r0 = COPY %2 380 tBX_RET 14, $noreg, implicit $r0 381 382... 383--- 384name: t2LDRHi12_posoff 385tracksRegLiveness: true 386registers: 387 - { id: 0, class: gprnopc, preferred-register: '' } 388 - { id: 1, class: rgpr, preferred-register: '' } 389 - { id: 2, class: rgpr, preferred-register: '' } 390 - { id: 3, class: rgpr, preferred-register: '' } 391 - { id: 4, class: rgpr, preferred-register: '' } 392 - { id: 5, class: rgpr, preferred-register: '' } 393liveins: 394 - { reg: '$r0', virtual-reg: '%0' } 395body: | 396 bb.0: 397 liveins: $r0 398 399 ; CHECK-LABEL: name: t2LDRHi12_posoff 400 ; CHECK: liveins: $r0 401 ; CHECK-NEXT: {{ $}} 402 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 403 ; CHECK-NEXT: [[t2LDRH_POST:%[0-9]+]]:rgpr, [[t2LDRH_POST1:%[0-9]+]]:rgpr = t2LDRH_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load (s32)) 404 ; CHECK-NEXT: [[t2LDRHi8_:%[0-9]+]]:rgpr = t2LDRHi8 [[t2LDRH_POST1]], -28, 14 /* CC::al */, $noreg :: (load (s32)) 405 ; CHECK-NEXT: [[t2LDRHi8_1:%[0-9]+]]:rgpr = t2LDRHi8 [[t2LDRH_POST1]], -40, 14 /* CC::al */, $noreg :: (load (s32)) 406 ; CHECK-NEXT: [[t2LDRSHi8_:%[0-9]+]]:rgpr = t2LDRSHi8 [[t2LDRH_POST1]], -20, 14 /* CC::al */, $noreg :: (load (s32)) 407 ; CHECK-NEXT: $r0 = COPY [[t2LDRH_POST1]] 408 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 409 %0:gprnopc = COPY $r0 410 %1:rgpr = t2LDRHi12 %0, 0, 14, $noreg :: (load (s32), align 4) 411 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 412 %3:rgpr = t2LDRHi12 %0, 4, 14, $noreg :: (load (s32), align 4) 413 %4:rgpr = t2LDRHi8 %0, -8, 14, $noreg :: (load (s32), align 4) 414 %5:rgpr = t2LDRSHi12 %0, 12, 14, $noreg :: (load (s32), align 4) 415 $r0 = COPY %2 416 tBX_RET 14, $noreg, implicit $r0 417 418... 419--- 420name: t2LDRBi12_posoff 421tracksRegLiveness: true 422registers: 423 - { id: 0, class: gprnopc, preferred-register: '' } 424 - { id: 1, class: rgpr, preferred-register: '' } 425 - { id: 2, class: rgpr, preferred-register: '' } 426 - { id: 3, class: rgpr, preferred-register: '' } 427 - { id: 4, class: rgpr, preferred-register: '' } 428 - { id: 5, class: rgpr, preferred-register: '' } 429liveins: 430 - { reg: '$r0', virtual-reg: '%0' } 431body: | 432 bb.0: 433 liveins: $r0 434 435 ; CHECK-LABEL: name: t2LDRBi12_posoff 436 ; CHECK: liveins: $r0 437 ; CHECK-NEXT: {{ $}} 438 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 439 ; CHECK-NEXT: [[t2LDRB_POST:%[0-9]+]]:rgpr, [[t2LDRB_POST1:%[0-9]+]]:rgpr = t2LDRB_POST [[COPY]], 32, 14 /* CC::al */, $noreg :: (load (s32)) 440 ; CHECK-NEXT: [[t2LDRBi8_:%[0-9]+]]:rgpr = t2LDRBi8 [[t2LDRB_POST1]], -28, 14 /* CC::al */, $noreg :: (load (s32)) 441 ; CHECK-NEXT: [[t2LDRBi8_1:%[0-9]+]]:rgpr = t2LDRBi8 [[t2LDRB_POST1]], -40, 14 /* CC::al */, $noreg :: (load (s32)) 442 ; CHECK-NEXT: [[t2LDRSBi8_:%[0-9]+]]:rgpr = t2LDRSBi8 [[t2LDRB_POST1]], -20, 14 /* CC::al */, $noreg :: (load (s32)) 443 ; CHECK-NEXT: $r0 = COPY [[t2LDRB_POST1]] 444 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 445 %0:gprnopc = COPY $r0 446 %1:rgpr = t2LDRBi12 %0, 0, 14, $noreg :: (load (s32), align 4) 447 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 448 %3:rgpr = t2LDRBi12 %0, 4, 14, $noreg :: (load (s32), align 4) 449 %4:rgpr = t2LDRBi8 %0, -8, 14, $noreg :: (load (s32), align 4) 450 %12:rgpr = t2LDRSBi12 %0, 12, 14, $noreg :: (load (s32), align 4) 451 $r0 = COPY %2 452 tBX_RET 14, $noreg, implicit $r0 453 454... 455--- 456name: t2STRi12_posoff 457tracksRegLiveness: true 458registers: 459 - { id: 0, class: gprnopc, preferred-register: '' } 460 - { id: 1, class: rgpr, preferred-register: '' } 461 - { id: 2, class: rgpr, preferred-register: '' } 462liveins: 463 - { reg: '$r0', virtual-reg: '%0' } 464 - { reg: '$r1', virtual-reg: '%1' } 465body: | 466 bb.0: 467 liveins: $r0, $r1 468 469 ; CHECK-LABEL: name: t2STRi12_posoff 470 ; CHECK: liveins: $r0, $r1 471 ; CHECK-NEXT: {{ $}} 472 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 473 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 474 ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 475 ; CHECK-NEXT: t2STRi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32)) 476 ; CHECK-NEXT: t2STRi12 [[COPY1]], [[COPY]], 4, 14 /* CC::al */, $noreg :: (store (s32)) 477 ; CHECK-NEXT: t2STRi8 [[COPY1]], [[COPY]], -8, 14 /* CC::al */, $noreg :: (store (s32)) 478 ; CHECK-NEXT: $r0 = COPY [[t2ADDri]] 479 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 480 %0:gprnopc = COPY $r0 481 %1:rgpr = COPY $r1 482 t2STRi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4) 483 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 484 t2STRi12 %1:rgpr, %0, 4, 14, $noreg :: (store (s32), align 4) 485 t2STRi8 %1:rgpr, %0, -8, 14, $noreg :: (store (s32), align 4) 486 $r0 = COPY %2 487 tBX_RET 14, $noreg, implicit $r0 488 489... 490--- 491name: t2STRHi12_posoff 492tracksRegLiveness: true 493registers: 494 - { id: 0, class: gprnopc, preferred-register: '' } 495 - { id: 1, class: rgpr, preferred-register: '' } 496 - { id: 2, class: rgpr, preferred-register: '' } 497liveins: 498 - { reg: '$r0', virtual-reg: '%0' } 499 - { reg: '$r1', virtual-reg: '%1' } 500body: | 501 bb.0: 502 liveins: $r0, $r1 503 504 ; CHECK-LABEL: name: t2STRHi12_posoff 505 ; CHECK: liveins: $r0, $r1 506 ; CHECK-NEXT: {{ $}} 507 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 508 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 509 ; CHECK-NEXT: early-clobber %2:rgpr = t2STRH_POST [[COPY1]], [[COPY]], 32, 14 /* CC::al */, $noreg :: (store (s32)) 510 ; CHECK-NEXT: t2STRHi8 [[COPY1]], %2, -28, 14 /* CC::al */, $noreg :: (store (s32)) 511 ; CHECK-NEXT: t2STRHi8 [[COPY1]], %2, -40, 14 /* CC::al */, $noreg :: (store (s32)) 512 ; CHECK-NEXT: $r0 = COPY %2 513 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 514 %0:gprnopc = COPY $r0 515 %1:rgpr = COPY $r1 516 t2STRHi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4) 517 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 518 t2STRHi12 %1:rgpr, %0, 4, 14, $noreg :: (store (s32), align 4) 519 t2STRHi8 %1:rgpr, %0, -8, 14, $noreg :: (store (s32), align 4) 520 $r0 = COPY %2 521 tBX_RET 14, $noreg, implicit $r0 522 523... 524--- 525name: t2STRBi12_posoff 526tracksRegLiveness: true 527registers: 528 - { id: 0, class: gprnopc, preferred-register: '' } 529 - { id: 1, class: rgpr, preferred-register: '' } 530 - { id: 2, class: rgpr, preferred-register: '' } 531liveins: 532 - { reg: '$r0', virtual-reg: '%0' } 533 - { reg: '$r1', virtual-reg: '%1' } 534body: | 535 bb.0: 536 liveins: $r0, $r1 537 538 ; CHECK-LABEL: name: t2STRBi12_posoff 539 ; CHECK: liveins: $r0, $r1 540 ; CHECK-NEXT: {{ $}} 541 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 542 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 543 ; CHECK-NEXT: early-clobber %2:rgpr = t2STRB_POST [[COPY1]], [[COPY]], 32, 14 /* CC::al */, $noreg :: (store (s32)) 544 ; CHECK-NEXT: t2STRBi8 [[COPY1]], %2, -28, 14 /* CC::al */, $noreg :: (store (s32)) 545 ; CHECK-NEXT: t2STRBi8 [[COPY1]], %2, -40, 14 /* CC::al */, $noreg :: (store (s32)) 546 ; CHECK-NEXT: $r0 = COPY %2 547 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 548 %0:gprnopc = COPY $r0 549 %1:rgpr = COPY $r1 550 t2STRBi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4) 551 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg 552 t2STRBi12 %1:rgpr, %0, 4, 14, $noreg :: (store (s32), align 4) 553 t2STRBi8 %1:rgpr, %0, -8, 14, $noreg :: (store (s32), align 4) 554 $r0 = COPY %2 555 tBX_RET 14, $noreg, implicit $r0 556 557... 558--- 559name: t2LDRi12_negoff 560tracksRegLiveness: true 561registers: 562 - { id: 0, class: gprnopc, preferred-register: '' } 563 - { id: 1, class: rgpr, preferred-register: '' } 564 - { id: 2, class: rgpr, preferred-register: '' } 565 - { id: 3, class: rgpr, preferred-register: '' } 566 - { id: 4, class: rgpr, preferred-register: '' } 567liveins: 568 - { reg: '$r0', virtual-reg: '%0' } 569body: | 570 bb.0: 571 liveins: $r0 572 573 ; CHECK-LABEL: name: t2LDRi12_negoff 574 ; CHECK: liveins: $r0 575 ; CHECK-NEXT: {{ $}} 576 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 577 ; CHECK-NEXT: [[t2LDRDi8_:%[0-9]+]]:rgpr, [[t2LDRDi8_1:%[0-9]+]]:rgpr = t2LDRDi8 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32)) 578 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 579 ; CHECK-NEXT: [[t2LDRi8_:%[0-9]+]]:rgpr = t2LDRi8 [[COPY]], -8, 14 /* CC::al */, $noreg :: (load (s32)) 580 ; CHECK-NEXT: $r0 = COPY [[t2SUBri]] 581 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 582 %0:gprnopc = COPY $r0 583 %1:rgpr = t2LDRi12 %0, 0, 14, $noreg :: (load (s32), align 4) 584 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg 585 %3:rgpr = t2LDRi12 %0, 4, 14, $noreg :: (load (s32), align 4) 586 %4:rgpr = t2LDRi8 %0, -8, 14, $noreg :: (load (s32), align 4) 587 $r0 = COPY %2 588 tBX_RET 14, $noreg, implicit $r0 589 590... 591--- 592name: t2LDRHi12_negoff 593tracksRegLiveness: true 594registers: 595 - { id: 0, class: gprnopc, preferred-register: '' } 596 - { id: 1, class: rgpr, preferred-register: '' } 597 - { id: 2, class: rgpr, preferred-register: '' } 598 - { id: 3, class: rgpr, preferred-register: '' } 599 - { id: 4, class: rgpr, preferred-register: '' } 600 - { id: 5, class: rgpr, preferred-register: '' } 601liveins: 602 - { reg: '$r0', virtual-reg: '%0' } 603body: | 604 bb.0: 605 liveins: $r0 606 607 ; CHECK-LABEL: name: t2LDRHi12_negoff 608 ; CHECK: liveins: $r0 609 ; CHECK-NEXT: {{ $}} 610 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 611 ; CHECK-NEXT: [[t2LDRHi12_:%[0-9]+]]:rgpr = t2LDRHi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32)) 612 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 613 ; CHECK-NEXT: [[t2LDRHi12_1:%[0-9]+]]:rgpr = t2LDRHi12 [[COPY]], 4, 14 /* CC::al */, $noreg :: (load (s32)) 614 ; CHECK-NEXT: [[t2LDRHi8_:%[0-9]+]]:rgpr = t2LDRHi8 [[COPY]], -8, 14 /* CC::al */, $noreg :: (load (s32)) 615 ; CHECK-NEXT: [[t2LDRSHi12_:%[0-9]+]]:rgpr = t2LDRSHi12 [[COPY]], 12, 14 /* CC::al */, $noreg :: (load (s32)) 616 ; CHECK-NEXT: $r0 = COPY [[t2SUBri]] 617 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 618 %0:gprnopc = COPY $r0 619 %1:rgpr = t2LDRHi12 %0, 0, 14, $noreg :: (load (s32), align 4) 620 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg 621 %3:rgpr = t2LDRHi12 %0, 4, 14, $noreg :: (load (s32), align 4) 622 %4:rgpr = t2LDRHi8 %0, -8, 14, $noreg :: (load (s32), align 4) 623 %5:rgpr = t2LDRSHi12 %0, 12, 14, $noreg :: (load (s32), align 4) 624 $r0 = COPY %2 625 tBX_RET 14, $noreg, implicit $r0 626 627... 628--- 629name: t2LDRBi12_negoff 630tracksRegLiveness: true 631registers: 632 - { id: 0, class: gprnopc, preferred-register: '' } 633 - { id: 1, class: rgpr, preferred-register: '' } 634 - { id: 2, class: rgpr, preferred-register: '' } 635 - { id: 3, class: rgpr, preferred-register: '' } 636 - { id: 4, class: rgpr, preferred-register: '' } 637 - { id: 5, class: rgpr, preferred-register: '' } 638liveins: 639 - { reg: '$r0', virtual-reg: '%0' } 640body: | 641 bb.0: 642 liveins: $r0 643 644 ; CHECK-LABEL: name: t2LDRBi12_negoff 645 ; CHECK: liveins: $r0 646 ; CHECK-NEXT: {{ $}} 647 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 648 ; CHECK-NEXT: [[t2LDRBi12_:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32)) 649 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 650 ; CHECK-NEXT: [[t2LDRBi12_1:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 4, 14 /* CC::al */, $noreg :: (load (s32)) 651 ; CHECK-NEXT: [[t2LDRBi8_:%[0-9]+]]:rgpr = t2LDRBi8 [[COPY]], -8, 14 /* CC::al */, $noreg :: (load (s32)) 652 ; CHECK-NEXT: [[t2LDRSBi12_:%[0-9]+]]:rgpr = t2LDRSBi12 [[COPY]], 12, 14 /* CC::al */, $noreg :: (load (s32)) 653 ; CHECK-NEXT: $r0 = COPY [[t2SUBri]] 654 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 655 %0:gprnopc = COPY $r0 656 %1:rgpr = t2LDRBi12 %0, 0, 14, $noreg :: (load (s32), align 4) 657 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg 658 %3:rgpr = t2LDRBi12 %0, 4, 14, $noreg :: (load (s32), align 4) 659 %4:rgpr = t2LDRBi8 %0, -8, 14, $noreg :: (load (s32), align 4) 660 %12:rgpr = t2LDRSBi12 %0, 12, 14, $noreg :: (load (s32), align 4) 661 $r0 = COPY %2 662 tBX_RET 14, $noreg, implicit $r0 663 664... 665--- 666name: t2STRi12_negoff 667tracksRegLiveness: true 668registers: 669 - { id: 0, class: gprnopc, preferred-register: '' } 670 - { id: 1, class: rgpr, preferred-register: '' } 671 - { id: 2, class: rgpr, preferred-register: '' } 672liveins: 673 - { reg: '$r0', virtual-reg: '%0' } 674 - { reg: '$r1', virtual-reg: '%1' } 675body: | 676 bb.0: 677 liveins: $r0, $r1 678 679 ; CHECK-LABEL: name: t2STRi12_negoff 680 ; CHECK: liveins: $r0, $r1 681 ; CHECK-NEXT: {{ $}} 682 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 683 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 684 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 685 ; CHECK-NEXT: t2STRi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32)) 686 ; CHECK-NEXT: t2STRi12 [[COPY1]], [[COPY]], 4, 14 /* CC::al */, $noreg :: (store (s32)) 687 ; CHECK-NEXT: t2STRi8 [[COPY1]], [[COPY]], -8, 14 /* CC::al */, $noreg :: (store (s32)) 688 ; CHECK-NEXT: $r0 = COPY [[t2SUBri]] 689 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 690 %0:gprnopc = COPY $r0 691 %1:rgpr = COPY $r1 692 t2STRi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4) 693 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg 694 t2STRi12 %1:rgpr, %0, 4, 14, $noreg :: (store (s32), align 4) 695 t2STRi8 %1:rgpr, %0, -8, 14, $noreg :: (store (s32), align 4) 696 $r0 = COPY %2 697 tBX_RET 14, $noreg, implicit $r0 698 699... 700--- 701name: t2STRHi12_negoff 702tracksRegLiveness: true 703registers: 704 - { id: 0, class: gprnopc, preferred-register: '' } 705 - { id: 1, class: rgpr, preferred-register: '' } 706 - { id: 2, class: rgpr, preferred-register: '' } 707liveins: 708 - { reg: '$r0', virtual-reg: '%0' } 709 - { reg: '$r1', virtual-reg: '%1' } 710body: | 711 bb.0: 712 liveins: $r0, $r1 713 714 ; CHECK-LABEL: name: t2STRHi12_negoff 715 ; CHECK: liveins: $r0, $r1 716 ; CHECK-NEXT: {{ $}} 717 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 718 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 719 ; CHECK-NEXT: t2STRHi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32)) 720 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 721 ; CHECK-NEXT: t2STRHi12 [[COPY1]], [[COPY]], 4, 14 /* CC::al */, $noreg :: (store (s32)) 722 ; CHECK-NEXT: t2STRHi8 [[COPY1]], [[COPY]], -8, 14 /* CC::al */, $noreg :: (store (s32)) 723 ; CHECK-NEXT: $r0 = COPY [[t2SUBri]] 724 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 725 %0:gprnopc = COPY $r0 726 %1:rgpr = COPY $r1 727 t2STRHi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4) 728 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg 729 t2STRHi12 %1:rgpr, %0, 4, 14, $noreg :: (store (s32), align 4) 730 t2STRHi8 %1:rgpr, %0, -8, 14, $noreg :: (store (s32), align 4) 731 $r0 = COPY %2 732 tBX_RET 14, $noreg, implicit $r0 733 734... 735--- 736name: t2STRBi12_negoff 737tracksRegLiveness: true 738registers: 739 - { id: 0, class: gprnopc, preferred-register: '' } 740 - { id: 1, class: rgpr, preferred-register: '' } 741 - { id: 2, class: rgpr, preferred-register: '' } 742liveins: 743 - { reg: '$r0', virtual-reg: '%0' } 744 - { reg: '$r1', virtual-reg: '%1' } 745body: | 746 bb.0: 747 liveins: $r0, $r1 748 749 ; CHECK-LABEL: name: t2STRBi12_negoff 750 ; CHECK: liveins: $r0, $r1 751 ; CHECK-NEXT: {{ $}} 752 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 753 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 754 ; CHECK-NEXT: t2STRBi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32)) 755 ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg 756 ; CHECK-NEXT: t2STRBi12 [[COPY1]], [[COPY]], 4, 14 /* CC::al */, $noreg :: (store (s32)) 757 ; CHECK-NEXT: t2STRBi8 [[COPY1]], [[COPY]], -8, 14 /* CC::al */, $noreg :: (store (s32)) 758 ; CHECK-NEXT: $r0 = COPY [[t2SUBri]] 759 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 760 %0:gprnopc = COPY $r0 761 %1:rgpr = COPY $r1 762 t2STRBi12 %1:rgpr, %0, 0, 14, $noreg :: (store (s32), align 4) 763 %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg 764 t2STRBi12 %1:rgpr, %0, 4, 14, $noreg :: (store (s32), align 4) 765 t2STRBi8 %1:rgpr, %0, -8, 14, $noreg :: (store (s32), align 4) 766 $r0 = COPY %2 767 tBX_RET 14, $noreg, implicit $r0 768 769... 770