xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-vqshrn.ll (revision 7b3bbd83c0c24087072ec5b22a76799ab31f87d5)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
3
4define arm_aapcs_vfpcc <4 x i32> @vqshrni32_smaxmin(<4 x i32> %so) {
5; CHECK-LABEL: vqshrni32_smaxmin:
6; CHECK:       @ %bb.0: @ %entry
7; CHECK-NEXT:    vqshrnb.s32 q0, q0, #3
8; CHECK-NEXT:    vmovlb.s16 q0, q0
9; CHECK-NEXT:    bx lr
10entry:
11  %s0 = ashr <4 x i32> %so, <i32 3, i32 3, i32 3, i32 3>
12  %c1 = icmp slt <4 x i32> %s0, <i32 32767, i32 32767, i32 32767, i32 32767>
13  %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
14  %c2 = icmp sgt <4 x i32> %s1, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
15  %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
16  ret <4 x i32> %s2
17}
18
19define arm_aapcs_vfpcc <4 x i32> @vqshrni32_sminmax(<4 x i32> %so) {
20; CHECK-LABEL: vqshrni32_sminmax:
21; CHECK:       @ %bb.0: @ %entry
22; CHECK-NEXT:    vqshrnb.s32 q0, q0, #3
23; CHECK-NEXT:    vmovlb.s16 q0, q0
24; CHECK-NEXT:    bx lr
25entry:
26  %s0 = ashr <4 x i32> %so, <i32 3, i32 3, i32 3, i32 3>
27  %c1 = icmp sgt <4 x i32> %s0, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
28  %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
29  %c2 = icmp slt <4 x i32> %s1, <i32 32767, i32 32767, i32 32767, i32 32767>
30  %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
31  ret <4 x i32> %s2
32}
33
34define arm_aapcs_vfpcc <4 x i32> @vqshrni32_umaxmin(<4 x i32> %so) {
35; CHECK-LABEL: vqshrni32_umaxmin:
36; CHECK:       @ %bb.0: @ %entry
37; CHECK-NEXT:    vqshrnb.u32 q0, q0, #3
38; CHECK-NEXT:    vmovlb.u16 q0, q0
39; CHECK-NEXT:    bx lr
40entry:
41  %s0 = lshr <4 x i32> %so, <i32 3, i32 3, i32 3, i32 3>
42  %c1 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>
43  %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
44  ret <4 x i32> %s1
45}
46
47define arm_aapcs_vfpcc <4 x i32> @vqshrni32_uminmax(<4 x i32> %so) {
48; CHECK-LABEL: vqshrni32_uminmax:
49; CHECK:       @ %bb.0: @ %entry
50; CHECK-NEXT:    vqshrnb.u32 q0, q0, #3
51; CHECK-NEXT:    vmovlb.u16 q0, q0
52; CHECK-NEXT:    bx lr
53entry:
54  %s0 = lshr <4 x i32> %so, <i32 3, i32 3, i32 3, i32 3>
55  %c2 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>
56  %s2 = select <4 x i1> %c2, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
57  ret <4 x i32> %s2
58}
59
60define arm_aapcs_vfpcc <8 x i16> @vqshrni16_smaxmin(<8 x i16> %so) {
61; CHECK-LABEL: vqshrni16_smaxmin:
62; CHECK:       @ %bb.0: @ %entry
63; CHECK-NEXT:    vqshrnb.s16 q0, q0, #3
64; CHECK-NEXT:    vmovlb.s8 q0, q0
65; CHECK-NEXT:    bx lr
66entry:
67  %s0 = ashr <8 x i16> %so, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
68  %c1 = icmp slt <8 x i16> %s0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
69  %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
70  %c2 = icmp sgt <8 x i16> %s1, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
71  %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
72  ret <8 x i16> %s2
73}
74
75define arm_aapcs_vfpcc <8 x i16> @vqshrni16_sminmax(<8 x i16> %so) {
76; CHECK-LABEL: vqshrni16_sminmax:
77; CHECK:       @ %bb.0: @ %entry
78; CHECK-NEXT:    vqshrnb.s16 q0, q0, #3
79; CHECK-NEXT:    vmovlb.s8 q0, q0
80; CHECK-NEXT:    bx lr
81entry:
82  %s0 = ashr <8 x i16> %so, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
83  %c1 = icmp sgt <8 x i16> %s0, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
84  %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
85  %c2 = icmp slt <8 x i16> %s1, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
86  %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
87  ret <8 x i16> %s2
88}
89
90define arm_aapcs_vfpcc <8 x i16> @vqshrni16_umaxmin(<8 x i16> %so) {
91; CHECK-LABEL: vqshrni16_umaxmin:
92; CHECK:       @ %bb.0: @ %entry
93; CHECK-NEXT:    vqshrnb.u16 q0, q0, #3
94; CHECK-NEXT:    vmovlb.u8 q0, q0
95; CHECK-NEXT:    bx lr
96entry:
97  %s0 = lshr <8 x i16> %so, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
98  %c1 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
99  %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
100  ret <8 x i16> %s1
101}
102
103define arm_aapcs_vfpcc <8 x i16> @vqshrni16_uminmax(<8 x i16> %so) {
104; CHECK-LABEL: vqshrni16_uminmax:
105; CHECK:       @ %bb.0: @ %entry
106; CHECK-NEXT:    vqshrnb.u16 q0, q0, #3
107; CHECK-NEXT:    vmovlb.u8 q0, q0
108; CHECK-NEXT:    bx lr
109entry:
110  %s0 = lshr <8 x i16> %so, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
111  %c2 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
112  %s2 = select <8 x i1> %c2, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
113  ret <8 x i16> %s2
114}
115
116define arm_aapcs_vfpcc <16 x i8> @vqshrni8_smaxmin(<16 x i8> %so) {
117; CHECK-LABEL: vqshrni8_smaxmin:
118; CHECK:       @ %bb.0: @ %entry
119; CHECK-NEXT:    vshr.s8 q0, q0, #3
120; CHECK-NEXT:    vmov.i8 q1, #0x7
121; CHECK-NEXT:    vmin.s8 q0, q0, q1
122; CHECK-NEXT:    vmov.i8 q1, #0xf8
123; CHECK-NEXT:    vmax.s8 q0, q0, q1
124; CHECK-NEXT:    bx lr
125entry:
126  %s0 = ashr <16 x i8> %so, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
127  %c1 = icmp slt <16 x i8> %s0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
128  %s1 = select <16 x i1> %c1, <16 x i8> %s0, <16 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
129  %c2 = icmp sgt <16 x i8> %s1, <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8>
130  %s2 = select <16 x i1> %c2, <16 x i8> %s1, <16 x i8> <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8>
131  ret <16 x i8> %s2
132}
133
134define arm_aapcs_vfpcc <16 x i8> @vqshrni8_sminmax(<16 x i8> %so) {
135; CHECK-LABEL: vqshrni8_sminmax:
136; CHECK:       @ %bb.0: @ %entry
137; CHECK-NEXT:    vshr.s8 q0, q0, #3
138; CHECK-NEXT:    vmov.i8 q1, #0xf8
139; CHECK-NEXT:    vmax.s8 q0, q0, q1
140; CHECK-NEXT:    vmov.i8 q1, #0x7
141; CHECK-NEXT:    vmin.s8 q0, q0, q1
142; CHECK-NEXT:    bx lr
143entry:
144  %s0 = ashr <16 x i8> %so, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
145  %c1 = icmp sgt <16 x i8> %s0, <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8>
146  %s1 = select <16 x i1> %c1, <16 x i8> %s0, <16 x i8> <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8>
147  %c2 = icmp slt <16 x i8> %s1, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
148  %s2 = select <16 x i1> %c2, <16 x i8> %s1, <16 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
149  ret <16 x i8> %s2
150}
151
152define arm_aapcs_vfpcc <16 x i8> @vqshrni8_umaxmin(<16 x i8> %so) {
153; CHECK-LABEL: vqshrni8_umaxmin:
154; CHECK:       @ %bb.0: @ %entry
155; CHECK-NEXT:    vshr.u8 q0, q0, #3
156; CHECK-NEXT:    vmov.i8 q1, #0xf
157; CHECK-NEXT:    vmin.u8 q0, q0, q1
158; CHECK-NEXT:    bx lr
159entry:
160  %s0 = lshr <16 x i8> %so, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
161  %c1 = icmp ult <16 x i8> %s0, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
162  %s1 = select <16 x i1> %c1, <16 x i8> %s0, <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
163  ret <16 x i8> %s1
164}
165
166define arm_aapcs_vfpcc <16 x i8> @vqshrni8_uminmax(<16 x i8> %so) {
167; CHECK-LABEL: vqshrni8_uminmax:
168; CHECK:       @ %bb.0: @ %entry
169; CHECK-NEXT:    vshr.u8 q0, q0, #3
170; CHECK-NEXT:    vmov.i8 q1, #0xf
171; CHECK-NEXT:    vmin.u8 q0, q0, q1
172; CHECK-NEXT:    bx lr
173entry:
174  %s0 = lshr <16 x i8> %so, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
175  %c2 = icmp ult <16 x i8> %s0, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
176  %s2 = select <16 x i1> %c2, <16 x i8> %s0, <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
177  ret <16 x i8> %s2
178}
179
180define arm_aapcs_vfpcc <2 x i64> @vqshrni64_smaxmin(<2 x i64> %so) {
181; CHECK-LABEL: vqshrni64_smaxmin:
182; CHECK:       @ %bb.0: @ %entry
183; CHECK-NEXT:    .save {r7, lr}
184; CHECK-NEXT:    push {r7, lr}
185; CHECK-NEXT:    vmov r0, r1, d1
186; CHECK-NEXT:    mvn r12, #-2147483648
187; CHECK-NEXT:    vmov r2, r3, d0
188; CHECK-NEXT:    asrl r0, r1, #3
189; CHECK-NEXT:    asrl r2, r3, #3
190; CHECK-NEXT:    vmov q0[2], q0[0], r2, r0
191; CHECK-NEXT:    subs.w r2, r2, r12
192; CHECK-NEXT:    sbcs r2, r3, #0
193; CHECK-NEXT:    vmov q0[3], q0[1], r3, r1
194; CHECK-NEXT:    csetm lr, lt
195; CHECK-NEXT:    subs.w r0, r0, r12
196; CHECK-NEXT:    mov.w r2, #0
197; CHECK-NEXT:    sbcs r0, r1, #0
198; CHECK-NEXT:    bfi r2, lr, #0, #8
199; CHECK-NEXT:    csetm r0, lt
200; CHECK-NEXT:    bfi r2, r0, #8, #8
201; CHECK-NEXT:    adr r0, .LCPI12_0
202; CHECK-NEXT:    vldrw.u32 q1, [r0]
203; CHECK-NEXT:    vmsr p0, r2
204; CHECK-NEXT:    mov.w r2, #-1
205; CHECK-NEXT:    movs r3, #0
206; CHECK-NEXT:    vpsel q0, q0, q1
207; CHECK-NEXT:    vmov r0, r1, d0
208; CHECK-NEXT:    rsbs.w r0, r0, #-2147483648
209; CHECK-NEXT:    sbcs.w r0, r2, r1
210; CHECK-NEXT:    csetm r0, lt
211; CHECK-NEXT:    bfi r3, r0, #0, #8
212; CHECK-NEXT:    vmov r0, r1, d1
213; CHECK-NEXT:    rsbs.w r0, r0, #-2147483648
214; CHECK-NEXT:    sbcs.w r0, r2, r1
215; CHECK-NEXT:    csetm r0, lt
216; CHECK-NEXT:    bfi r3, r0, #8, #8
217; CHECK-NEXT:    adr r0, .LCPI12_1
218; CHECK-NEXT:    vldrw.u32 q1, [r0]
219; CHECK-NEXT:    vmsr p0, r3
220; CHECK-NEXT:    vpsel q0, q0, q1
221; CHECK-NEXT:    pop {r7, pc}
222; CHECK-NEXT:    .p2align 4
223; CHECK-NEXT:  @ %bb.1:
224; CHECK-NEXT:  .LCPI12_0:
225; CHECK-NEXT:    .long 2147483647 @ 0x7fffffff
226; CHECK-NEXT:    .long 0 @ 0x0
227; CHECK-NEXT:    .long 2147483647 @ 0x7fffffff
228; CHECK-NEXT:    .long 0 @ 0x0
229; CHECK-NEXT:  .LCPI12_1:
230; CHECK-NEXT:    .long 2147483648 @ 0x80000000
231; CHECK-NEXT:    .long 4294967295 @ 0xffffffff
232; CHECK-NEXT:    .long 2147483648 @ 0x80000000
233; CHECK-NEXT:    .long 4294967295 @ 0xffffffff
234entry:
235  %s0 = ashr <2 x i64> %so, <i64 3, i64 3>
236  %c1 = icmp slt <2 x i64> %s0, <i64 2147483647, i64 2147483647>
237  %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 2147483647, i64 2147483647>
238  %c2 = icmp sgt <2 x i64> %s1, <i64 -2147483648, i64 -2147483648>
239  %s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 -2147483648, i64 -2147483648>
240  ret <2 x i64> %s2
241}
242
243define arm_aapcs_vfpcc <2 x i64> @vqshrni64_sminmax(<2 x i64> %so) {
244; CHECK-LABEL: vqshrni64_sminmax:
245; CHECK:       @ %bb.0: @ %entry
246; CHECK-NEXT:    .save {r4, r5, r6, lr}
247; CHECK-NEXT:    push {r4, r5, r6, lr}
248; CHECK-NEXT:    vmov r2, r1, d0
249; CHECK-NEXT:    mov.w r12, #-1
250; CHECK-NEXT:    asrl r2, r1, #3
251; CHECK-NEXT:    vmov r4, r5, d1
252; CHECK-NEXT:    rsbs.w r0, r2, #-2147483648
253; CHECK-NEXT:    asrl r4, r5, #3
254; CHECK-NEXT:    sbcs.w r0, r12, r1
255; CHECK-NEXT:    mov.w r3, #0
256; CHECK-NEXT:    csetm lr, lt
257; CHECK-NEXT:    rsbs.w r0, r4, #-2147483648
258; CHECK-NEXT:    sbcs.w r0, r12, r5
259; CHECK-NEXT:    bfi r3, lr, #0, #8
260; CHECK-NEXT:    csetm r0, lt
261; CHECK-NEXT:    vmov q0[2], q0[0], r2, r4
262; CHECK-NEXT:    bfi r3, r0, #8, #8
263; CHECK-NEXT:    adr r0, .LCPI13_0
264; CHECK-NEXT:    vldrw.u32 q1, [r0]
265; CHECK-NEXT:    vmsr p0, r3
266; CHECK-NEXT:    vmov q0[3], q0[1], r1, r5
267; CHECK-NEXT:    mvn r2, #-2147483648
268; CHECK-NEXT:    vpsel q0, q0, q1
269; CHECK-NEXT:    movs r6, #0
270; CHECK-NEXT:    vmov r0, r1, d0
271; CHECK-NEXT:    subs r0, r0, r2
272; CHECK-NEXT:    sbcs r0, r1, #0
273; CHECK-NEXT:    csetm r0, lt
274; CHECK-NEXT:    bfi r6, r0, #0, #8
275; CHECK-NEXT:    vmov r0, r1, d1
276; CHECK-NEXT:    subs r0, r0, r2
277; CHECK-NEXT:    sbcs r0, r1, #0
278; CHECK-NEXT:    csetm r0, lt
279; CHECK-NEXT:    bfi r6, r0, #8, #8
280; CHECK-NEXT:    adr r0, .LCPI13_1
281; CHECK-NEXT:    vldrw.u32 q1, [r0]
282; CHECK-NEXT:    vmsr p0, r6
283; CHECK-NEXT:    vpsel q0, q0, q1
284; CHECK-NEXT:    pop {r4, r5, r6, pc}
285; CHECK-NEXT:    .p2align 4
286; CHECK-NEXT:  @ %bb.1:
287; CHECK-NEXT:  .LCPI13_0:
288; CHECK-NEXT:    .long 2147483648 @ 0x80000000
289; CHECK-NEXT:    .long 4294967295 @ 0xffffffff
290; CHECK-NEXT:    .long 2147483648 @ 0x80000000
291; CHECK-NEXT:    .long 4294967295 @ 0xffffffff
292; CHECK-NEXT:  .LCPI13_1:
293; CHECK-NEXT:    .long 2147483647 @ 0x7fffffff
294; CHECK-NEXT:    .long 0 @ 0x0
295; CHECK-NEXT:    .long 2147483647 @ 0x7fffffff
296; CHECK-NEXT:    .long 0 @ 0x0
297entry:
298  %s0 = ashr <2 x i64> %so, <i64 3, i64 3>
299  %c1 = icmp sgt <2 x i64> %s0, <i64 -2147483648, i64 -2147483648>
300  %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 -2147483648, i64 -2147483648>
301  %c2 = icmp slt <2 x i64> %s1, <i64 2147483647, i64 2147483647>
302  %s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 2147483647, i64 2147483647>
303  ret <2 x i64> %s2
304}
305
306define arm_aapcs_vfpcc <2 x i64> @vqshrni64_umaxmin(<2 x i64> %so) {
307; CHECK-LABEL: vqshrni64_umaxmin:
308; CHECK:       @ %bb.0: @ %entry
309; CHECK-NEXT:    vmov r0, r1, d1
310; CHECK-NEXT:    vmov.i64 q1, #0xffffffff
311; CHECK-NEXT:    vmov r2, r3, d0
312; CHECK-NEXT:    lsrl r0, r1, #3
313; CHECK-NEXT:    lsrl r2, r3, #3
314; CHECK-NEXT:    vmov q0[2], q0[0], r2, r0
315; CHECK-NEXT:    subs.w r2, r2, #-1
316; CHECK-NEXT:    sbcs r2, r3, #0
317; CHECK-NEXT:    vmov q0[3], q0[1], r3, r1
318; CHECK-NEXT:    csetm r2, lo
319; CHECK-NEXT:    subs.w r0, r0, #-1
320; CHECK-NEXT:    mov.w r3, #0
321; CHECK-NEXT:    sbcs r0, r1, #0
322; CHECK-NEXT:    bfi r3, r2, #0, #8
323; CHECK-NEXT:    csetm r0, lo
324; CHECK-NEXT:    bfi r3, r0, #8, #8
325; CHECK-NEXT:    vmsr p0, r3
326; CHECK-NEXT:    vpsel q0, q0, q1
327; CHECK-NEXT:    bx lr
328entry:
329  %s0 = lshr <2 x i64> %so, <i64 3, i64 3>
330  %c1 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295>
331  %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>
332  ret <2 x i64> %s1
333}
334
335define arm_aapcs_vfpcc <2 x i64> @vqshrni64_uminmax(<2 x i64> %so) {
336; CHECK-LABEL: vqshrni64_uminmax:
337; CHECK:       @ %bb.0: @ %entry
338; CHECK-NEXT:    vmov r0, r1, d1
339; CHECK-NEXT:    vmov.i64 q1, #0xffffffff
340; CHECK-NEXT:    vmov r2, r3, d0
341; CHECK-NEXT:    lsrl r0, r1, #3
342; CHECK-NEXT:    lsrl r2, r3, #3
343; CHECK-NEXT:    vmov q0[2], q0[0], r2, r0
344; CHECK-NEXT:    subs.w r2, r2, #-1
345; CHECK-NEXT:    sbcs r2, r3, #0
346; CHECK-NEXT:    vmov q0[3], q0[1], r3, r1
347; CHECK-NEXT:    csetm r2, lo
348; CHECK-NEXT:    subs.w r0, r0, #-1
349; CHECK-NEXT:    mov.w r3, #0
350; CHECK-NEXT:    sbcs r0, r1, #0
351; CHECK-NEXT:    bfi r3, r2, #0, #8
352; CHECK-NEXT:    csetm r0, lo
353; CHECK-NEXT:    bfi r3, r0, #8, #8
354; CHECK-NEXT:    vmsr p0, r3
355; CHECK-NEXT:    vpsel q0, q0, q1
356; CHECK-NEXT:    bx lr
357entry:
358  %s0 = lshr <2 x i64> %so, <i64 3, i64 3>
359  %c2 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295>
360  %s2 = select <2 x i1> %c2, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>
361  ret <2 x i64> %s2
362}
363