1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s 3 4define arm_aapcs_vfpcc <4 x i32> @vqmovni32_smaxmin(<4 x i32> %s0) { 5; CHECK-LABEL: vqmovni32_smaxmin: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vqmovnb.s32 q0, q0 8; CHECK-NEXT: vmovlb.s16 q0, q0 9; CHECK-NEXT: bx lr 10entry: 11 %c1 = icmp slt <4 x i32> %s0, <i32 32767, i32 32767, i32 32767, i32 32767> 12 %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 13 %c2 = icmp sgt <4 x i32> %s1, <i32 -32768, i32 -32768, i32 -32768, i32 -32768> 14 %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768> 15 ret <4 x i32> %s2 16} 17 18define arm_aapcs_vfpcc <4 x i32> @vqmovni32_sminmax(<4 x i32> %s0) { 19; CHECK-LABEL: vqmovni32_sminmax: 20; CHECK: @ %bb.0: @ %entry 21; CHECK-NEXT: vqmovnb.s32 q0, q0 22; CHECK-NEXT: vmovlb.s16 q0, q0 23; CHECK-NEXT: bx lr 24entry: 25 %c1 = icmp sgt <4 x i32> %s0, <i32 -32768, i32 -32768, i32 -32768, i32 -32768> 26 %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768> 27 %c2 = icmp slt <4 x i32> %s1, <i32 32767, i32 32767, i32 32767, i32 32767> 28 %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 29 ret <4 x i32> %s2 30} 31 32define arm_aapcs_vfpcc <4 x i32> @vqmovni32_umaxmin(<4 x i32> %s0) { 33; CHECK-LABEL: vqmovni32_umaxmin: 34; CHECK: @ %bb.0: @ %entry 35; CHECK-NEXT: vqmovnb.u32 q0, q0 36; CHECK-NEXT: vmovlb.u16 q0, q0 37; CHECK-NEXT: bx lr 38entry: 39 %c1 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535> 40 %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 41 ret <4 x i32> %s1 42} 43 44define arm_aapcs_vfpcc <4 x i32> @vqmovni32_uminmax(<4 x i32> %s0) { 45; CHECK-LABEL: vqmovni32_uminmax: 46; CHECK: @ %bb.0: @ %entry 47; CHECK-NEXT: vqmovnb.u32 q0, q0 48; CHECK-NEXT: vmovlb.u16 q0, q0 49; CHECK-NEXT: bx lr 50entry: 51 %c2 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535> 52 %s2 = select <4 x i1> %c2, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 53 ret <4 x i32> %s2 54} 55 56define arm_aapcs_vfpcc <8 x i16> @vqmovni16_smaxmin(<8 x i16> %s0) { 57; CHECK-LABEL: vqmovni16_smaxmin: 58; CHECK: @ %bb.0: @ %entry 59; CHECK-NEXT: vqmovnb.s16 q0, q0 60; CHECK-NEXT: vmovlb.s8 q0, q0 61; CHECK-NEXT: bx lr 62entry: 63 %c1 = icmp slt <8 x i16> %s0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127> 64 %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127> 65 %c2 = icmp sgt <8 x i16> %s1, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128> 66 %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128> 67 ret <8 x i16> %s2 68} 69 70define arm_aapcs_vfpcc <8 x i16> @vqmovni16_sminmax(<8 x i16> %s0) { 71; CHECK-LABEL: vqmovni16_sminmax: 72; CHECK: @ %bb.0: @ %entry 73; CHECK-NEXT: vqmovnb.s16 q0, q0 74; CHECK-NEXT: vmovlb.s8 q0, q0 75; CHECK-NEXT: bx lr 76entry: 77 %c1 = icmp sgt <8 x i16> %s0, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128> 78 %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128> 79 %c2 = icmp slt <8 x i16> %s1, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127> 80 %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127> 81 ret <8 x i16> %s2 82} 83 84define arm_aapcs_vfpcc <8 x i16> @vqmovni16_umaxmin(<8 x i16> %s0) { 85; CHECK-LABEL: vqmovni16_umaxmin: 86; CHECK: @ %bb.0: @ %entry 87; CHECK-NEXT: vqmovnb.u16 q0, q0 88; CHECK-NEXT: vmovlb.u8 q0, q0 89; CHECK-NEXT: bx lr 90entry: 91 %c1 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> 92 %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> 93 ret <8 x i16> %s1 94} 95 96define arm_aapcs_vfpcc <8 x i16> @vqmovni16_uminmax(<8 x i16> %s0) { 97; CHECK-LABEL: vqmovni16_uminmax: 98; CHECK: @ %bb.0: @ %entry 99; CHECK-NEXT: vqmovnb.u16 q0, q0 100; CHECK-NEXT: vmovlb.u8 q0, q0 101; CHECK-NEXT: bx lr 102entry: 103 %c2 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> 104 %s2 = select <8 x i1> %c2, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> 105 ret <8 x i16> %s2 106} 107 108define arm_aapcs_vfpcc <16 x i8> @vqmovni8_smaxmin(<16 x i8> %s0) { 109; CHECK-LABEL: vqmovni8_smaxmin: 110; CHECK: @ %bb.0: @ %entry 111; CHECK-NEXT: vmov.i8 q1, #0x7 112; CHECK-NEXT: vmin.s8 q0, q0, q1 113; CHECK-NEXT: vmov.i8 q1, #0xf8 114; CHECK-NEXT: vmax.s8 q0, q0, q1 115; CHECK-NEXT: bx lr 116entry: 117 %c1 = icmp slt <16 x i8> %s0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 118 %s1 = select <16 x i1> %c1, <16 x i8> %s0, <16 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 119 %c2 = icmp sgt <16 x i8> %s1, <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8> 120 %s2 = select <16 x i1> %c2, <16 x i8> %s1, <16 x i8> <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8> 121 ret <16 x i8> %s2 122} 123 124define arm_aapcs_vfpcc <16 x i8> @vqmovni8_sminmax(<16 x i8> %s0) { 125; CHECK-LABEL: vqmovni8_sminmax: 126; CHECK: @ %bb.0: @ %entry 127; CHECK-NEXT: vmov.i8 q1, #0xf8 128; CHECK-NEXT: vmax.s8 q0, q0, q1 129; CHECK-NEXT: vmov.i8 q1, #0x7 130; CHECK-NEXT: vmin.s8 q0, q0, q1 131; CHECK-NEXT: bx lr 132entry: 133 %c1 = icmp sgt <16 x i8> %s0, <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8> 134 %s1 = select <16 x i1> %c1, <16 x i8> %s0, <16 x i8> <i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8> 135 %c2 = icmp slt <16 x i8> %s1, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 136 %s2 = select <16 x i1> %c2, <16 x i8> %s1, <16 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 137 ret <16 x i8> %s2 138} 139 140define arm_aapcs_vfpcc <16 x i8> @vqmovni8_umaxmin(<16 x i8> %s0) { 141; CHECK-LABEL: vqmovni8_umaxmin: 142; CHECK: @ %bb.0: @ %entry 143; CHECK-NEXT: vmov.i8 q1, #0xf 144; CHECK-NEXT: vmin.u8 q0, q0, q1 145; CHECK-NEXT: bx lr 146entry: 147 %c1 = icmp ult <16 x i8> %s0, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15> 148 %s1 = select <16 x i1> %c1, <16 x i8> %s0, <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15> 149 ret <16 x i8> %s1 150} 151 152define arm_aapcs_vfpcc <16 x i8> @vqmovni8_uminmax(<16 x i8> %s0) { 153; CHECK-LABEL: vqmovni8_uminmax: 154; CHECK: @ %bb.0: @ %entry 155; CHECK-NEXT: vmov.i8 q1, #0xf 156; CHECK-NEXT: vmin.u8 q0, q0, q1 157; CHECK-NEXT: bx lr 158entry: 159 %c2 = icmp ult <16 x i8> %s0, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15> 160 %s2 = select <16 x i1> %c2, <16 x i8> %s0, <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15> 161 ret <16 x i8> %s2 162} 163 164define arm_aapcs_vfpcc <2 x i64> @vqmovni64_smaxmin(<2 x i64> %s0) { 165; CHECK-LABEL: vqmovni64_smaxmin: 166; CHECK: @ %bb.0: @ %entry 167; CHECK-NEXT: vmov r0, r1, d0 168; CHECK-NEXT: mvn r12, #-2147483648 169; CHECK-NEXT: movs r3, #0 170; CHECK-NEXT: subs.w r0, r0, r12 171; CHECK-NEXT: sbcs r0, r1, #0 172; CHECK-NEXT: csetm r1, lt 173; CHECK-NEXT: movs r0, #0 174; CHECK-NEXT: bfi r3, r1, #0, #8 175; CHECK-NEXT: vmov r1, r2, d1 176; CHECK-NEXT: subs.w r1, r1, r12 177; CHECK-NEXT: sbcs r1, r2, #0 178; CHECK-NEXT: csetm r1, lt 179; CHECK-NEXT: bfi r3, r1, #8, #8 180; CHECK-NEXT: adr r1, .LCPI12_0 181; CHECK-NEXT: vldrw.u32 q1, [r1] 182; CHECK-NEXT: vmsr p0, r3 183; CHECK-NEXT: mov.w r3, #-1 184; CHECK-NEXT: vpsel q0, q0, q1 185; CHECK-NEXT: vmov r1, r2, d0 186; CHECK-NEXT: rsbs.w r1, r1, #-2147483648 187; CHECK-NEXT: sbcs.w r1, r3, r2 188; CHECK-NEXT: csetm r1, lt 189; CHECK-NEXT: bfi r0, r1, #0, #8 190; CHECK-NEXT: vmov r1, r2, d1 191; CHECK-NEXT: rsbs.w r1, r1, #-2147483648 192; CHECK-NEXT: sbcs.w r1, r3, r2 193; CHECK-NEXT: csetm r1, lt 194; CHECK-NEXT: bfi r0, r1, #8, #8 195; CHECK-NEXT: vmsr p0, r0 196; CHECK-NEXT: adr r0, .LCPI12_1 197; CHECK-NEXT: vldrw.u32 q1, [r0] 198; CHECK-NEXT: vpsel q0, q0, q1 199; CHECK-NEXT: bx lr 200; CHECK-NEXT: .p2align 4 201; CHECK-NEXT: @ %bb.1: 202; CHECK-NEXT: .LCPI12_0: 203; CHECK-NEXT: .long 2147483647 @ 0x7fffffff 204; CHECK-NEXT: .long 0 @ 0x0 205; CHECK-NEXT: .long 2147483647 @ 0x7fffffff 206; CHECK-NEXT: .long 0 @ 0x0 207; CHECK-NEXT: .LCPI12_1: 208; CHECK-NEXT: .long 2147483648 @ 0x80000000 209; CHECK-NEXT: .long 4294967295 @ 0xffffffff 210; CHECK-NEXT: .long 2147483648 @ 0x80000000 211; CHECK-NEXT: .long 4294967295 @ 0xffffffff 212entry: 213 %c1 = icmp slt <2 x i64> %s0, <i64 2147483647, i64 2147483647> 214 %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 2147483647, i64 2147483647> 215 %c2 = icmp sgt <2 x i64> %s1, <i64 -2147483648, i64 -2147483648> 216 %s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 -2147483648, i64 -2147483648> 217 ret <2 x i64> %s2 218} 219 220define arm_aapcs_vfpcc <2 x i64> @vqmovni64_sminmax(<2 x i64> %s0) { 221; CHECK-LABEL: vqmovni64_sminmax: 222; CHECK: @ %bb.0: @ %entry 223; CHECK-NEXT: vmov r0, r1, d0 224; CHECK-NEXT: mov.w r12, #-1 225; CHECK-NEXT: movs r3, #0 226; CHECK-NEXT: rsbs.w r0, r0, #-2147483648 227; CHECK-NEXT: sbcs.w r0, r12, r1 228; CHECK-NEXT: csetm r1, lt 229; CHECK-NEXT: movs r0, #0 230; CHECK-NEXT: bfi r3, r1, #0, #8 231; CHECK-NEXT: vmov r1, r2, d1 232; CHECK-NEXT: rsbs.w r1, r1, #-2147483648 233; CHECK-NEXT: sbcs.w r1, r12, r2 234; CHECK-NEXT: csetm r1, lt 235; CHECK-NEXT: bfi r3, r1, #8, #8 236; CHECK-NEXT: adr r1, .LCPI13_0 237; CHECK-NEXT: vldrw.u32 q1, [r1] 238; CHECK-NEXT: vmsr p0, r3 239; CHECK-NEXT: mvn r3, #-2147483648 240; CHECK-NEXT: vpsel q0, q0, q1 241; CHECK-NEXT: vmov r1, r2, d0 242; CHECK-NEXT: subs r1, r1, r3 243; CHECK-NEXT: sbcs r1, r2, #0 244; CHECK-NEXT: csetm r1, lt 245; CHECK-NEXT: bfi r0, r1, #0, #8 246; CHECK-NEXT: vmov r1, r2, d1 247; CHECK-NEXT: subs r1, r1, r3 248; CHECK-NEXT: sbcs r1, r2, #0 249; CHECK-NEXT: csetm r1, lt 250; CHECK-NEXT: bfi r0, r1, #8, #8 251; CHECK-NEXT: vmsr p0, r0 252; CHECK-NEXT: adr r0, .LCPI13_1 253; CHECK-NEXT: vldrw.u32 q1, [r0] 254; CHECK-NEXT: vpsel q0, q0, q1 255; CHECK-NEXT: bx lr 256; CHECK-NEXT: .p2align 4 257; CHECK-NEXT: @ %bb.1: 258; CHECK-NEXT: .LCPI13_0: 259; CHECK-NEXT: .long 2147483648 @ 0x80000000 260; CHECK-NEXT: .long 4294967295 @ 0xffffffff 261; CHECK-NEXT: .long 2147483648 @ 0x80000000 262; CHECK-NEXT: .long 4294967295 @ 0xffffffff 263; CHECK-NEXT: .LCPI13_1: 264; CHECK-NEXT: .long 2147483647 @ 0x7fffffff 265; CHECK-NEXT: .long 0 @ 0x0 266; CHECK-NEXT: .long 2147483647 @ 0x7fffffff 267; CHECK-NEXT: .long 0 @ 0x0 268entry: 269 %c1 = icmp sgt <2 x i64> %s0, <i64 -2147483648, i64 -2147483648> 270 %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 -2147483648, i64 -2147483648> 271 %c2 = icmp slt <2 x i64> %s1, <i64 2147483647, i64 2147483647> 272 %s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 2147483647, i64 2147483647> 273 ret <2 x i64> %s2 274} 275 276define arm_aapcs_vfpcc <2 x i64> @vqmovni64_umaxmin(<2 x i64> %s0) { 277; CHECK-LABEL: vqmovni64_umaxmin: 278; CHECK: @ %bb.0: @ %entry 279; CHECK-NEXT: vmov r0, r1, d0 280; CHECK-NEXT: vmov.i64 q1, #0xffffffff 281; CHECK-NEXT: subs.w r0, r0, #-1 282; CHECK-NEXT: sbcs r0, r1, #0 283; CHECK-NEXT: mov.w r1, #0 284; CHECK-NEXT: csetm r0, lo 285; CHECK-NEXT: bfi r1, r0, #0, #8 286; CHECK-NEXT: vmov r0, r2, d1 287; CHECK-NEXT: subs.w r0, r0, #-1 288; CHECK-NEXT: sbcs r0, r2, #0 289; CHECK-NEXT: csetm r0, lo 290; CHECK-NEXT: bfi r1, r0, #8, #8 291; CHECK-NEXT: vmsr p0, r1 292; CHECK-NEXT: vpsel q0, q0, q1 293; CHECK-NEXT: bx lr 294entry: 295 %c1 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295> 296 %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295> 297 ret <2 x i64> %s1 298} 299 300define arm_aapcs_vfpcc <2 x i64> @vqmovni64_uminmax(<2 x i64> %s0) { 301; CHECK-LABEL: vqmovni64_uminmax: 302; CHECK: @ %bb.0: @ %entry 303; CHECK-NEXT: vmov r0, r1, d0 304; CHECK-NEXT: vmov.i64 q1, #0xffffffff 305; CHECK-NEXT: subs.w r0, r0, #-1 306; CHECK-NEXT: sbcs r0, r1, #0 307; CHECK-NEXT: mov.w r1, #0 308; CHECK-NEXT: csetm r0, lo 309; CHECK-NEXT: bfi r1, r0, #0, #8 310; CHECK-NEXT: vmov r0, r2, d1 311; CHECK-NEXT: subs.w r0, r0, #-1 312; CHECK-NEXT: sbcs r0, r2, #0 313; CHECK-NEXT: csetm r0, lo 314; CHECK-NEXT: bfi r1, r0, #8, #8 315; CHECK-NEXT: vmsr p0, r1 316; CHECK-NEXT: vpsel q0, q0, q1 317; CHECK-NEXT: bx lr 318entry: 319 %c2 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295> 320 %s2 = select <2 x i1> %c2, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295> 321 ret <2 x i64> %s2 322} 323