xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-vpt-optimisations.mir (revision 313bf28f98f714a0bd8f74a3beb4631d94428f89) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode -run-pass arm-mve-vpt-opts -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name:            vcmp_with_opposite_cond
6alignment:       4
7body:             |
8  ; CHECK-LABEL: name: vcmp_with_opposite_cond
9  ; CHECK: bb.0:
10  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
11  ; CHECK-NEXT: {{  $}}
12  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF
13  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF
14  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:gprwithzr = IMPLICIT_DEF
15  ; CHECK-NEXT:   [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
16  ; CHECK-NEXT:   [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16_]], 0, $noreg, $noreg
17  ; CHECK-NEXT: {{  $}}
18  ; CHECK-NEXT: bb.1:
19  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
20  ; CHECK-NEXT: {{  $}}
21  ; CHECK-NEXT:   [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
22  ; CHECK-NEXT:   [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf32_]], 0, $noreg, $noreg
23  ; CHECK-NEXT: {{  $}}
24  ; CHECK-NEXT: bb.2:
25  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
26  ; CHECK-NEXT: {{  $}}
27  ; CHECK-NEXT:   [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
28  ; CHECK-NEXT:   [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16_]], 0, $noreg, $noreg
29  ; CHECK-NEXT: {{  $}}
30  ; CHECK-NEXT: bb.3:
31  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
32  ; CHECK-NEXT: {{  $}}
33  ; CHECK-NEXT:   [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
34  ; CHECK-NEXT:   [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32_]], 0, $noreg, $noreg
35  ; CHECK-NEXT: {{  $}}
36  ; CHECK-NEXT: bb.4:
37  ; CHECK-NEXT:   successors: %bb.5(0x80000000)
38  ; CHECK-NEXT: {{  $}}
39  ; CHECK-NEXT:   [[MVE_VCMPi8_:%[0-9]+]]:vccr = MVE_VCMPi8 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
40  ; CHECK-NEXT:   [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8_]], 0, $noreg, $noreg
41  ; CHECK-NEXT: {{  $}}
42  ; CHECK-NEXT: bb.5:
43  ; CHECK-NEXT:   successors: %bb.6(0x80000000)
44  ; CHECK-NEXT: {{  $}}
45  ; CHECK-NEXT:   [[MVE_VCMPs16_:%[0-9]+]]:vccr = MVE_VCMPs16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
46  ; CHECK-NEXT:   [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16_]], 0, $noreg, $noreg
47  ; CHECK-NEXT: {{  $}}
48  ; CHECK-NEXT: bb.6:
49  ; CHECK-NEXT:   successors: %bb.7(0x80000000)
50  ; CHECK-NEXT: {{  $}}
51  ; CHECK-NEXT:   [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
52  ; CHECK-NEXT:   [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
53  ; CHECK-NEXT: {{  $}}
54  ; CHECK-NEXT: bb.7:
55  ; CHECK-NEXT:   successors: %bb.8(0x80000000)
56  ; CHECK-NEXT: {{  $}}
57  ; CHECK-NEXT:   [[MVE_VCMPs8_:%[0-9]+]]:vccr = MVE_VCMPs8 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
58  ; CHECK-NEXT:   [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8_]], 0, $noreg, $noreg
59  ; CHECK-NEXT: {{  $}}
60  ; CHECK-NEXT: bb.8:
61  ; CHECK-NEXT:   successors: %bb.9(0x80000000)
62  ; CHECK-NEXT: {{  $}}
63  ; CHECK-NEXT:   [[MVE_VCMPu16_:%[0-9]+]]:vccr = MVE_VCMPu16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
64  ; CHECK-NEXT:   [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16_]], 0, $noreg, $noreg
65  ; CHECK-NEXT: {{  $}}
66  ; CHECK-NEXT: bb.9:
67  ; CHECK-NEXT:   successors: %bb.10(0x80000000)
68  ; CHECK-NEXT: {{  $}}
69  ; CHECK-NEXT:   [[MVE_VCMPu32_:%[0-9]+]]:vccr = MVE_VCMPu32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
70  ; CHECK-NEXT:   [[MVE_VPNOT9:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32_]], 0, $noreg, $noreg
71  ; CHECK-NEXT: {{  $}}
72  ; CHECK-NEXT: bb.10:
73  ; CHECK-NEXT:   successors: %bb.11(0x80000000)
74  ; CHECK-NEXT: {{  $}}
75  ; CHECK-NEXT:   [[MVE_VCMPu8_:%[0-9]+]]:vccr = MVE_VCMPu8 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
76  ; CHECK-NEXT:   [[MVE_VPNOT10:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8_]], 0, $noreg, $noreg
77  ; CHECK-NEXT: {{  $}}
78  ; CHECK-NEXT: bb.11:
79  ; CHECK-NEXT:   successors: %bb.12(0x80000000)
80  ; CHECK-NEXT: {{  $}}
81  ; CHECK-NEXT:   [[MVE_VCMPf16r:%[0-9]+]]:vccr = MVE_VCMPf16r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg
82  ; CHECK-NEXT:   [[MVE_VPNOT11:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16r]], 0, $noreg, $noreg
83  ; CHECK-NEXT: {{  $}}
84  ; CHECK-NEXT: bb.12:
85  ; CHECK-NEXT:   successors: %bb.13(0x80000000)
86  ; CHECK-NEXT: {{  $}}
87  ; CHECK-NEXT:   [[MVE_VCMPf32r:%[0-9]+]]:vccr = MVE_VCMPf32r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg
88  ; CHECK-NEXT:   [[MVE_VPNOT12:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf32r]], 0, $noreg, $noreg
89  ; CHECK-NEXT: {{  $}}
90  ; CHECK-NEXT: bb.13:
91  ; CHECK-NEXT:   successors: %bb.14(0x80000000)
92  ; CHECK-NEXT: {{  $}}
93  ; CHECK-NEXT:   [[MVE_VCMPi16r:%[0-9]+]]:vccr = MVE_VCMPi16r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg
94  ; CHECK-NEXT:   [[MVE_VPNOT13:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16r]], 0, $noreg, $noreg
95  ; CHECK-NEXT: {{  $}}
96  ; CHECK-NEXT: bb.14:
97  ; CHECK-NEXT:   successors: %bb.15(0x80000000)
98  ; CHECK-NEXT: {{  $}}
99  ; CHECK-NEXT:   [[MVE_VCMPi32r:%[0-9]+]]:vccr = MVE_VCMPi32r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg
100  ; CHECK-NEXT:   [[MVE_VPNOT14:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32r]], 0, $noreg, $noreg
101  ; CHECK-NEXT: {{  $}}
102  ; CHECK-NEXT: bb.15:
103  ; CHECK-NEXT:   successors: %bb.16(0x80000000)
104  ; CHECK-NEXT: {{  $}}
105  ; CHECK-NEXT:   [[MVE_VCMPi8r:%[0-9]+]]:vccr = MVE_VCMPi8r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg
106  ; CHECK-NEXT:   [[MVE_VPNOT15:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8r]], 0, $noreg, $noreg
107  ; CHECK-NEXT: {{  $}}
108  ; CHECK-NEXT: bb.16:
109  ; CHECK-NEXT:   successors: %bb.17(0x80000000)
110  ; CHECK-NEXT: {{  $}}
111  ; CHECK-NEXT:   [[MVE_VCMPs16r:%[0-9]+]]:vccr = MVE_VCMPs16r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg
112  ; CHECK-NEXT:   [[MVE_VPNOT16:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16r]], 0, $noreg, $noreg
113  ; CHECK-NEXT: {{  $}}
114  ; CHECK-NEXT: bb.17:
115  ; CHECK-NEXT:   successors: %bb.18(0x80000000)
116  ; CHECK-NEXT: {{  $}}
117  ; CHECK-NEXT:   [[MVE_VCMPs32r:%[0-9]+]]:vccr = MVE_VCMPs32r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg
118  ; CHECK-NEXT:   [[MVE_VPNOT17:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32r]], 0, $noreg, $noreg
119  ; CHECK-NEXT: {{  $}}
120  ; CHECK-NEXT: bb.18:
121  ; CHECK-NEXT:   successors: %bb.19(0x80000000)
122  ; CHECK-NEXT: {{  $}}
123  ; CHECK-NEXT:   [[MVE_VCMPs8r:%[0-9]+]]:vccr = MVE_VCMPs8r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg
124  ; CHECK-NEXT:   [[MVE_VPNOT18:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8r]], 0, $noreg, $noreg
125  ; CHECK-NEXT: {{  $}}
126  ; CHECK-NEXT: bb.19:
127  ; CHECK-NEXT:   successors: %bb.20(0x80000000)
128  ; CHECK-NEXT: {{  $}}
129  ; CHECK-NEXT:   [[MVE_VCMPu16r:%[0-9]+]]:vccr = MVE_VCMPu16r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg
130  ; CHECK-NEXT:   [[MVE_VPNOT19:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16r]], 0, $noreg, $noreg
131  ; CHECK-NEXT: {{  $}}
132  ; CHECK-NEXT: bb.20:
133  ; CHECK-NEXT:   successors: %bb.21(0x80000000)
134  ; CHECK-NEXT: {{  $}}
135  ; CHECK-NEXT:   [[MVE_VCMPu32r:%[0-9]+]]:vccr = MVE_VCMPu32r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg
136  ; CHECK-NEXT:   [[MVE_VPNOT20:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32r]], 0, $noreg, $noreg
137  ; CHECK-NEXT: {{  $}}
138  ; CHECK-NEXT: bb.21:
139  ; CHECK-NEXT:   successors: %bb.22(0x80000000)
140  ; CHECK-NEXT: {{  $}}
141  ; CHECK-NEXT:   [[MVE_VCMPu8r:%[0-9]+]]:vccr = MVE_VCMPu8r [[DEF]], [[DEF2]], 10, 0, $noreg, $noreg
142  ; CHECK-NEXT:   [[MVE_VPNOT21:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8r]], 0, $noreg, $noreg
143  ; CHECK-NEXT: {{  $}}
144  ; CHECK-NEXT: bb.22:
145  ; CHECK-NEXT:   [[MVE_VCMPu8r1:%[0-9]+]]:vccr = MVE_VCMPu8r [[DEF]], $zr, 10, 0, $noreg, $noreg
146  ; CHECK-NEXT:   [[MVE_VPNOT22:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8r1]], 0, $noreg, $noreg
147  ; CHECK-NEXT:   tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]
148  ;
149  ; Tests that VCMPs with an opposite condition are correctly converted into VPNOTs.
150  ;
151  bb.0:
152    %1:mqpr = IMPLICIT_DEF
153    %2:mqpr = IMPLICIT_DEF
154    %25:gprwithzr = IMPLICIT_DEF
155    %0:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
156    %3:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg
157
158  bb.1:
159    %4:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
160    %5:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg
161
162  bb.2:
163    %6:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
164    %7:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg
165
166  bb.3:
167    %8:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
168    %9:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg
169
170  bb.4:
171    %10:vccr = MVE_VCMPi8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
172    %11:vccr = MVE_VCMPi8 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg
173
174  bb.5:
175    %12:vccr = MVE_VCMPs16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
176    %13:vccr = MVE_VCMPs16 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg
177
178  bb.6:
179    %14:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
180    %15:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg
181
182  bb.7:
183    %16:vccr = MVE_VCMPs8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
184    %17:vccr = MVE_VCMPs8 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg
185
186  bb.8:
187    %18:vccr = MVE_VCMPu16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
188    %19:vccr = MVE_VCMPu16 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg
189
190  bb.9:
191    %20:vccr = MVE_VCMPu32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
192    %21:vccr = MVE_VCMPu32 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg
193
194  bb.10:
195    %22:vccr = MVE_VCMPu8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
196    %23:vccr = MVE_VCMPu8 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg
197
198  bb.11:
199    %24:vccr = MVE_VCMPf16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
200    %26:vccr = MVE_VCMPf16r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg
201
202  bb.12:
203    %27:vccr = MVE_VCMPf32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
204    %28:vccr = MVE_VCMPf32r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg
205
206  bb.13:
207    %29:vccr = MVE_VCMPi16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
208    %30:vccr = MVE_VCMPi16r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg
209
210  bb.14:
211    %31:vccr = MVE_VCMPi32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
212    %32:vccr = MVE_VCMPi32r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg
213
214  bb.15:
215    %33:vccr = MVE_VCMPi8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
216    %34:vccr = MVE_VCMPi8r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg
217
218  bb.16:
219    %35:vccr = MVE_VCMPs16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
220    %36:vccr = MVE_VCMPs16r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg
221
222  bb.17:
223    %37:vccr = MVE_VCMPs32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
224    %38:vccr = MVE_VCMPs32r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg
225
226  bb.18:
227    %39:vccr = MVE_VCMPs8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
228    %40:vccr = MVE_VCMPs8r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg
229
230  bb.19:
231    %41:vccr = MVE_VCMPu16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
232    %42:vccr = MVE_VCMPu16r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg
233
234  bb.20:
235    %43:vccr = MVE_VCMPu32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
236    %44:vccr = MVE_VCMPu32r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg
237
238  bb.21:
239    %45:vccr = MVE_VCMPu8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
240    %46:vccr = MVE_VCMPu8r %1:mqpr, %25:gprwithzr, 11, 0, $noreg, $noreg
241
242  bb.22:
243    ; There shouldn't be any exception for $zr, so the second VCMP should
244    ; be transformed into a VPNOT.
245    %47:vccr = MVE_VCMPu8r %1:mqpr, $zr, 10, 0, $noreg, $noreg
246    %48:vccr = MVE_VCMPu8r %1:mqpr, $zr, 11, 0, $noreg, $noreg
247    tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
248...
249---
250name:            vcmp_with_opposite_cond_and_swapped_operands
251alignment:       4
252body:             |
253  ; CHECK-LABEL: name: vcmp_with_opposite_cond_and_swapped_operands
254  ; CHECK: bb.0:
255  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
256  ; CHECK-NEXT: {{  $}}
257  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF
258  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF
259  ; CHECK-NEXT:   [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
260  ; CHECK-NEXT:   [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16_]], 0, $noreg, $noreg
261  ; CHECK-NEXT: {{  $}}
262  ; CHECK-NEXT: bb.1:
263  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
264  ; CHECK-NEXT: {{  $}}
265  ; CHECK-NEXT:   [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
266  ; CHECK-NEXT:   [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32_]], 0, $noreg, $noreg
267  ; CHECK-NEXT: {{  $}}
268  ; CHECK-NEXT: bb.2:
269  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
270  ; CHECK-NEXT: {{  $}}
271  ; CHECK-NEXT:   [[MVE_VCMPi8_:%[0-9]+]]:vccr = MVE_VCMPi8 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
272  ; CHECK-NEXT:   [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8_]], 0, $noreg, $noreg
273  ; CHECK-NEXT: {{  $}}
274  ; CHECK-NEXT: bb.3:
275  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
276  ; CHECK-NEXT: {{  $}}
277  ; CHECK-NEXT:   [[MVE_VCMPs16_:%[0-9]+]]:vccr = MVE_VCMPs16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
278  ; CHECK-NEXT:   [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16_]], 0, $noreg, $noreg
279  ; CHECK-NEXT: {{  $}}
280  ; CHECK-NEXT: bb.4:
281  ; CHECK-NEXT:   successors: %bb.5(0x80000000)
282  ; CHECK-NEXT: {{  $}}
283  ; CHECK-NEXT:   [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
284  ; CHECK-NEXT:   [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
285  ; CHECK-NEXT: {{  $}}
286  ; CHECK-NEXT: bb.5:
287  ; CHECK-NEXT:   successors: %bb.6(0x80000000)
288  ; CHECK-NEXT: {{  $}}
289  ; CHECK-NEXT:   [[MVE_VCMPs8_:%[0-9]+]]:vccr = MVE_VCMPs8 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
290  ; CHECK-NEXT:   [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8_]], 0, $noreg, $noreg
291  ; CHECK-NEXT: {{  $}}
292  ; CHECK-NEXT: bb.6:
293  ; CHECK-NEXT:   successors: %bb.7(0x80000000)
294  ; CHECK-NEXT: {{  $}}
295  ; CHECK-NEXT:   [[MVE_VCMPu16_:%[0-9]+]]:vccr = MVE_VCMPu16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
296  ; CHECK-NEXT:   [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16_]], 0, $noreg, $noreg
297  ; CHECK-NEXT: {{  $}}
298  ; CHECK-NEXT: bb.7:
299  ; CHECK-NEXT:   successors: %bb.8(0x80000000)
300  ; CHECK-NEXT: {{  $}}
301  ; CHECK-NEXT:   [[MVE_VCMPu32_:%[0-9]+]]:vccr = MVE_VCMPu32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
302  ; CHECK-NEXT:   [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32_]], 0, $noreg, $noreg
303  ; CHECK-NEXT: {{  $}}
304  ; CHECK-NEXT: bb.8:
305  ; CHECK-NEXT:   [[MVE_VCMPu8_:%[0-9]+]]:vccr = MVE_VCMPu8 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
306  ; CHECK-NEXT:   [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8_]], 0, $noreg, $noreg
307  ; CHECK-NEXT:   tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]
308  ;
309  ; Tests that VCMPs with an opposite condition and swapped operands are
310  ; correctly converted into VPNOTs.
311  ;
312  bb.0:
313    %1:mqpr = IMPLICIT_DEF
314    %2:mqpr = IMPLICIT_DEF
315    %0:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
316    %3:vccr = MVE_VCMPi16 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
317
318  bb.1:
319    %4:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
320    %5:vccr = MVE_VCMPi32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
321
322  bb.2:
323    %6:vccr = MVE_VCMPi8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
324    %7:vccr = MVE_VCMPi8 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
325
326  bb.3:
327    %8:vccr = MVE_VCMPs16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
328    %9:vccr = MVE_VCMPs16 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
329
330  bb.4:
331    %10:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
332    %11:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
333
334  bb.5:
335    %12:vccr = MVE_VCMPs8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
336    %13:vccr = MVE_VCMPs8 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
337
338  bb.6:
339    %14:vccr = MVE_VCMPu16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
340    %15:vccr = MVE_VCMPu16 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
341
342  bb.7:
343    %16:vccr = MVE_VCMPu32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
344    %17:vccr = MVE_VCMPu32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
345
346  bb.8:
347    %18:vccr = MVE_VCMPu8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
348    %19:vccr = MVE_VCMPu8 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
349    tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
350
351...
352
353...
354---
355name:            triple_vcmp
356alignment:       4
357body:             |
358  ;
359  ; Tests that, when there are 2 "VPNOT-like VCMPs" in a row, only the first
360  ; becomes a VPNOT.
361  ;
362  bb.0:
363    ; CHECK-LABEL: name: triple_vcmp
364    ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
365    ; CHECK-NEXT: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
366    ; CHECK-NEXT: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
367    ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
368    %2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
369    %3:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
370    %4:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
371    tBX_RET 14, $noreg, implicit %0:mqpr
372...
373---
374name:            killed_vccr_values
375alignment:       4
376body:             |
377  ; CHECK-LABEL: name: killed_vccr_values
378  ; CHECK: bb.0:
379  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
380  ; CHECK-NEXT: {{  $}}
381  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF
382  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF
383  ; CHECK-NEXT:   [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
384  ; CHECK-NEXT:   [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF1]], 1, [[MVE_VCMPf16_]], $noreg, undef [[MVE_VORR]]
385  ; CHECK-NEXT:   [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16_]], 0, $noreg, $noreg
386  ; CHECK-NEXT: {{  $}}
387  ; CHECK-NEXT: bb.1:
388  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
389  ; CHECK-NEXT: {{  $}}
390  ; CHECK-NEXT:   [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
391  ; CHECK-NEXT:   [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
392  ; CHECK-NEXT:   [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR1]]
393  ; CHECK-NEXT:   [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT1]], 0, $noreg, $noreg
394  ; CHECK-NEXT:   [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR1]], [[MVE_VORR1]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR2]]
395  ; CHECK-NEXT: {{  $}}
396  ; CHECK-NEXT: bb.2:
397  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
398  ; CHECK-NEXT: {{  $}}
399  ; CHECK-NEXT:   [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
400  ; CHECK-NEXT:   [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg, $noreg
401  ; CHECK-NEXT:   [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT3]], $noreg, undef [[MVE_VORR3]]
402  ; CHECK-NEXT:   [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT3]], 0, $noreg, $noreg
403  ; CHECK-NEXT:   [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR3]], [[MVE_VORR3]], 1, [[MVE_VPNOT4]], $noreg, undef [[MVE_VORR4]]
404  ; CHECK-NEXT: {{  $}}
405  ; CHECK-NEXT: bb.3:
406  ; CHECK-NEXT:   [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
407  ; CHECK-NEXT:   [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_2]], 0, $noreg, $noreg
408  ; CHECK-NEXT:   [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT5]], $noreg, undef [[MVE_VORR5]]
409  ; CHECK-NEXT:   [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT5]], 0, $noreg, $noreg
410  ; CHECK-NEXT:   [[MVE_VORR6:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR5]], [[MVE_VORR5]], 1, [[MVE_VPNOT6]], $noreg, undef [[MVE_VORR6]]
411  ; CHECK-NEXT:   [[MVE_VORR7:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR6]], [[MVE_VORR6]], 1, [[MVE_VPNOT6]], $noreg, undef [[MVE_VORR7]]
412  ; CHECK-NEXT:   tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]
413  bb.0:
414    ;
415    ; Tests that, if the result of the VCMP is killed before the
416    ; second VCMP (that will be converted into a VPNOT) is found,
417    ; the kill flag is removed.
418    ;
419    %1:mqpr = IMPLICIT_DEF
420    %2:mqpr = IMPLICIT_DEF
421    %0:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
422    %3:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, killed %0, $noreg, undef %3
423    %4:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 11, 0, $noreg, $noreg
424  bb.1:
425    ;
426    ; Tests that, if the result of the VCMP that has been replaced with a
427    ; VPNOT is killed (before the insertion of the second VPNOT),
428    ; the kill flag is removed.
429    ;
430    %5:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
431    %6:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
432    %7:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, killed %6, $noreg, undef %7
433    %8:mqpr = MVE_VORR %7, %7, 1, %5, $noreg, undef %8
434  bb.2:
435    ;
436    ; Tests that the kill flag is removed when inserting a VPNOT for
437    ; an instruction.
438    ;
439    %9:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
440    %10:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
441    %11:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %10, $noreg, undef %11
442    %12:mqpr = MVE_VORR %11, %11, 1, killed %9, $noreg, undef %12
443  bb.3:
444    ;
445    ; Tests that the kill flag is correctly removed when replacing a use
446    ; of the opposite vccr, $noreg value with the last VPNOT's result
447    ;
448    %13:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
449    %14:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
450    %15:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %14, $noreg, undef %15
451    %16:mqpr = MVE_VORR %15, %15, 1, %13, $noreg, undef %16
452    %17:mqpr = MVE_VORR %16, %16, 1, killed %13, $noreg, undef %17
453    tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
454
455...
456---
457name:            predicated_vcmps
458alignment:       4
459body:             |
460  ; CHECK-LABEL: name: predicated_vcmps
461  ; CHECK: bb.0:
462  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
463  ; CHECK-NEXT: {{  $}}
464  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF
465  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF
466  ; CHECK-NEXT:   [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
467  ; CHECK-NEXT:   [[MVE_VCMPi16_1:%[0-9]+]]:vccr = MVE_VCMPi16 [[DEF1]], [[DEF]], 12, 1, [[MVE_VCMPi16_]], $noreg
468  ; CHECK-NEXT:   [[MVE_VCMPi16_2:%[0-9]+]]:vccr = MVE_VCMPi16 [[DEF]], [[DEF1]], 10, 1, [[MVE_VCMPi16_]], $noreg
469  ; CHECK-NEXT: {{  $}}
470  ; CHECK-NEXT: bb.1:
471  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
472  ; CHECK-NEXT: {{  $}}
473  ; CHECK-NEXT:   [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
474  ; CHECK-NEXT:   [[MVE_VCMPi32_1:%[0-9]+]]:vccr = MVE_VCMPi32 [[DEF1]], [[DEF]], 12, 1, [[MVE_VCMPi32_]], $noreg
475  ; CHECK-NEXT:   [[MVE_VCMPi32_2:%[0-9]+]]:vccr = MVE_VCMPi32 [[DEF]], [[DEF1]], 10, 1, [[MVE_VCMPi32_]], $noreg
476  ; CHECK-NEXT: {{  $}}
477  ; CHECK-NEXT: bb.2:
478  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
479  ; CHECK-NEXT: {{  $}}
480  ; CHECK-NEXT:   [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
481  ; CHECK-NEXT:   [[MVE_VCMPf16_1:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF]], [[DEF1]], 11, 1, [[MVE_VCMPf16_]], $noreg
482  ; CHECK-NEXT:   [[MVE_VCMPf16_2:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF]], [[DEF1]], 10, 1, [[MVE_VCMPf16_]], $noreg
483  ; CHECK-NEXT: {{  $}}
484  ; CHECK-NEXT: bb.3:
485  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
486  ; CHECK-NEXT: {{  $}}
487  ; CHECK-NEXT:   [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
488  ; CHECK-NEXT:   [[MVE_VCMPf32_1:%[0-9]+]]:vccr = MVE_VCMPf32 [[DEF]], [[DEF1]], 11, 1, [[MVE_VCMPf32_]], $noreg
489  ; CHECK-NEXT:   [[MVE_VCMPf32_2:%[0-9]+]]:vccr = MVE_VCMPf32 [[DEF]], [[DEF1]], 10, 1, [[MVE_VCMPf32_]], $noreg
490  ; CHECK-NEXT: {{  $}}
491  ; CHECK-NEXT: bb.4:
492  ; CHECK-NEXT:   successors: %bb.5(0x80000000)
493  ; CHECK-NEXT: {{  $}}
494  ; CHECK-NEXT:   [[MVE_VCMPi16_3:%[0-9]+]]:vccr = MVE_VCMPi16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
495  ; CHECK-NEXT:   [[MVE_VCMPi16_4:%[0-9]+]]:vccr = MVE_VCMPi16 [[DEF]], [[DEF1]], 11, 1, [[MVE_VCMPi16_3]], $noreg
496  ; CHECK-NEXT:   [[MVE_VCMPi16_5:%[0-9]+]]:vccr = MVE_VCMPi16 [[DEF]], [[DEF1]], 10, 1, [[MVE_VCMPi16_3]], $noreg
497  ; CHECK-NEXT: {{  $}}
498  ; CHECK-NEXT: bb.5:
499  ; CHECK-NEXT:   [[MVE_VCMPi32_3:%[0-9]+]]:vccr = MVE_VCMPi32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
500  ; CHECK-NEXT:   [[MVE_VCMPi32_4:%[0-9]+]]:vccr = MVE_VCMPi32 [[DEF]], [[DEF1]], 11, 1, [[MVE_VCMPi32_3]], $noreg
501  ; CHECK-NEXT:   [[MVE_VCMPi32_5:%[0-9]+]]:vccr = MVE_VCMPi32 [[DEF]], [[DEF1]], 10, 1, [[MVE_VCMPi32_3]], $noreg
502  ; CHECK-NEXT:   tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]
503  ;
504  ; Tests that predicated VCMPs are not replaced.
505  ;
506  bb.0:
507    %1:mqpr = IMPLICIT_DEF
508    %2:mqpr = IMPLICIT_DEF
509    %0:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
510    %3:vccr = MVE_VCMPi16 %2:mqpr, %1:mqpr, 12, 1, %0, $noreg
511    %4:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 1, %0, $noreg
512
513  bb.1:
514    %5:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
515    %6:vccr = MVE_VCMPi32 %2:mqpr, %1:mqpr, 12, 1, %5, $noreg
516    %7:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 1, %5, $noreg
517
518  bb.2:
519    %8:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
520    %9:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 11, 1, %8, $noreg
521    %10:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 1, %8, $noreg
522
523  bb.3:
524    %11:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
525    %12:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 11, 1, %11, $noreg
526    %13:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 1, %11, $noreg
527
528  bb.4:
529    %14:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
530    %15:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 11, 1, %14, $noreg
531    %16:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 1, %14, $noreg
532
533  bb.5:
534    %17:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
535    %18:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 11, 1, %17, $noreg
536    %19:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 1, %17, $noreg
537    tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
538...
539---
540name:            flt_with_swapped_operands
541alignment:       4
542body:             |
543  ; CHECK-LABEL: name: flt_with_swapped_operands
544  ; CHECK: bb.0:
545  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
546  ; CHECK-NEXT: {{  $}}
547  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF
548  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF
549  ; CHECK-NEXT:   [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
550  ; CHECK-NEXT:   [[MVE_VCMPf16_1:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF1]], [[DEF]], 12, 0, $noreg, $noreg
551  ; CHECK-NEXT: {{  $}}
552  ; CHECK-NEXT: bb.1:
553  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
554  ; CHECK-NEXT: {{  $}}
555  ; CHECK-NEXT:   [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
556  ; CHECK-NEXT:   [[MVE_VCMPf32_1:%[0-9]+]]:vccr = MVE_VCMPf32 [[DEF1]], [[DEF]], 12, 0, $noreg, $noreg
557  ; CHECK-NEXT: {{  $}}
558  ; CHECK-NEXT: bb.2:
559  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
560  ; CHECK-NEXT: {{  $}}
561  ; CHECK-NEXT:   [[MVE_VCMPf16_2:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
562  ; CHECK-NEXT:   [[MVE_VCMPf16_3:%[0-9]+]]:vccr = MVE_VCMPf16 [[DEF1]], [[DEF]], 11, 0, $noreg, $noreg
563  ; CHECK-NEXT: {{  $}}
564  ; CHECK-NEXT: bb.3:
565  ; CHECK-NEXT:   [[MVE_VCMPf32_2:%[0-9]+]]:vccr = MVE_VCMPf32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
566  ; CHECK-NEXT:   [[MVE_VCMPf32_3:%[0-9]+]]:vccr = MVE_VCMPf32 [[DEF1]], [[DEF]], 11, 0, $noreg, $noreg
567  ; CHECK-NEXT:   tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]
568  ;
569  ; Tests that float VCMPs with an opposite condition and swapped operands
570  ; are not transformed into VPNOTs.
571  ;
572  bb.0:
573    %1:mqpr = IMPLICIT_DEF
574    %2:mqpr = IMPLICIT_DEF
575    %0:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
576    %3:vccr = MVE_VCMPf16 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
577
578  bb.1:
579    %4:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
580    %5:vccr = MVE_VCMPf32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
581
582  bb.2:
583    %6:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
584    %7:vccr = MVE_VCMPf16 %2:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
585
586  bb.3:
587    %8:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
588    %9:vccr = MVE_VCMPf32 %2:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
589    tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
590
591...
592---
593name:            different_opcodes
594alignment:       4
595body:             |
596  ;
597  ; Tests that a "VPNOT-like VCMP" with an opcode different from the previous VCMP
598  ; is not transformed into a VPNOT.
599  ;
600  bb.0:
601    ; CHECK-LABEL: name: different_opcodes
602    ; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 0, 0, $noreg, $noreg
603    ; CHECK-NEXT: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 1, 1, $noreg, $noreg
604    ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
605    %0:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 0, 0, $noreg, $noreg
606    %3:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 1, 1, $noreg, $noreg
607    tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
608...
609---
610name:            incorrect_condcode
611alignment:       4
612body:             |
613  ; CHECK-LABEL: name: incorrect_condcode
614  ; CHECK: bb.0:
615  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
616  ; CHECK-NEXT: {{  $}}
617  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF
618  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF
619  ; CHECK-NEXT:   [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
620  ; CHECK-NEXT:   [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF1]], [[DEF]], 11, 0, $noreg, $noreg
621  ; CHECK-NEXT: {{  $}}
622  ; CHECK-NEXT: bb.1:
623  ; CHECK-NEXT:   [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
624  ; CHECK-NEXT:   [[MVE_VCMPs32_3:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 12, 0, $noreg, $noreg
625  ; CHECK-NEXT:   tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]
626  ;
627  ; Tests that a VCMP is not transformed into a VPNOT if its CondCode is not
628  ; the opposite CondCode.
629  ;
630  bb.0:
631    %1:mqpr = IMPLICIT_DEF
632    %2:mqpr = IMPLICIT_DEF
633    %0:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
634    %3:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
635
636  bb.1:
637    %4:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
638    %5:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 12, 0, $noreg, $noreg
639    tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
640
641...
642---
643name:            vpr_or_vccr_write_between_vcmps
644alignment:       4
645body:             |
646  ;
647  ; Tests that a "VPNOT-like VCMP" will not be transformed into a VPNOT if
648  ; VCCR/VPR is written to in-between.
649  ;
650  bb.0:
651    ; CHECK-LABEL: name: vpr_or_vccr_write_between_vcmps
652    ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 12, 0, $noreg, $noreg
653    ; CHECK-NEXT: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT killed [[MVE_VCMPs32_]], 0, $noreg, $noreg
654    ; CHECK-NEXT: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
655    ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
656    %0:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 12, 0, $noreg, $noreg
657    %3:vccr = MVE_VPNOT killed %0, 0, $noreg, $noreg
658    %4:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
659    tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
660...
661---
662name:            spill_prevention
663alignment:       4
664body:             |
665  ; CHECK-LABEL: name: spill_prevention
666  ; CHECK: bb.0:
667  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
668  ; CHECK-NEXT: {{  $}}
669  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF
670  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF
671  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:gpr = IMPLICIT_DEF
672  ; CHECK-NEXT:   [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
673  ; CHECK-NEXT:   [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
674  ; CHECK-NEXT:   [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR]]
675  ; CHECK-NEXT:   [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT]], 0, $noreg, $noreg
676  ; CHECK-NEXT:   [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR]], 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR1]]
677  ; CHECK-NEXT:   [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT1]], 0, $noreg, $noreg
678  ; CHECK-NEXT:   [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR1]], [[MVE_VORR1]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR2]]
679  ; CHECK-NEXT:   [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT2]], 0, $noreg, $noreg
680  ; CHECK-NEXT:   [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR2]], [[MVE_VORR2]], 1, [[MVE_VPNOT3]], $noreg, undef [[MVE_VORR3]]
681  ; CHECK-NEXT:   [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT3]], 0, $noreg, $noreg
682  ; CHECK-NEXT:   [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR3]], [[MVE_VORR3]], 1, [[MVE_VPNOT4]], $noreg, undef [[MVE_VORR4]]
683  ; CHECK-NEXT: {{  $}}
684  ; CHECK-NEXT: bb.1:
685  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
686  ; CHECK-NEXT: {{  $}}
687  ; CHECK-NEXT:   [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
688  ; CHECK-NEXT:   [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg, $noreg
689  ; CHECK-NEXT:   [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT5]], $noreg, undef [[MVE_VORR5]]
690  ; CHECK-NEXT:   [[MVE_VORR6:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR5]], [[MVE_VORR5]], 0, $noreg, $noreg, undef [[MVE_VORR6]]
691  ; CHECK-NEXT:   [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT5]], 0, $noreg, $noreg
692  ; CHECK-NEXT:   [[MVE_VORR7:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR6]], [[MVE_VORR6]], 1, [[MVE_VPNOT6]], $noreg, undef [[MVE_VORR7]]
693  ; CHECK-NEXT:   [[MVE_VORR8:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR7]], [[MVE_VORR7]], 0, $noreg, $noreg, undef [[MVE_VORR8]]
694  ; CHECK-NEXT:   [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT6]], 0, $noreg, $noreg
695  ; CHECK-NEXT:   [[MVE_VORR9:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR8]], [[MVE_VORR8]], 1, [[MVE_VPNOT7]], $noreg, undef [[MVE_VORR9]]
696  ; CHECK-NEXT: {{  $}}
697  ; CHECK-NEXT: bb.2:
698  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
699  ; CHECK-NEXT: {{  $}}
700  ; CHECK-NEXT:   [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
701  ; CHECK-NEXT:   [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_2]], 0, $noreg, $noreg
702  ; CHECK-NEXT:   [[MVE_VORR10:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT8]], $noreg, undef [[MVE_VORR10]]
703  ; CHECK-NEXT:   [[MVE_VORR11:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR10]], [[MVE_VORR10]], 1, [[MVE_VPNOT8]], $noreg, undef [[MVE_VORR11]]
704  ; CHECK-NEXT:   [[MVE_VPNOT9:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT8]], 0, $noreg, $noreg
705  ; CHECK-NEXT:   [[MVE_VORR12:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR11]], [[MVE_VORR11]], 1, [[MVE_VPNOT9]], $noreg, undef [[MVE_VORR12]]
706  ; CHECK-NEXT:   [[MVE_VORR13:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR12]], [[MVE_VORR12]], 1, [[MVE_VPNOT9]], $noreg, undef [[MVE_VORR13]]
707  ; CHECK-NEXT:   [[MVE_VPNOT10:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT9]], 0, $noreg, $noreg
708  ; CHECK-NEXT:   [[MVE_VORR14:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR13]], [[MVE_VORR13]], 1, [[MVE_VPNOT10]], $noreg, undef [[MVE_VORR14]]
709  ; CHECK-NEXT:   [[MVE_VORR15:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR14]], [[MVE_VORR14]], 1, [[MVE_VPNOT10]], $noreg, undef [[MVE_VORR15]]
710  ; CHECK-NEXT:   [[MVE_VPNOT11:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT10]], 0, $noreg, $noreg
711  ; CHECK-NEXT:   [[MVE_VORR16:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR15]], [[MVE_VORR15]], 1, [[MVE_VPNOT11]], $noreg, undef [[MVE_VORR16]]
712  ; CHECK-NEXT:   [[MVE_VORR17:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR16]], [[MVE_VORR16]], 1, [[MVE_VPNOT11]], $noreg, undef [[MVE_VORR17]]
713  ; CHECK-NEXT: {{  $}}
714  ; CHECK-NEXT: bb.3:
715  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
716  ; CHECK-NEXT: {{  $}}
717  ; CHECK-NEXT:   [[MVE_VCMPs32_3:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
718  ; CHECK-NEXT:   [[MVE_VPNOT12:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_3]], 0, $noreg, $noreg
719  ; CHECK-NEXT:   [[MVE_VORR18:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT12]], $noreg, undef [[MVE_VORR11]]
720  ; CHECK-NEXT:   [[MVE_VPNOT13:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT12]], 0, $noreg, $noreg
721  ; CHECK-NEXT:   [[MVE_VORR19:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT13]], $noreg, undef [[MVE_VORR19]]
722  ; CHECK-NEXT: {{  $}}
723  ; CHECK-NEXT: bb.4:
724  ; CHECK-NEXT:   [[VMSR_P0_:%[0-9]+]]:vccr = VMSR_P0 killed [[DEF2]], 14 /* CC::al */, $noreg
725  ; CHECK-NEXT:   [[MVE_VPNOT14:%[0-9]+]]:vccr = MVE_VPNOT [[VMSR_P0_]], 0, $noreg, $noreg
726  ; CHECK-NEXT:   [[MVE_VORR20:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR19]], [[MVE_VORR19]], 1, [[MVE_VPNOT14]], $noreg, undef [[MVE_VORR20]]
727  ; CHECK-NEXT:   [[MVE_VPNOT15:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT14]], 0, $noreg, $noreg
728  ; CHECK-NEXT:   [[MVE_VORR21:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR20]], [[MVE_VORR20]], 1, [[MVE_VPNOT15]], $noreg, undef [[MVE_VORR21]]
729  ; CHECK-NEXT:   [[MVE_VPNOT16:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT15]], 0, $noreg, $noreg
730  ; CHECK-NEXT:   [[MVE_VORR22:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR21]], [[MVE_VORR21]], 1, [[MVE_VPNOT16]], $noreg, undef [[MVE_VORR22]]
731  ; CHECK-NEXT:   [[MVE_VPNOT17:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT16]], 0, $noreg, $noreg
732  ; CHECK-NEXT:   [[MVE_VORR23:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR22]], [[MVE_VORR22]], 1, [[MVE_VPNOT17]], $noreg, undef [[MVE_VORR23]]
733  ; CHECK-NEXT:   [[MVE_VPNOT18:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT17]], 0, $noreg, $noreg
734  ; CHECK-NEXT:   [[MVE_VORR24:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR23]], [[MVE_VORR23]], 1, [[MVE_VPNOT18]], $noreg, undef [[MVE_VORR24]]
735  ; CHECK-NEXT:   tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]
736  bb.0:
737    ;
738    ; Basic test case
739    ;
740
741    %1:mqpr = IMPLICIT_DEF
742    %2:mqpr = IMPLICIT_DEF
743    %32:gpr = IMPLICIT_DEF
744    %0:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
745    %3:vccr = MVE_VPNOT %0, 0, $noreg, $noreg
746    %4:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %3, $noreg, undef %4
747    %5:mqpr = MVE_VORR %4, %4, 1, %0, $noreg, undef %5
748    %6:mqpr = MVE_VORR %5, %5, 1, %3, $noreg, undef %6
749    %7:mqpr = MVE_VORR %6, %6, 1, %0, $noreg, undef %7
750    %8:mqpr = MVE_VORR %7, %7, 1, %3, $noreg, undef %8
751  bb.1:
752    ;
753    ; Tests that unpredicated instructions in the middle of the block
754    ; don't interfere with the replacement.
755    ;
756    %9:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
757    %10:vccr = MVE_VPNOT %9, 0, $noreg, $noreg
758    %11:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %10, $noreg, undef %11
759    %12:mqpr = MVE_VORR %11, %11, 0, $noreg, $noreg, undef %12
760    %13:mqpr = MVE_VORR %12, %12, 1, %9, $noreg, undef %13
761    %14:mqpr = MVE_VORR %13, %13, 0, $noreg, $noreg, undef %14
762    %15:mqpr = MVE_VORR %14, %14, 1, %10, $noreg, undef %15
763  bb.2:
764    ;
765    ; Tests that all uses of the register are replaced, even when it's used
766    ; multiple times in a row.
767    ;
768    %16:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
769    %17:vccr = MVE_VPNOT %16, 0, $noreg, $noreg
770    %18:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %17, $noreg, undef %18
771    %19:mqpr = MVE_VORR %18, %18, 1, %17, $noreg, undef %19
772    %20:mqpr = MVE_VORR %19, %19, 1, %16, $noreg, undef %20
773    %21:mqpr = MVE_VORR %20, %20, 1, %16, $noreg, undef %21
774    %22:mqpr = MVE_VORR %21, %21, 1, %17, $noreg, undef %22
775    %23:mqpr = MVE_VORR %22, %22, 1, %17, $noreg, undef %23
776    %24:mqpr = MVE_VORR %23, %23, 1, %16, $noreg, undef %24
777    %25:mqpr = MVE_VORR %24, %24, 1, %16, $noreg, undef %25
778
779  bb.3:
780    ;
781    ; Tests that already present VPNOTs are "registered" by the pass so
782    ; it does not insert a useless VPNOT.
783    ;
784    %26:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
785    %27:vccr = MVE_VPNOT %26, 0, $noreg, $noreg
786    %28:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %27, $noreg, undef %19
787    %29:vccr = MVE_VPNOT %27, 0, $noreg, $noreg
788    %30:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %26, $noreg, undef %30
789  bb.4:
790    ;
791    ; Tests that the pass works with instructions other than vcmp.
792    ;
793    %31:vccr = VMSR_P0 killed %32:gpr, 14 /* CC::al */, $noreg
794    %33:vccr = MVE_VPNOT %31, 0, $noreg, $noreg
795    %34:mqpr = MVE_VORR %30, %30, 1, %33, $noreg, undef %34
796    %35:mqpr = MVE_VORR %34, %34, 1, %31, $noreg, undef %35
797    %36:mqpr = MVE_VORR %35, %35, 1, %33, $noreg, undef %36
798    %37:mqpr = MVE_VORR %36, %36, 1, %31, $noreg, undef %37
799    %38:mqpr = MVE_VORR %37, %37, 1, %33, $noreg, undef %38
800    tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
801...
802---
803name:            spill_prevention_multi
804alignment:       4
805body:             |
806  bb.0:
807    ;
808    ; Tests that multiple groups of predicated instructions in the same basic block are optimized.
809    ;
810    ; CHECK-LABEL: name: spill_prevention_multi
811    ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
812    ; CHECK-NEXT: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
813    ; CHECK-NEXT: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR]]
814    ; CHECK-NEXT: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT]], 0, $noreg, $noreg
815    ; CHECK-NEXT: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR]], 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR1]]
816    ; CHECK-NEXT: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT1]], 0, $noreg, $noreg
817    ; CHECK-NEXT: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR1]], [[MVE_VORR1]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR2]]
818    ; CHECK-NEXT: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT2]], 0, $noreg, $noreg
819    ; CHECK-NEXT: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR2]], [[MVE_VORR2]], 1, [[MVE_VPNOT3]], $noreg, undef [[MVE_VORR3]]
820    ; CHECK-NEXT: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
821    ; CHECK-NEXT: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VCMPs32_1]], $noreg, undef [[MVE_VORR4]]
822    ; CHECK-NEXT: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg, $noreg
823    ; CHECK-NEXT: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR4]], [[MVE_VORR4]], 1, [[MVE_VPNOT4]], $noreg, undef [[MVE_VORR5]]
824    ; CHECK-NEXT: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT4]], 0, $noreg, $noreg
825    ; CHECK-NEXT: [[MVE_VORR6:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR5]], [[MVE_VORR5]], 1, [[MVE_VPNOT5]], $noreg, undef [[MVE_VORR6]]
826    ; CHECK-NEXT: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT5]], 0, $noreg, $noreg
827    ; CHECK-NEXT: [[MVE_VORR7:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR6]], [[MVE_VORR6]], 1, [[MVE_VPNOT6]], $noreg, undef [[MVE_VORR7]]
828    ; CHECK-NEXT: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
829    ; CHECK-NEXT: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_2]], 0, $noreg, $noreg
830    ; CHECK-NEXT: [[MVE_VORR8:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT7]], $noreg, undef [[MVE_VORR8]]
831    ; CHECK-NEXT: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT7]], 0, $noreg, $noreg
832    ; CHECK-NEXT: [[MVE_VORR9:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR8]], [[MVE_VORR8]], 1, [[MVE_VPNOT8]], $noreg, undef [[MVE_VORR9]]
833    ; CHECK-NEXT: [[MVE_VPNOT9:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT8]], 0, $noreg, $noreg
834    ; CHECK-NEXT: [[MVE_VORR10:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR9]], [[MVE_VORR9]], 1, [[MVE_VPNOT9]], $noreg, undef [[MVE_VORR10]]
835    ; CHECK-NEXT: [[MVE_VPNOT10:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT9]], 0, $noreg, $noreg
836    ; CHECK-NEXT: [[MVE_VORR11:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR10]], [[MVE_VORR10]], 1, [[MVE_VPNOT10]], $noreg, undef [[MVE_VORR11]]
837    ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
838    %0:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
839    %3:vccr = MVE_VPNOT %0, 0, $noreg, $noreg
840    %4:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %3, $noreg, undef %4
841    %5:mqpr = MVE_VORR %4, %4, 1, %0, $noreg, undef %5
842    %6:mqpr = MVE_VORR %5, %5, 1, %3, $noreg, undef %6
843    %7:mqpr = MVE_VORR %6, %6, 1, %0, $noreg, undef %7
844    %8:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
845    %9:vccr = MVE_VPNOT %8, 0, $noreg, $noreg
846    %10:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %8, $noreg, undef %10
847    %11:mqpr = MVE_VORR %10, %10, 1, %9, $noreg, undef %11
848    %12:mqpr = MVE_VORR %11, %11, 1, %8, $noreg, undef %12
849    %13:mqpr = MVE_VORR %12, %12, 1, %9, $noreg, undef %13
850    %14:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
851    %15:vccr = MVE_VPNOT %14, 0, $noreg, $noreg
852    %16:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %15, $noreg, undef %16
853    %17:mqpr = MVE_VORR %16, %16, 1, %14, $noreg, undef %17
854    %18:mqpr = MVE_VORR %17, %17, 1, %15, $noreg, undef %18
855    %19:mqpr = MVE_VORR %18, %18, 1, %14, $noreg, undef %19
856    tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
857...
858---
859name:            spill_prevention_predicated_vpnots
860alignment:       4
861body:             |
862  ; CHECK-LABEL: name: spill_prevention_predicated_vpnots
863  ; CHECK: bb.0:
864  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
865  ; CHECK-NEXT: {{  $}}
866  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF
867  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF
868  ; CHECK-NEXT:   [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
869  ; CHECK-NEXT:   [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 1, [[MVE_VCMPs32_]], $noreg
870  ; CHECK-NEXT:   [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VCMPs32_]], $noreg, undef [[MVE_VORR]]
871  ; CHECK-NEXT:   [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR]], 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR1]]
872  ; CHECK-NEXT: {{  $}}
873  ; CHECK-NEXT: bb.1:
874  ; CHECK-NEXT:   [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
875  ; CHECK-NEXT:   [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 1, [[MVE_VCMPs32_1]], $noreg
876  ; CHECK-NEXT:   [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF1]], 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR]]
877  ; CHECK-NEXT:   [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VCMPs32_1]], $noreg, undef [[MVE_VORR1]]
878  ; CHECK-NEXT:   [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR [[DEF1]], [[DEF]], 1, [[MVE_VPNOT1]], $noreg, undef %11:mqpr
879  ; CHECK-NEXT:   tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]
880  ;
881  ; Tests that predicated VPNOTs are not considered by this pass
882  ; (This means that these examples should not be optimized.)
883  ;
884  bb.0:
885    %1:mqpr = IMPLICIT_DEF
886    %2:mqpr = IMPLICIT_DEF
887    %0:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
888    %3:vccr = MVE_VPNOT %0, 1, %0, $noreg
889    %4:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %0, $noreg, undef %4
890    %5:mqpr = MVE_VORR %4, %4, 1, %3, $noreg, undef %5
891  bb.1:
892    %6:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
893    %7:vccr = MVE_VPNOT %0, 1, %6, $noreg
894    %8:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, %7, $noreg, undef %4
895    %9:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %6, $noreg, undef %5
896    %10:mqpr = MVE_VORR %2:mqpr, %1:mqpr, 1, %7, $noreg, undef %11:mqpr
897    tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
898...
899---
900name:            spill_prevention_copies
901alignment:       4
902body:             |
903  ;
904  ; Tests that VPNOTs are replaced by a COPY instead of inserting a VPNOT
905  ; (which would result in a double VPNOT).
906  ;
907  bb.0:
908    ; CHECK-LABEL: name: spill_prevention_copies
909    ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
910    ; CHECK-NEXT: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
911    ; CHECK-NEXT: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR]]
912    ; CHECK-NEXT: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR1]]
913    ; CHECK-NEXT: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR2]]
914    ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
915    %0:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
916    %3:vccr = MVE_VPNOT %0, 0, $noreg, $noreg
917    %4:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %3, $noreg, undef %4
918    %5:vccr = MVE_VPNOT %0, 0, $noreg, $noreg
919    %6:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %5, $noreg, undef %6
920    %7:vccr = MVE_VPNOT %0, 0, $noreg, $noreg
921    %8:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %7, $noreg, undef %8
922    tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
923
924...
925---
926name:            spill_prevention_vpnot_reordering
927alignment:       4
928body:             |
929  ; CHECK-LABEL: name: spill_prevention_vpnot_reordering
930  ; CHECK: bb.0:
931  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
932  ; CHECK-NEXT: {{  $}}
933  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF
934  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF
935  ; CHECK-NEXT:   [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
936  ; CHECK-NEXT:   [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF1]], 1, [[MVE_VCMPs32_]], $noreg, undef [[MVE_VORR]]
937  ; CHECK-NEXT:   [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[DEF1]], [[DEF]], 1, [[MVE_VCMPs32_]], $noreg, undef [[MVE_VORR1]]
938  ; CHECK-NEXT:   [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
939  ; CHECK-NEXT:   [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR1]], 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR2]]
940  ; CHECK-NEXT: {{  $}}
941  ; CHECK-NEXT: bb.1:
942  ; CHECK-NEXT:   [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
943  ; CHECK-NEXT:   [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF1]], 1, [[MVE_VCMPs32_1]], $noreg, undef [[MVE_VORR3]]
944  ; CHECK-NEXT:   [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR [[DEF1]], [[DEF]], 1, [[MVE_VCMPs32_1]], $noreg, undef [[MVE_VORR4]]
945  ; CHECK-NEXT:   [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg, $noreg
946  ; CHECK-NEXT:   [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR3]], [[MVE_VORR4]], 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR5]]
947  ; CHECK-NEXT:   tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF]]
948  ;
949  ; Tests that the first VPNOT is moved down when the result of the VCMP is used
950  ; before the first usage of the VPNOT's result.
951  ;
952  bb.0:
953    %1:mqpr = IMPLICIT_DEF
954    %2:mqpr = IMPLICIT_DEF
955    %0:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
956    %3:vccr = MVE_VPNOT %0, 0, $noreg, $noreg
957    %4:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, %0, $noreg, undef %4
958    %5:mqpr = MVE_VORR %2:mqpr, %1:mqpr, 1, %0, $noreg, undef %5
959    %6:mqpr = MVE_VORR %4, %5, 1, %3, $noreg, undef %6
960
961  bb.1:
962    ; Test again with a "killed" flag to check if it's properly removed.
963    %7:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
964    %8:vccr = MVE_VPNOT %7, 0, $noreg, $noreg
965    %9:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, %7, $noreg, undef %9
966    %10:mqpr = MVE_VORR %2:mqpr, %1:mqpr, 1, killed %7, $noreg, undef %10
967    %11:mqpr = MVE_VORR %9, %10, 1, %8, $noreg, undef %11
968    tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
969...
970---
971name:            spill_prevention_stop_after_write
972alignment:       4
973body:             |
974  ; CHECK-LABEL: name: spill_prevention_stop_after_write
975  ; CHECK: bb.0:
976  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
977  ; CHECK-NEXT: {{  $}}
978  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF
979  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF
980  ; CHECK-NEXT:   [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
981  ; CHECK-NEXT:   [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
982  ; CHECK-NEXT:   [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR]]
983  ; CHECK-NEXT:   [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT]], 0, $noreg, $noreg
984  ; CHECK-NEXT:   [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR]], 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR1]]
985  ; CHECK-NEXT:   [[VMSR_P0_:%[0-9]+]]:vccr = VMSR_P0 killed %7:gpr, 14 /* CC::al */, $noreg
986  ; CHECK-NEXT:   [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR1]], [[MVE_VORR1]], 1, [[MVE_VCMPs32_]], $noreg, undef [[MVE_VORR2]]
987  ; CHECK-NEXT:   [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR2]], [[MVE_VORR2]], 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR3]]
988  ; CHECK-NEXT: {{  $}}
989  ; CHECK-NEXT: bb.1:
990  ; CHECK-NEXT:   [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF]], [[DEF1]], 10, 0, $noreg, $noreg
991  ; CHECK-NEXT:   [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg, $noreg
992  ; CHECK-NEXT:   [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR]]
993  ; CHECK-NEXT:   [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT2]], 0, $noreg, $noreg
994  ; CHECK-NEXT:   [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR4]], [[MVE_VORR4]], 1, [[MVE_VPNOT3]], $noreg, undef [[MVE_VORR5]]
995  ; CHECK-NEXT:   [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 [[DEF1]], [[DEF]], 10, 0, $noreg, $noreg
996  ; CHECK-NEXT:   [[MVE_VORR6:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR5]], [[MVE_VORR5]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR6]]
997  ; CHECK-NEXT:   [[MVE_VORR7:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR6]], [[MVE_VORR6]], 1, [[MVE_VCMPs32_1]], $noreg, undef [[MVE_VORR7]]
998  ; CHECK-NEXT:   [[MVE_VORR8:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR7]], [[MVE_VORR7]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR8]]
999  ;
1000  ; Tests that the optimisation stops when it sees an instruction
1001  ; that writes to VPR, and that doesn't use any of the registers we care about.
1002  ;
1003  bb.0:
1004    %1:mqpr = IMPLICIT_DEF
1005    %2:mqpr = IMPLICIT_DEF
1006    %0:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
1007    %3:vccr = MVE_VPNOT %0, 0, $noreg, $noreg
1008    %4:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %3, $noreg, undef %4
1009    %5:mqpr = MVE_VORR %4, %4, 1, %0, $noreg, undef %5
1010    %6:vccr = VMSR_P0 killed %7:gpr, 14 /* CC::al */, $noreg
1011    %8:mqpr = MVE_VORR %5, %5, 1, %0, $noreg, undef %8
1012    %9:mqpr = MVE_VORR %8, %8, 1, %3, $noreg, undef %9
1013
1014  bb.1:
1015    %10:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
1016    %11:vccr = MVE_VPNOT %10, 0, $noreg, $noreg
1017    %12:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, %11, $noreg, undef %4
1018    %13:mqpr = MVE_VORR %12, %12, 1, %10, $noreg, undef %13
1019    %14:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
1020    %15:mqpr = MVE_VORR %13, %13, 1, %11, $noreg, undef %15
1021    %16:mqpr = MVE_VORR %15, %15, 1, %10, $noreg, undef %16
1022    %17:mqpr = MVE_VORR %16, %16, 1, %11, $noreg, undef %17
1023...
1024---
1025name:            reuse_kill_flags
1026alignment:       4
1027body:             |
1028  bb.0:
1029    ; CHECK-LABEL: name: reuse_kill_flags
1030    ; CHECK: [[t2MOVi:%[0-9]+]]:tgpreven = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
1031    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vccr = COPY [[t2MOVi]]
1032    ; CHECK-NEXT: [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF
1033    ; CHECK-NEXT: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[COPY]], $noreg, undef [[MVE_VORR]]
1034    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:mqpr = IMPLICIT_DEF
1035    ; CHECK-NEXT: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[DEF1]], [[DEF1]], 1, killed [[COPY]], $noreg, undef [[MVE_VORR1]]
1036    ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit [[DEF1]]
1037    %0:tgpreven = t2MOVi 0, 14, $noreg, $noreg
1038    %1:vccr = COPY %0:tgpreven
1039    %2:mqpr = IMPLICIT_DEF
1040    %3:mqpr = MVE_VORR %2:mqpr, %2:mqpr, 1, killed %1, $noreg, undef %3
1041    %4:vccr = COPY %0:tgpreven
1042    %5:mqpr = IMPLICIT_DEF
1043    %6:mqpr = MVE_VORR %5:mqpr, %5:mqpr, 1, killed %4, $noreg, undef %6
1044    tBX_RET 14 /* CC::al */, $noreg, implicit %5:mqpr
1045
1046...
1047