1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s 3 4define arm_aapcs_vfpcc <16 x i8> @vpsel_i8(<16 x i8> %mask, <16 x i8> %src1, <16 x i8> %src2) { 5; CHECK-LABEL: vpsel_i8: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vcmp.i8 ne, q0, zr 8; CHECK-NEXT: vpsel q0, q1, q2 9; CHECK-NEXT: bx lr 10entry: 11 %0 = icmp ne <16 x i8> %mask, zeroinitializer 12 %1 = select <16 x i1> %0, <16 x i8> %src1, <16 x i8> %src2 13 ret <16 x i8> %1 14} 15 16define arm_aapcs_vfpcc <8 x i16> @vpsel_i16(<8 x i16> %mask, <8 x i16> %src1, <8 x i16> %src2) { 17; CHECK-LABEL: vpsel_i16: 18; CHECK: @ %bb.0: @ %entry 19; CHECK-NEXT: vcmp.i16 ne, q0, zr 20; CHECK-NEXT: vpsel q0, q1, q2 21; CHECK-NEXT: bx lr 22entry: 23 %0 = icmp ne <8 x i16> %mask, zeroinitializer 24 %1 = select <8 x i1> %0, <8 x i16> %src1, <8 x i16> %src2 25 ret <8 x i16> %1 26} 27 28define arm_aapcs_vfpcc <4 x i32> @vpsel_i32(<4 x i32> %mask, <4 x i32> %src1, <4 x i32> %src2) { 29; CHECK-LABEL: vpsel_i32: 30; CHECK: @ %bb.0: @ %entry 31; CHECK-NEXT: vcmp.i32 ne, q0, zr 32; CHECK-NEXT: vpsel q0, q1, q2 33; CHECK-NEXT: bx lr 34entry: 35 %0 = icmp ne <4 x i32> %mask, zeroinitializer 36 %1 = select <4 x i1> %0, <4 x i32> %src1, <4 x i32> %src2 37 ret <4 x i32> %1 38} 39 40define arm_aapcs_vfpcc <2 x i64> @vpsel_i64(<2 x i64> %mask, <2 x i64> %src1, <2 x i64> %src2) { 41; CHECK-LABEL: vpsel_i64: 42; CHECK: @ %bb.0: @ %entry 43; CHECK-NEXT: vmov r0, r1, d0 44; CHECK-NEXT: movs r2, #0 45; CHECK-NEXT: vmov r12, r3, d1 46; CHECK-NEXT: orrs r0, r1 47; CHECK-NEXT: csetm r0, ne 48; CHECK-NEXT: bfi r2, r0, #0, #8 49; CHECK-NEXT: orrs.w r0, r12, r3 50; CHECK-NEXT: csetm r0, ne 51; CHECK-NEXT: bfi r2, r0, #8, #8 52; CHECK-NEXT: vmsr p0, r2 53; CHECK-NEXT: vpsel q0, q1, q2 54; CHECK-NEXT: bx lr 55entry: 56 %0 = icmp ne <2 x i64> %mask, zeroinitializer 57 %1 = select <2 x i1> %0, <2 x i64> %src1, <2 x i64> %src2 58 ret <2 x i64> %1 59} 60 61define arm_aapcs_vfpcc <8 x half> @vpsel_f16(<8 x i16> %mask, <8 x half> %src1, <8 x half> %src2) { 62; CHECK-LABEL: vpsel_f16: 63; CHECK: @ %bb.0: @ %entry 64; CHECK-NEXT: vcmp.i16 ne, q0, zr 65; CHECK-NEXT: vpsel q0, q1, q2 66; CHECK-NEXT: bx lr 67entry: 68 %0 = icmp ne <8 x i16> %mask, zeroinitializer 69 %1 = select <8 x i1> %0, <8 x half> %src1, <8 x half> %src2 70 ret <8 x half> %1 71} 72 73define arm_aapcs_vfpcc <4 x float> @vpsel_f32(<4 x i32> %mask, <4 x float> %src1, <4 x float> %src2) { 74; CHECK-LABEL: vpsel_f32: 75; CHECK: @ %bb.0: @ %entry 76; CHECK-NEXT: vcmp.i32 ne, q0, zr 77; CHECK-NEXT: vpsel q0, q1, q2 78; CHECK-NEXT: bx lr 79entry: 80 %0 = icmp ne <4 x i32> %mask, zeroinitializer 81 %1 = select <4 x i1> %0, <4 x float> %src1, <4 x float> %src2 82 ret <4 x float> %1 83} 84 85define arm_aapcs_vfpcc <2 x double> @vpsel_f64(<2 x i64> %mask, <2 x double> %src1, <2 x double> %src2) { 86; CHECK-LABEL: vpsel_f64: 87; CHECK: @ %bb.0: @ %entry 88; CHECK-NEXT: vmov r0, r1, d0 89; CHECK-NEXT: movs r2, #0 90; CHECK-NEXT: vmov r12, r3, d1 91; CHECK-NEXT: orrs r0, r1 92; CHECK-NEXT: csetm r0, ne 93; CHECK-NEXT: bfi r2, r0, #0, #8 94; CHECK-NEXT: orrs.w r0, r12, r3 95; CHECK-NEXT: csetm r0, ne 96; CHECK-NEXT: bfi r2, r0, #8, #8 97; CHECK-NEXT: vmsr p0, r2 98; CHECK-NEXT: vpsel q0, q1, q2 99; CHECK-NEXT: bx lr 100entry: 101 %0 = icmp ne <2 x i64> %mask, zeroinitializer 102 %1 = select <2 x i1> %0, <2 x double> %src1, <2 x double> %src2 103 ret <2 x double> %1 104} 105 106define arm_aapcs_vfpcc <4 x i32> @foo(<4 x i32> %vec.ind) { 107; CHECK-LABEL: foo: 108; CHECK: @ %bb.0: 109; CHECK-NEXT: vmov.i32 q2, #0x1 110; CHECK-NEXT: vmov.i32 q1, #0x0 111; CHECK-NEXT: vand q2, q0, q2 112; CHECK-NEXT: vcmp.i32 eq, q2, zr 113; CHECK-NEXT: vpsel q0, q0, q1 114; CHECK-NEXT: bx lr 115 %tmp = and <4 x i32> %vec.ind, <i32 1, i32 1, i32 1, i32 1> 116 %tmp1 = icmp eq <4 x i32> %tmp, zeroinitializer 117 %tmp2 = select <4 x i1> %tmp1, <4 x i32> %vec.ind, <4 x i32> zeroinitializer 118 ret <4 x i32> %tmp2 119} 120