1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s 3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s 4 5define arm_aapcs_vfpcc <8 x i16> @mov_int16_511() { 6; CHECK-LABEL: mov_int16_511: 7; CHECK: @ %bb.0: @ %entry 8; CHECK-NEXT: vmvn.i16 q0, #0xfe00 9; CHECK-NEXT: bx lr 10entry: 11 ret <8 x i16> <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511> 12} 13 14define arm_aapcs_vfpcc <8 x i16> @mov_int16_65281() { 15; CHECK-LABEL: mov_int16_65281: 16; CHECK: @ %bb.0: @ %entry 17; CHECK-NEXT: vmvn.i16 q0, #0xfe 18; CHECK-NEXT: bx lr 19entry: 20 ret <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281> 21} 22 23define arm_aapcs_vfpcc <4 x i32> @mov_int32_m7() { 24; CHECK-LABEL: mov_int32_m7: 25; CHECK: @ %bb.0: @ %entry 26; CHECK-NEXT: vmvn.i32 q0, #0x6 27; CHECK-NEXT: bx lr 28entry: 29 ret <4 x i32> <i32 -7, i32 -7, i32 -7, i32 -7> 30} 31 32define arm_aapcs_vfpcc <4 x i32> @mov_int32_m769() { 33; CHECK-LABEL: mov_int32_m769: 34; CHECK: @ %bb.0: @ %entry 35; CHECK-NEXT: vmvn.i32 q0, #0x300 36; CHECK-NEXT: bx lr 37entry: 38 ret <4 x i32> <i32 -769, i32 -769, i32 -769, i32 -769> 39} 40 41define arm_aapcs_vfpcc <4 x i32> @mov_int32_m262145() { 42; CHECK-LABEL: mov_int32_m262145: 43; CHECK: @ %bb.0: @ %entry 44; CHECK-NEXT: vmvn.i32 q0, #0x40000 45; CHECK-NEXT: bx lr 46entry: 47 ret <4 x i32> <i32 -262145, i32 -262145, i32 -262145, i32 -262145> 48} 49 50define arm_aapcs_vfpcc <4 x i32> @mov_int32_m134217729() { 51; CHECK-LABEL: mov_int32_m134217729: 52; CHECK: @ %bb.0: @ %entry 53; CHECK-NEXT: vmvn.i32 q0, #0x8000000 54; CHECK-NEXT: bx lr 55entry: 56 ret <4 x i32> <i32 -134217729, i32 -134217729, i32 -134217729, i32 -134217729> 57} 58 59define arm_aapcs_vfpcc <4 x i32> @mov_int32_4294902528() { 60; CHECK-LABEL: mov_int32_4294902528: 61; CHECK: @ %bb.0: @ %entry 62; CHECK-NEXT: vmvn.i32 q0, #0xfcff 63; CHECK-NEXT: bx lr 64entry: 65 ret <4 x i32> <i32 4294902528, i32 4294902528, i32 4294902528, i32 4294902528> 66} 67 68define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278386688() { 69; CHECK-LABEL: mov_int32_4278386688: 70; CHECK: @ %bb.0: @ %entry 71; CHECK-NEXT: movs r0, #0 72; CHECK-NEXT: movt r0, #65283 73; CHECK-NEXT: vdup.32 q0, r0 74; CHECK-NEXT: bx lr 75entry: 76 ret <4 x i32> <i32 4278386688, i32 4278386688, i32 4278386688, i32 4278386688> 77} 78