xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-vmull.ll (revision eecba950671629e656e90b5a948a58d3a86a375d) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
3
4define arm_aapcs_vfpcc <2 x i64> @sext_02(<4 x i32> %src1, <4 x i32> %src2) {
5; CHECK-LABEL: sext_02:
6; CHECK:       @ %bb.0: @ %entry
7; CHECK-NEXT:    vmullb.s32 q2, q0, q1
8; CHECK-NEXT:    vmov q0, q2
9; CHECK-NEXT:    bx lr
10entry:
11  %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
12  %out1 = sext <2 x i32> %shuf1 to <2 x i64>
13  %shuf2 = shufflevector <4 x i32> %src2, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
14  %out2 = sext <2 x i32> %shuf2 to <2 x i64>
15  %out = mul <2 x i64> %out1, %out2
16  ret <2 x i64> %out
17}
18
19define arm_aapcs_vfpcc <2 x i64> @sext_13(<4 x i32> %src1, <4 x i32> %src2) {
20; CHECK-LABEL: sext_13:
21; CHECK:       @ %bb.0: @ %entry
22; CHECK-NEXT:    vmullt.s32 q2, q0, q1
23; CHECK-NEXT:    vmov q0, q2
24; CHECK-NEXT:    bx lr
25entry:
26  %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
27  %out1 = sext <2 x i32> %shuf1 to <2 x i64>
28  %shuf2 = shufflevector <4 x i32> %src2, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
29  %out2 = sext <2 x i32> %shuf2 to <2 x i64>
30  %out = mul <2 x i64> %out1, %out2
31  ret <2 x i64> %out
32}
33
34define arm_aapcs_vfpcc <2 x i64> @zext_02(<4 x i32> %src1, <4 x i32> %src2) {
35; CHECK-LABEL: zext_02:
36; CHECK:       @ %bb.0: @ %entry
37; CHECK-NEXT:    vmullb.u32 q2, q0, q1
38; CHECK-NEXT:    vmov q0, q2
39; CHECK-NEXT:    bx lr
40entry:
41  %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
42  %out1 = zext <2 x i32> %shuf1 to <2 x i64>
43  %shuf2 = shufflevector <4 x i32> %src2, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
44  %out2 = zext <2 x i32> %shuf2 to <2 x i64>
45  %out = mul <2 x i64> %out1, %out2
46  ret <2 x i64> %out
47}
48
49define arm_aapcs_vfpcc <2 x i64> @zext_13(<4 x i32> %src1, <4 x i32> %src2) {
50; CHECK-LABEL: zext_13:
51; CHECK:       @ %bb.0: @ %entry
52; CHECK-NEXT:    vmullt.u32 q2, q0, q1
53; CHECK-NEXT:    vmov q0, q2
54; CHECK-NEXT:    bx lr
55entry:
56  %shuf1 = shufflevector <4 x i32> %src1, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
57  %out1 = zext <2 x i32> %shuf1 to <2 x i64>
58  %shuf2 = shufflevector <4 x i32> %src2, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
59  %out2 = zext <2 x i32> %shuf2 to <2 x i64>
60  %out = mul <2 x i64> %out1, %out2
61  ret <2 x i64> %out
62}
63
64
65define arm_aapcs_vfpcc <4 x i32> @sext_0246(<8 x i16> %src1, <8 x i16> %src2) {
66; CHECK-LABEL: sext_0246:
67; CHECK:       @ %bb.0: @ %entry
68; CHECK-NEXT:    vmullb.s16 q0, q0, q1
69; CHECK-NEXT:    bx lr
70entry:
71  %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
72  %out1 = sext <4 x i16> %shuf1 to <4 x i32>
73  %shuf2 = shufflevector <8 x i16> %src2, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
74  %out2 = sext <4 x i16> %shuf2 to <4 x i32>
75  %out = mul <4 x i32> %out1, %out2
76  ret <4 x i32> %out
77}
78
79define arm_aapcs_vfpcc <4 x i32> @sext_1357(<8 x i16> %src1, <8 x i16> %src2) {
80; CHECK-LABEL: sext_1357:
81; CHECK:       @ %bb.0: @ %entry
82; CHECK-NEXT:    vmullt.s16 q0, q0, q1
83; CHECK-NEXT:    bx lr
84entry:
85  %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
86  %out1 = sext <4 x i16> %shuf1 to <4 x i32>
87  %shuf2 = shufflevector <8 x i16> %src2, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
88  %out2 = sext <4 x i16> %shuf2 to <4 x i32>
89  %out = mul <4 x i32> %out1, %out2
90  ret <4 x i32> %out
91}
92
93define arm_aapcs_vfpcc <4 x i32> @zext_0246(<8 x i16> %src1, <8 x i16> %src2) {
94; CHECK-LABEL: zext_0246:
95; CHECK:       @ %bb.0: @ %entry
96; CHECK-NEXT:    vmullb.u16 q0, q0, q1
97; CHECK-NEXT:    bx lr
98entry:
99  %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
100  %out1 = zext <4 x i16> %shuf1 to <4 x i32>
101  %shuf2 = shufflevector <8 x i16> %src2, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
102  %out2 = zext <4 x i16> %shuf2 to <4 x i32>
103  %out = mul <4 x i32> %out1, %out2
104  ret <4 x i32> %out
105}
106
107define arm_aapcs_vfpcc <4 x i32> @zext_1357(<8 x i16> %src1, <8 x i16> %src2) {
108; CHECK-LABEL: zext_1357:
109; CHECK:       @ %bb.0: @ %entry
110; CHECK-NEXT:    vmullt.u16 q0, q0, q1
111; CHECK-NEXT:    bx lr
112entry:
113  %shuf1 = shufflevector <8 x i16> %src1, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
114  %out1 = zext <4 x i16> %shuf1 to <4 x i32>
115  %shuf2 = shufflevector <8 x i16> %src2, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
116  %out2 = zext <4 x i16> %shuf2 to <4 x i32>
117  %out = mul <4 x i32> %out1, %out2
118  ret <4 x i32> %out
119}
120
121define arm_aapcs_vfpcc <8 x i16> @sext_02468101214(<16 x i8> %src1, <16 x i8> %src2) {
122; CHECK-LABEL: sext_02468101214:
123; CHECK:       @ %bb.0: @ %entry
124; CHECK-NEXT:    vmullb.s8 q0, q0, q1
125; CHECK-NEXT:    bx lr
126entry:
127  %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
128  %out1 = sext <8 x i8> %shuf1 to <8 x i16>
129  %shuf2 = shufflevector <16 x i8> %src2, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
130  %out2 = sext <8 x i8> %shuf2 to <8 x i16>
131  %out = mul <8 x i16> %out1, %out2
132  ret <8 x i16> %out
133}
134
135define arm_aapcs_vfpcc <8 x i16> @sext_13579111315(<16 x i8> %src1, <16 x i8> %src2) {
136; CHECK-LABEL: sext_13579111315:
137; CHECK:       @ %bb.0: @ %entry
138; CHECK-NEXT:    vmullt.s8 q0, q0, q1
139; CHECK-NEXT:    bx lr
140entry:
141  %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
142  %out1 = sext <8 x i8> %shuf1 to <8 x i16>
143  %shuf2 = shufflevector <16 x i8> %src2, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
144  %out2 = sext <8 x i8> %shuf2 to <8 x i16>
145  %out = mul <8 x i16> %out1, %out2
146  ret <8 x i16> %out
147}
148
149define arm_aapcs_vfpcc <8 x i16> @zext_02468101214(<16 x i8> %src1, <16 x i8> %src2) {
150; CHECK-LABEL: zext_02468101214:
151; CHECK:       @ %bb.0: @ %entry
152; CHECK-NEXT:    vmullb.u8 q0, q0, q1
153; CHECK-NEXT:    bx lr
154entry:
155  %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
156  %out1 = zext <8 x i8> %shuf1 to <8 x i16>
157  %shuf2 = shufflevector <16 x i8> %src2, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
158  %out2 = zext <8 x i8> %shuf2 to <8 x i16>
159  %out = mul <8 x i16> %out1, %out2
160  ret <8 x i16> %out
161}
162
163define arm_aapcs_vfpcc <8 x i16> @zext_13579111315(<16 x i8> %src1, <16 x i8> %src2) {
164; CHECK-LABEL: zext_13579111315:
165; CHECK:       @ %bb.0: @ %entry
166; CHECK-NEXT:    vmullt.u8 q0, q0, q1
167; CHECK-NEXT:    bx lr
168entry:
169  %shuf1 = shufflevector <16 x i8> %src1, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
170  %out1 = zext <8 x i8> %shuf1 to <8 x i16>
171  %shuf2 = shufflevector <16 x i8> %src2, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
172  %out2 = zext <8 x i8> %shuf2 to <8 x i16>
173  %out = mul <8 x i16> %out1, %out2
174  ret <8 x i16> %out
175}
176