xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll (revision 637aa61732c5bda7cbcf94e5f08fb3a44655cef0) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKLE
3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKLE
4; RUN: llc -mtriple=thumbebv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKBE
5
6define arm_aapcs_vfpcc <16 x i8> @mov_int8_1() {
7; CHECK-LABEL: mov_int8_1:
8; CHECK:       @ %bb.0: @ %entry
9; CHECK-NEXT:    vmov.i8 q0, #0x1
10; CHECK-NEXT:    bx lr
11entry:
12  ret <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
13}
14
15define arm_aapcs_vfpcc <16 x i8> @xor_int8_1(<16 x i8> %a) {
16; CHECKLE-LABEL: xor_int8_1:
17; CHECKLE:       @ %bb.0: @ %entry
18; CHECKLE-NEXT:    vmov.i8 q1, #0x1
19; CHECKLE-NEXT:    veor q0, q0, q1
20; CHECKLE-NEXT:    bx lr
21;
22; CHECKBE-LABEL: xor_int8_1:
23; CHECKBE:       @ %bb.0: @ %entry
24; CHECKBE-NEXT:    vmov.i8 q1, #0x1
25; CHECKBE-NEXT:    vrev64.8 q2, q0
26; CHECKBE-NEXT:    veor q1, q2, q1
27; CHECKBE-NEXT:    vrev64.8 q0, q1
28; CHECKBE-NEXT:    bx lr
29entry:
30  %b = xor <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
31  ret <16 x i8> %b
32}
33
34define arm_aapcs_vfpcc <16 x i8> @mov_int8_m1() {
35; CHECK-LABEL: mov_int8_m1:
36; CHECK:       @ %bb.0: @ %entry
37; CHECK-NEXT:    vmov.i8 q0, #0xff
38; CHECK-NEXT:    bx lr
39entry:
40  ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
41}
42
43define arm_aapcs_vfpcc <16 x i8> @xor_int8_m1(<16 x i8> %a) {
44; CHECKLE-LABEL: xor_int8_m1:
45; CHECKLE:       @ %bb.0: @ %entry
46; CHECKLE-NEXT:    vmvn q0, q0
47; CHECKLE-NEXT:    bx lr
48;
49; CHECKBE-LABEL: xor_int8_m1:
50; CHECKBE:       @ %bb.0: @ %entry
51; CHECKBE-NEXT:    vrev64.8 q1, q0
52; CHECKBE-NEXT:    vmvn q1, q1
53; CHECKBE-NEXT:    vrev64.8 q0, q1
54; CHECKBE-NEXT:    bx lr
55entry:
56  %b = xor <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
57  ret <16 x i8> %b
58}
59
60; This has 0x01020304 or 0x04030201 vdup.32'd to q reg depending on endianness.
61; The big endian is different as there is an implicit vrev64.8 out of the
62; function, which gets constant folded away.
63define arm_aapcs_vfpcc <16 x i8> @mov_int8_1234() {
64; CHECKLE-LABEL: mov_int8_1234:
65; CHECKLE:       @ %bb.0: @ %entry
66; CHECKLE-NEXT:    movw r0, #513
67; CHECKLE-NEXT:    movt r0, #1027
68; CHECKLE-NEXT:    vdup.32 q0, r0
69; CHECKLE-NEXT:    bx lr
70;
71; CHECKBE-LABEL: mov_int8_1234:
72; CHECKBE:       @ %bb.0: @ %entry
73; CHECKBE-NEXT:    movw r0, #772
74; CHECKBE-NEXT:    movt r0, #258
75; CHECKBE-NEXT:    vdup.32 q0, r0
76; CHECKBE-NEXT:    bx lr
77entry:
78  ret <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>
79}
80
81define arm_aapcs_vfpcc <16 x i8> @xor_int8_1234(<16 x i8> %a) {
82; CHECKLE-LABEL: xor_int8_1234:
83; CHECKLE:       @ %bb.0: @ %entry
84; CHECKLE-NEXT:    movw r0, #513
85; CHECKLE-NEXT:    movt r0, #1027
86; CHECKLE-NEXT:    vdup.32 q1, r0
87; CHECKLE-NEXT:    veor q0, q0, q1
88; CHECKLE-NEXT:    bx lr
89;
90; CHECKBE-LABEL: xor_int8_1234:
91; CHECKBE:       @ %bb.0: @ %entry
92; CHECKBE-NEXT:    movw r0, #513
93; CHECKBE-NEXT:    vrev64.8 q1, q0
94; CHECKBE-NEXT:    movt r0, #1027
95; CHECKBE-NEXT:    vdup.32 q0, r0
96; CHECKBE-NEXT:    veor q1, q1, q0
97; CHECKBE-NEXT:    vrev64.8 q0, q1
98; CHECKBE-NEXT:    bx lr
99entry:
100  %b = xor <16 x i8> %a, <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>
101  ret <16 x i8> %b
102}
103
104define arm_aapcs_vfpcc <16 x i8> @mov_int8_32() {
105; CHECKLE-LABEL: mov_int8_32:
106; CHECKLE:       @ %bb.0: @ %entry
107; CHECKLE-NEXT:    vmov.i32 q0, #0x1
108; CHECKLE-NEXT:    bx lr
109;
110; CHECKBE-LABEL: mov_int8_32:
111; CHECKBE:       @ %bb.0: @ %entry
112; CHECKBE-NEXT:    vmov.i32 q0, #0x1000000
113; CHECKBE-NEXT:    bx lr
114entry:
115  ret <16 x i8> <i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0>
116}
117
118define arm_aapcs_vfpcc <16 x i8> @xor_int8_32(<16 x i8> %a) {
119; CHECKLE-LABEL: xor_int8_32:
120; CHECKLE:       @ %bb.0: @ %entry
121; CHECKLE-NEXT:    vmov.i32 q1, #0x1
122; CHECKLE-NEXT:    veor q0, q0, q1
123; CHECKLE-NEXT:    bx lr
124;
125; CHECKBE-LABEL: xor_int8_32:
126; CHECKBE:       @ %bb.0: @ %entry
127; CHECKBE-NEXT:    vmov.i32 q1, #0x1
128; CHECKBE-NEXT:    vrev64.8 q2, q0
129; CHECKBE-NEXT:    veor q1, q2, q1
130; CHECKBE-NEXT:    vrev64.8 q0, q1
131; CHECKBE-NEXT:    bx lr
132entry:
133  %b = xor <16 x i8> %a, <i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0>
134  ret <16 x i8> %b
135}
136
137define arm_aapcs_vfpcc <16 x i8> @mov_int8_64() {
138; CHECKLE-LABEL: mov_int8_64:
139; CHECKLE:       @ %bb.0: @ %entry
140; CHECKLE-NEXT:    vmov.i64 q0, #0xffff00ffff0000ff
141; CHECKLE-NEXT:    bx lr
142;
143; CHECKBE-LABEL: mov_int8_64:
144; CHECKBE:       @ %bb.0: @ %entry
145; CHECKBE-NEXT:    vmov.i64 q0, #0xff0000ffff00ffff
146; CHECKBE-NEXT:    bx lr
147entry:
148  ret <16 x i8> <i8 255, i8 0, i8 0, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 0, i8 255, i8 255, i8 0, i8 255, i8 255>
149}
150
151define arm_aapcs_vfpcc <16 x i8> @xor_int8_64(<16 x i8> %a) {
152; CHECKLE-LABEL: xor_int8_64:
153; CHECKLE:       @ %bb.0: @ %entry
154; CHECKLE-NEXT:    vmov.i64 q1, #0xffff00ffff0000ff
155; CHECKLE-NEXT:    veor q0, q0, q1
156; CHECKLE-NEXT:    bx lr
157;
158; CHECKBE-LABEL: xor_int8_64:
159; CHECKBE:       @ %bb.0: @ %entry
160; CHECKBE-NEXT:    vmov.i64 q1, #0xffff00ffff0000ff
161; CHECKBE-NEXT:    vrev64.8 q2, q0
162; CHECKBE-NEXT:    veor q1, q2, q1
163; CHECKBE-NEXT:    vrev64.8 q0, q1
164; CHECKBE-NEXT:    bx lr
165entry:
166  %b = xor <16 x i8> %a, <i8 255, i8 0, i8 0, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 0, i8 255, i8 255, i8 0, i8 255, i8 255>
167  ret <16 x i8> %b
168}
169
170define arm_aapcs_vfpcc <8 x i16> @mov_int16_1() {
171; CHECK-LABEL: mov_int16_1:
172; CHECK:       @ %bb.0: @ %entry
173; CHECK-NEXT:    vmov.i16 q0, #0x1
174; CHECK-NEXT:    bx lr
175entry:
176  ret <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
177}
178
179define arm_aapcs_vfpcc <8 x i16> @xor_int16_1(<8 x i16> %a) {
180; CHECKLE-LABEL: xor_int16_1:
181; CHECKLE:       @ %bb.0: @ %entry
182; CHECKLE-NEXT:    vmov.i16 q1, #0x1
183; CHECKLE-NEXT:    veor q0, q0, q1
184; CHECKLE-NEXT:    bx lr
185;
186; CHECKBE-LABEL: xor_int16_1:
187; CHECKBE:       @ %bb.0: @ %entry
188; CHECKBE-NEXT:    vmov.i16 q1, #0x1
189; CHECKBE-NEXT:    vrev64.16 q2, q0
190; CHECKBE-NEXT:    veor q1, q2, q1
191; CHECKBE-NEXT:    vrev64.16 q0, q1
192; CHECKBE-NEXT:    bx lr
193entry:
194  %b = xor <8 x i16> %a, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
195  ret <8 x i16> %b
196}
197
198define arm_aapcs_vfpcc <8 x i16> @mov_int16_m1() {
199; CHECK-LABEL: mov_int16_m1:
200; CHECK:       @ %bb.0: @ %entry
201; CHECK-NEXT:    vmov.i8 q0, #0xff
202; CHECK-NEXT:    bx lr
203entry:
204  ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
205}
206
207define arm_aapcs_vfpcc <8 x i16> @xor_int16_m1(<8 x i16> %a) {
208; CHECKLE-LABEL: xor_int16_m1:
209; CHECKLE:       @ %bb.0: @ %entry
210; CHECKLE-NEXT:    vmvn q0, q0
211; CHECKLE-NEXT:    bx lr
212;
213; CHECKBE-LABEL: xor_int16_m1:
214; CHECKBE:       @ %bb.0: @ %entry
215; CHECKBE-NEXT:    vmov.i8 q1, #0xff
216; CHECKBE-NEXT:    vrev64.16 q2, q0
217; CHECKBE-NEXT:    veor q1, q2, q1
218; CHECKBE-NEXT:    vrev64.16 q0, q1
219; CHECKBE-NEXT:    bx lr
220entry:
221  %b = xor <8 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
222  ret <8 x i16> %b
223}
224
225define arm_aapcs_vfpcc <8 x i16> @mov_int16_256() {
226; CHECK-LABEL: mov_int16_256:
227; CHECK:       @ %bb.0: @ %entry
228; CHECK-NEXT:    vmov.i16 q0, #0x100
229; CHECK-NEXT:    bx lr
230entry:
231  ret <8 x i16> <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
232}
233
234define arm_aapcs_vfpcc <8 x i16> @xor_int16_256(<8 x i16> %a) {
235; CHECKLE-LABEL: xor_int16_256:
236; CHECKLE:       @ %bb.0: @ %entry
237; CHECKLE-NEXT:    vmov.i16 q1, #0x100
238; CHECKLE-NEXT:    veor q0, q0, q1
239; CHECKLE-NEXT:    bx lr
240;
241; CHECKBE-LABEL: xor_int16_256:
242; CHECKBE:       @ %bb.0: @ %entry
243; CHECKBE-NEXT:    vmov.i16 q1, #0x100
244; CHECKBE-NEXT:    vrev64.16 q2, q0
245; CHECKBE-NEXT:    veor q1, q2, q1
246; CHECKBE-NEXT:    vrev64.16 q0, q1
247; CHECKBE-NEXT:    bx lr
248entry:
249  %b = xor <8 x i16> %a, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
250  ret <8 x i16> %b
251}
252
253define arm_aapcs_vfpcc <8 x i16> @mov_int16_257() {
254; CHECK-LABEL: mov_int16_257:
255; CHECK:       @ %bb.0: @ %entry
256; CHECK-NEXT:    vmov.i8 q0, #0x1
257; CHECK-NEXT:    bx lr
258entry:
259  ret <8 x i16> <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>
260}
261
262define arm_aapcs_vfpcc <8 x i16> @xor_int16_257(<8 x i16> %a) {
263; CHECKLE-LABEL: xor_int16_257:
264; CHECKLE:       @ %bb.0: @ %entry
265; CHECKLE-NEXT:    vmov.i8 q1, #0x1
266; CHECKLE-NEXT:    veor q0, q0, q1
267; CHECKLE-NEXT:    bx lr
268;
269; CHECKBE-LABEL: xor_int16_257:
270; CHECKBE:       @ %bb.0: @ %entry
271; CHECKBE-NEXT:    vmov.i8 q1, #0x1
272; CHECKBE-NEXT:    vrev64.16 q2, q0
273; CHECKBE-NEXT:    veor q1, q2, q1
274; CHECKBE-NEXT:    vrev64.16 q0, q1
275; CHECKBE-NEXT:    bx lr
276entry:
277  %b = xor <8 x i16> %a, <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>
278  ret <8 x i16> %b
279}
280
281define arm_aapcs_vfpcc <8 x i16> @mov_int16_258() {
282; CHECK-LABEL: mov_int16_258:
283; CHECK:       @ %bb.0: @ %entry
284; CHECK-NEXT:    mov.w r0, #258
285; CHECK-NEXT:    vdup.16 q0, r0
286; CHECK-NEXT:    bx lr
287entry:
288  ret <8 x i16> <i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258>
289}
290
291define arm_aapcs_vfpcc <8 x i16> @xor_int16_258(<8 x i16> %a) {
292; CHECKLE-LABEL: xor_int16_258:
293; CHECKLE:       @ %bb.0: @ %entry
294; CHECKLE-NEXT:    mov.w r0, #258
295; CHECKLE-NEXT:    vdup.16 q1, r0
296; CHECKLE-NEXT:    veor q0, q0, q1
297; CHECKLE-NEXT:    bx lr
298;
299; CHECKBE-LABEL: xor_int16_258:
300; CHECKBE:       @ %bb.0: @ %entry
301; CHECKBE-NEXT:    mov.w r0, #258
302; CHECKBE-NEXT:    vrev64.16 q2, q0
303; CHECKBE-NEXT:    vdup.16 q1, r0
304; CHECKBE-NEXT:    veor q1, q2, q1
305; CHECKBE-NEXT:    vrev64.16 q0, q1
306; CHECKBE-NEXT:    bx lr
307entry:
308  %b = xor <8 x i16> %a, <i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258>
309  ret <8 x i16> %b
310}
311
312define arm_aapcs_vfpcc <8 x i16> @mov_int16_32() {
313; CHECKLE-LABEL: mov_int16_32:
314; CHECKLE:       @ %bb.0: @ %entry
315; CHECKLE-NEXT:    movw r0, #257
316; CHECKLE-NEXT:    movt r0, #256
317; CHECKLE-NEXT:    vdup.32 q0, r0
318; CHECKLE-NEXT:    bx lr
319;
320; CHECKBE-LABEL: mov_int16_32:
321; CHECKBE:       @ %bb.0: @ %entry
322; CHECKBE-NEXT:    movw r0, #256
323; CHECKBE-NEXT:    movt r0, #257
324; CHECKBE-NEXT:    vdup.32 q0, r0
325; CHECKBE-NEXT:    bx lr
326entry:
327  ret <8 x i16> <i16 257, i16 256, i16 257, i16 256, i16 257, i16 256, i16 257, i16 256>
328}
329
330define arm_aapcs_vfpcc <8 x i16> @xor_int16_32(<8 x i16> %a) {
331; CHECKLE-LABEL: xor_int16_32:
332; CHECKLE:       @ %bb.0: @ %entry
333; CHECKLE-NEXT:    movw r0, #257
334; CHECKLE-NEXT:    movt r0, #256
335; CHECKLE-NEXT:    vdup.32 q1, r0
336; CHECKLE-NEXT:    veor q0, q0, q1
337; CHECKLE-NEXT:    bx lr
338;
339; CHECKBE-LABEL: xor_int16_32:
340; CHECKBE:       @ %bb.0: @ %entry
341; CHECKBE-NEXT:    movw r0, #257
342; CHECKBE-NEXT:    vrev64.16 q1, q0
343; CHECKBE-NEXT:    movt r0, #256
344; CHECKBE-NEXT:    vdup.32 q0, r0
345; CHECKBE-NEXT:    veor q1, q1, q0
346; CHECKBE-NEXT:    vrev64.16 q0, q1
347; CHECKBE-NEXT:    bx lr
348entry:
349  %b = xor <8 x i16> %a, <i16 257, i16 256, i16 257, i16 256, i16 257, i16 256, i16 257, i16 256>
350  ret <8 x i16> %b
351}
352
353define arm_aapcs_vfpcc <8 x i16> @mov_int16_64() {
354; CHECK-LABEL: mov_int16_64:
355; CHECK:       @ %bb.0: @ %entry
356; CHECK-NEXT:    vmov.i64 q0, #0xff0000000000ff
357; CHECK-NEXT:    bx lr
358entry:
359  ret <8 x i16> <i16 255, i16 0, i16 0, i16 255, i16 255, i16 0, i16 0, i16 255>
360}
361
362define arm_aapcs_vfpcc <8 x i16> @xor_int16_64(<8 x i16> %a) {
363; CHECKLE-LABEL: xor_int16_64:
364; CHECKLE:       @ %bb.0: @ %entry
365; CHECKLE-NEXT:    vmov.i64 q1, #0xff0000000000ff
366; CHECKLE-NEXT:    veor q0, q0, q1
367; CHECKLE-NEXT:    bx lr
368;
369; CHECKBE-LABEL: xor_int16_64:
370; CHECKBE:       @ %bb.0: @ %entry
371; CHECKBE-NEXT:    vmov.i64 q1, #0xff0000000000ff
372; CHECKBE-NEXT:    vrev64.16 q2, q0
373; CHECKBE-NEXT:    veor q1, q2, q1
374; CHECKBE-NEXT:    vrev64.16 q0, q1
375; CHECKBE-NEXT:    bx lr
376entry:
377  %b = xor <8 x i16> %a, <i16 255, i16 0, i16 0, i16 255, i16 255, i16 0, i16 0, i16 255>
378  ret <8 x i16> %b
379}
380
381define arm_aapcs_vfpcc <4 x i32> @mov_int32_1() {
382; CHECK-LABEL: mov_int32_1:
383; CHECK:       @ %bb.0: @ %entry
384; CHECK-NEXT:    vmov.i32 q0, #0x1
385; CHECK-NEXT:    bx lr
386entry:
387  ret <4 x i32> <i32 1, i32 1, i32 1, i32 1>
388}
389
390define arm_aapcs_vfpcc <4 x i32> @xor_int32_1(<4 x i32> %a) {
391; CHECKLE-LABEL: xor_int32_1:
392; CHECKLE:       @ %bb.0: @ %entry
393; CHECKLE-NEXT:    vmov.i32 q1, #0x1
394; CHECKLE-NEXT:    veor q0, q0, q1
395; CHECKLE-NEXT:    bx lr
396;
397; CHECKBE-LABEL: xor_int32_1:
398; CHECKBE:       @ %bb.0: @ %entry
399; CHECKBE-NEXT:    vmov.i32 q1, #0x1
400; CHECKBE-NEXT:    vrev64.32 q2, q0
401; CHECKBE-NEXT:    veor q1, q2, q1
402; CHECKBE-NEXT:    vrev64.32 q0, q1
403; CHECKBE-NEXT:    bx lr
404entry:
405  %b = xor <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1>
406  ret <4 x i32> %b
407}
408
409define arm_aapcs_vfpcc <4 x i32> @mov_int32_256() {
410; CHECK-LABEL: mov_int32_256:
411; CHECK:       @ %bb.0: @ %entry
412; CHECK-NEXT:    vmov.i32 q0, #0x100
413; CHECK-NEXT:    bx lr
414entry:
415  ret <4 x i32> <i32 256, i32 256, i32 256, i32 256>
416}
417
418define arm_aapcs_vfpcc <4 x i32> @xor_int32_256(<4 x i32> %a) {
419; CHECKLE-LABEL: xor_int32_256:
420; CHECKLE:       @ %bb.0: @ %entry
421; CHECKLE-NEXT:    vmov.i32 q1, #0x100
422; CHECKLE-NEXT:    veor q0, q0, q1
423; CHECKLE-NEXT:    bx lr
424;
425; CHECKBE-LABEL: xor_int32_256:
426; CHECKBE:       @ %bb.0: @ %entry
427; CHECKBE-NEXT:    vmov.i32 q1, #0x100
428; CHECKBE-NEXT:    vrev64.32 q2, q0
429; CHECKBE-NEXT:    veor q1, q2, q1
430; CHECKBE-NEXT:    vrev64.32 q0, q1
431; CHECKBE-NEXT:    bx lr
432entry:
433  %b = xor <4 x i32> %a, <i32 256, i32 256, i32 256, i32 256>
434  ret <4 x i32> %b
435}
436
437define arm_aapcs_vfpcc <4 x i32> @mov_int32_65536() {
438; CHECK-LABEL: mov_int32_65536:
439; CHECK:       @ %bb.0: @ %entry
440; CHECK-NEXT:    vmov.i32 q0, #0x10000
441; CHECK-NEXT:    bx lr
442entry:
443  ret <4 x i32> <i32 65536, i32 65536, i32 65536, i32 65536>
444}
445
446define arm_aapcs_vfpcc <4 x i32> @xor_int32_65536(<4 x i32> %a) {
447; CHECKLE-LABEL: xor_int32_65536:
448; CHECKLE:       @ %bb.0: @ %entry
449; CHECKLE-NEXT:    vmov.i32 q1, #0x10000
450; CHECKLE-NEXT:    veor q0, q0, q1
451; CHECKLE-NEXT:    bx lr
452;
453; CHECKBE-LABEL: xor_int32_65536:
454; CHECKBE:       @ %bb.0: @ %entry
455; CHECKBE-NEXT:    vmov.i32 q1, #0x10000
456; CHECKBE-NEXT:    vrev64.32 q2, q0
457; CHECKBE-NEXT:    veor q1, q2, q1
458; CHECKBE-NEXT:    vrev64.32 q0, q1
459; CHECKBE-NEXT:    bx lr
460entry:
461  %b = xor <4 x i32> %a, <i32 65536, i32 65536, i32 65536, i32 65536>
462  ret <4 x i32> %b
463}
464
465define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777216() {
466; CHECK-LABEL: mov_int32_16777216:
467; CHECK:       @ %bb.0: @ %entry
468; CHECK-NEXT:    vmov.i32 q0, #0x1000000
469; CHECK-NEXT:    bx lr
470entry:
471  ret <4 x i32> <i32 16777216, i32 16777216, i32 16777216, i32 16777216>
472}
473
474define arm_aapcs_vfpcc <4 x i32> @xor_int32_16777216(<4 x i32> %a) {
475; CHECKLE-LABEL: xor_int32_16777216:
476; CHECKLE:       @ %bb.0: @ %entry
477; CHECKLE-NEXT:    vmov.i32 q1, #0x1000000
478; CHECKLE-NEXT:    veor q0, q0, q1
479; CHECKLE-NEXT:    bx lr
480;
481; CHECKBE-LABEL: xor_int32_16777216:
482; CHECKBE:       @ %bb.0: @ %entry
483; CHECKBE-NEXT:    vmov.i32 q1, #0x1000000
484; CHECKBE-NEXT:    vrev64.32 q2, q0
485; CHECKBE-NEXT:    veor q1, q2, q1
486; CHECKBE-NEXT:    vrev64.32 q0, q1
487; CHECKBE-NEXT:    bx lr
488entry:
489  %b = xor <4 x i32> %a, <i32 16777216, i32 16777216, i32 16777216, i32 16777216>
490  ret <4 x i32> %b
491}
492
493define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777217() {
494; CHECK-LABEL: mov_int32_16777217:
495; CHECK:       @ %bb.0: @ %entry
496; CHECK-NEXT:    movs r0, #1
497; CHECK-NEXT:    movt r0, #256
498; CHECK-NEXT:    vdup.32 q0, r0
499; CHECK-NEXT:    bx lr
500entry:
501  ret <4 x i32> <i32 16777217, i32 16777217, i32 16777217, i32 16777217>
502}
503
504define arm_aapcs_vfpcc <4 x i32> @xor_int32_16777217(<4 x i32> %a) {
505; CHECKLE-LABEL: xor_int32_16777217:
506; CHECKLE:       @ %bb.0: @ %entry
507; CHECKLE-NEXT:    movs r0, #1
508; CHECKLE-NEXT:    movt r0, #256
509; CHECKLE-NEXT:    vdup.32 q1, r0
510; CHECKLE-NEXT:    veor q0, q0, q1
511; CHECKLE-NEXT:    bx lr
512;
513; CHECKBE-LABEL: xor_int32_16777217:
514; CHECKBE:       @ %bb.0: @ %entry
515; CHECKBE-NEXT:    movs r0, #1
516; CHECKBE-NEXT:    vrev64.32 q1, q0
517; CHECKBE-NEXT:    movt r0, #256
518; CHECKBE-NEXT:    vdup.32 q0, r0
519; CHECKBE-NEXT:    veor q1, q1, q0
520; CHECKBE-NEXT:    vrev64.32 q0, q1
521; CHECKBE-NEXT:    bx lr
522entry:
523  %b = xor <4 x i32> %a, <i32 16777217, i32 16777217, i32 16777217, i32 16777217>
524  ret <4 x i32> %b
525}
526
527define arm_aapcs_vfpcc <4 x i32> @mov_int32_17919() {
528; CHECK-LABEL: mov_int32_17919:
529; CHECK:       @ %bb.0: @ %entry
530; CHECK-NEXT:    vmov.i32 q0, #0x45ff
531; CHECK-NEXT:    bx lr
532entry:
533  ret <4 x i32> <i32 17919, i32 17919, i32 17919, i32 17919>
534}
535
536define arm_aapcs_vfpcc <4 x i32> @xor_int32_17919(<4 x i32> %a) {
537; CHECKLE-LABEL: xor_int32_17919:
538; CHECKLE:       @ %bb.0: @ %entry
539; CHECKLE-NEXT:    vmov.i32 q1, #0x45ff
540; CHECKLE-NEXT:    veor q0, q0, q1
541; CHECKLE-NEXT:    bx lr
542;
543; CHECKBE-LABEL: xor_int32_17919:
544; CHECKBE:       @ %bb.0: @ %entry
545; CHECKBE-NEXT:    vmov.i32 q1, #0x45ff
546; CHECKBE-NEXT:    vrev64.32 q2, q0
547; CHECKBE-NEXT:    veor q1, q2, q1
548; CHECKBE-NEXT:    vrev64.32 q0, q1
549; CHECKBE-NEXT:    bx lr
550entry:
551  %b = xor <4 x i32> %a, <i32 17919, i32 17919, i32 17919, i32 17919>
552  ret <4 x i32> %b
553}
554
555define arm_aapcs_vfpcc <4 x i32> @mov_int32_4587519() {
556; CHECK-LABEL: mov_int32_4587519:
557; CHECK:       @ %bb.0: @ %entry
558; CHECK-NEXT:    vmov.i32 q0, #0x45ffff
559; CHECK-NEXT:    bx lr
560entry:
561  ret <4 x i32> <i32 4587519, i32 4587519, i32 4587519, i32 4587519>
562}
563
564define arm_aapcs_vfpcc <4 x i32> @xor_int32_4587519(<4 x i32> %a) {
565; CHECKLE-LABEL: xor_int32_4587519:
566; CHECKLE:       @ %bb.0: @ %entry
567; CHECKLE-NEXT:    vmov.i32 q1, #0x45ffff
568; CHECKLE-NEXT:    veor q0, q0, q1
569; CHECKLE-NEXT:    bx lr
570;
571; CHECKBE-LABEL: xor_int32_4587519:
572; CHECKBE:       @ %bb.0: @ %entry
573; CHECKBE-NEXT:    vmov.i32 q1, #0x45ffff
574; CHECKBE-NEXT:    vrev64.32 q2, q0
575; CHECKBE-NEXT:    veor q1, q2, q1
576; CHECKBE-NEXT:    vrev64.32 q0, q1
577; CHECKBE-NEXT:    bx lr
578entry:
579  %b = xor <4 x i32> %a, <i32 4587519, i32 4587519, i32 4587519, i32 4587519>
580  ret <4 x i32> %b
581}
582
583define arm_aapcs_vfpcc <4 x i32> @mov_int32_m1() {
584; CHECK-LABEL: mov_int32_m1:
585; CHECK:       @ %bb.0: @ %entry
586; CHECK-NEXT:    vmov.i8 q0, #0xff
587; CHECK-NEXT:    bx lr
588entry:
589  ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
590}
591
592define arm_aapcs_vfpcc <4 x i32> @xor_int32_m1(<4 x i32> %a) {
593; CHECKLE-LABEL: xor_int32_m1:
594; CHECKLE:       @ %bb.0: @ %entry
595; CHECKLE-NEXT:    vmvn q0, q0
596; CHECKLE-NEXT:    bx lr
597;
598; CHECKBE-LABEL: xor_int32_m1:
599; CHECKBE:       @ %bb.0: @ %entry
600; CHECKBE-NEXT:    vmov.i8 q1, #0xff
601; CHECKBE-NEXT:    vrev64.32 q2, q0
602; CHECKBE-NEXT:    veor q1, q2, q1
603; CHECKBE-NEXT:    vrev64.32 q0, q1
604; CHECKBE-NEXT:    bx lr
605entry:
606  %b = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
607  ret <4 x i32> %b
608}
609
610define arm_aapcs_vfpcc <4 x i32> @mov_int32_4294901760() {
611; CHECK-LABEL: mov_int32_4294901760:
612; CHECK:       @ %bb.0: @ %entry
613; CHECK-NEXT:    vmvn.i32 q0, #0xffff
614; CHECK-NEXT:    bx lr
615entry:
616  ret <4 x i32> <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
617}
618
619define arm_aapcs_vfpcc <4 x i32> @xor_int32_4294901760(<4 x i32> %a) {
620; CHECKLE-LABEL: xor_int32_4294901760:
621; CHECKLE:       @ %bb.0: @ %entry
622; CHECKLE-NEXT:    vmvn.i32 q1, #0xffff
623; CHECKLE-NEXT:    veor q0, q0, q1
624; CHECKLE-NEXT:    bx lr
625;
626; CHECKBE-LABEL: xor_int32_4294901760:
627; CHECKBE:       @ %bb.0: @ %entry
628; CHECKBE-NEXT:    vmvn.i32 q1, #0xffff
629; CHECKBE-NEXT:    vrev64.32 q2, q0
630; CHECKBE-NEXT:    veor q1, q2, q1
631; CHECKBE-NEXT:    vrev64.32 q0, q1
632; CHECKBE-NEXT:    bx lr
633entry:
634  %b = xor <4 x i32> %a, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
635  ret <4 x i32> %b
636}
637
638define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278190335() {
639; CHECK-LABEL: mov_int32_4278190335:
640; CHECK:       @ %bb.0: @ %entry
641; CHECK-NEXT:    movs r0, #255
642; CHECK-NEXT:    movt r0, #65280
643; CHECK-NEXT:    vdup.32 q0, r0
644; CHECK-NEXT:    bx lr
645entry:
646  ret <4 x i32> <i32 4278190335, i32 4278190335, i32 4278190335, i32 4278190335>
647}
648
649define arm_aapcs_vfpcc <4 x i32> @xor_int32_4278190335(<4 x i32> %a) {
650; CHECKLE-LABEL: xor_int32_4278190335:
651; CHECKLE:       @ %bb.0: @ %entry
652; CHECKLE-NEXT:    movs r0, #255
653; CHECKLE-NEXT:    movt r0, #65280
654; CHECKLE-NEXT:    vdup.32 q1, r0
655; CHECKLE-NEXT:    veor q0, q0, q1
656; CHECKLE-NEXT:    bx lr
657;
658; CHECKBE-LABEL: xor_int32_4278190335:
659; CHECKBE:       @ %bb.0: @ %entry
660; CHECKBE-NEXT:    movs r0, #255
661; CHECKBE-NEXT:    vrev64.32 q1, q0
662; CHECKBE-NEXT:    movt r0, #65280
663; CHECKBE-NEXT:    vdup.32 q0, r0
664; CHECKBE-NEXT:    veor q1, q1, q0
665; CHECKBE-NEXT:    vrev64.32 q0, q1
666; CHECKBE-NEXT:    bx lr
667entry:
668  %b = xor <4 x i32> %a, <i32 4278190335, i32 4278190335, i32 4278190335, i32 4278190335>
669  ret <4 x i32> %b
670}
671
672define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278255615() {
673; CHECK-LABEL: mov_int32_4278255615:
674; CHECK:       @ %bb.0: @ %entry
675; CHECK-NEXT:    vmvn.i32 q0, #0xff0000
676; CHECK-NEXT:    bx lr
677entry:
678  ret <4 x i32> <i32 4278255615, i32 4278255615, i32 4278255615, i32 4278255615>
679}
680
681define arm_aapcs_vfpcc <4 x i32> @xor_int32_4278255615(<4 x i32> %a) {
682; CHECKLE-LABEL: xor_int32_4278255615:
683; CHECKLE:       @ %bb.0: @ %entry
684; CHECKLE-NEXT:    vmvn.i32 q1, #0xff0000
685; CHECKLE-NEXT:    veor q0, q0, q1
686; CHECKLE-NEXT:    bx lr
687;
688; CHECKBE-LABEL: xor_int32_4278255615:
689; CHECKBE:       @ %bb.0: @ %entry
690; CHECKBE-NEXT:    vmvn.i32 q1, #0xff0000
691; CHECKBE-NEXT:    vrev64.32 q2, q0
692; CHECKBE-NEXT:    veor q1, q2, q1
693; CHECKBE-NEXT:    vrev64.32 q0, q1
694; CHECKBE-NEXT:    bx lr
695entry:
696  %b = xor <4 x i32> %a, <i32 4278255615, i32 4278255615, i32 4278255615, i32 4278255615>
697  ret <4 x i32> %b
698}
699
700define arm_aapcs_vfpcc <4 x i32> @mov_int32_16908546() {
701; CHECK-LABEL: mov_int32_16908546:
702; CHECK:       @ %bb.0: @ %entry
703; CHECK-NEXT:    mov.w r0, #258
704; CHECK-NEXT:    vdup.16 q0, r0
705; CHECK-NEXT:    bx lr
706entry:
707  ret <4 x i32> <i32 16908546, i32 16908546, i32 16908546, i32 16908546>
708}
709
710define arm_aapcs_vfpcc <4 x i32> @xor_int32_16908546(<4 x i32> %a) {
711; CHECKLE-LABEL: xor_int32_16908546:
712; CHECKLE:       @ %bb.0: @ %entry
713; CHECKLE-NEXT:    mov.w r0, #258
714; CHECKLE-NEXT:    vdup.16 q1, r0
715; CHECKLE-NEXT:    veor q0, q0, q1
716; CHECKLE-NEXT:    bx lr
717;
718; CHECKBE-LABEL: xor_int32_16908546:
719; CHECKBE:       @ %bb.0: @ %entry
720; CHECKBE-NEXT:    mov.w r0, #258
721; CHECKBE-NEXT:    vrev64.32 q2, q0
722; CHECKBE-NEXT:    vdup.16 q1, r0
723; CHECKBE-NEXT:    veor q1, q2, q1
724; CHECKBE-NEXT:    vrev64.32 q0, q1
725; CHECKBE-NEXT:    bx lr
726entry:
727  %b = xor <4 x i32> %a, <i32 16908546, i32 16908546, i32 16908546, i32 16908546>
728  ret <4 x i32> %b
729}
730
731define arm_aapcs_vfpcc <4 x i32> @mov_int32_64() {
732; CHECKLE-LABEL: mov_int32_64:
733; CHECKLE:       @ %bb.0: @ %entry
734; CHECKLE-NEXT:    vmov.i64 q0, #0xff00ffff00ff00
735; CHECKLE-NEXT:    bx lr
736;
737; CHECKBE-LABEL: mov_int32_64:
738; CHECKBE:       @ %bb.0: @ %entry
739; CHECKBE-NEXT:    vmov.i64 q0, #0xff00ff0000ff00ff
740; CHECKBE-NEXT:    bx lr
741entry:
742  ret <4 x i32> <i32 u0xff00ff00, i32 u0x00ff00ff, i32 u0xff00ff00, i32 u0x00ff00ff>
743}
744
745define arm_aapcs_vfpcc <4 x i32> @xor_int32_64(<4 x i32> %a) {
746; CHECKLE-LABEL: xor_int32_64:
747; CHECKLE:       @ %bb.0: @ %entry
748; CHECKLE-NEXT:    vmov.i64 q1, #0xff00ffff00ff00
749; CHECKLE-NEXT:    veor q0, q0, q1
750; CHECKLE-NEXT:    bx lr
751;
752; CHECKBE-LABEL: xor_int32_64:
753; CHECKBE:       @ %bb.0: @ %entry
754; CHECKBE-NEXT:    vmov.i64 q1, #0xff00ffff00ff00
755; CHECKBE-NEXT:    vrev64.32 q2, q0
756; CHECKBE-NEXT:    veor q1, q2, q1
757; CHECKBE-NEXT:    vrev64.32 q0, q1
758; CHECKBE-NEXT:    bx lr
759entry:
760  %b = xor <4 x i32> %a, <i32 u0xff00ff00, i32 u0x00ff00ff, i32 u0xff00ff00, i32 u0x00ff00ff>
761  ret <4 x i32> %b
762}
763
764define arm_aapcs_vfpcc <2 x i64> @mov_int64_1() {
765; CHECKLE-LABEL: mov_int64_1:
766; CHECKLE:       @ %bb.0: @ %entry
767; CHECKLE-NEXT:    adr r0, .LCPI50_0
768; CHECKLE-NEXT:    vldrw.u32 q0, [r0]
769; CHECKLE-NEXT:    bx lr
770; CHECKLE-NEXT:    .p2align 4
771; CHECKLE-NEXT:  @ %bb.1:
772; CHECKLE-NEXT:  .LCPI50_0:
773; CHECKLE-NEXT:    .long 1 @ double 4.9406564584124654E-324
774; CHECKLE-NEXT:    .long 0
775; CHECKLE-NEXT:    .long 1 @ double 4.9406564584124654E-324
776; CHECKLE-NEXT:    .long 0
777;
778; CHECKBE-LABEL: mov_int64_1:
779; CHECKBE:       @ %bb.0: @ %entry
780; CHECKBE-NEXT:    adr r0, .LCPI50_0
781; CHECKBE-NEXT:    vldrb.u8 q1, [r0]
782; CHECKBE-NEXT:    vrev64.8 q0, q1
783; CHECKBE-NEXT:    bx lr
784; CHECKBE-NEXT:    .p2align 4
785; CHECKBE-NEXT:  @ %bb.1:
786; CHECKBE-NEXT:  .LCPI50_0:
787; CHECKBE-NEXT:    .long 0 @ double 4.9406564584124654E-324
788; CHECKBE-NEXT:    .long 1
789; CHECKBE-NEXT:    .long 0 @ double 4.9406564584124654E-324
790; CHECKBE-NEXT:    .long 1
791entry:
792  ret <2 x i64> <i64 1, i64 1>
793}
794
795define arm_aapcs_vfpcc <2 x i64> @xor_int64_1(<2 x i64> %a) {
796; CHECKLE-LABEL: xor_int64_1:
797; CHECKLE:       @ %bb.0: @ %entry
798; CHECKLE-NEXT:    adr r0, .LCPI51_0
799; CHECKLE-NEXT:    vldrw.u32 q1, [r0]
800; CHECKLE-NEXT:    veor q0, q0, q1
801; CHECKLE-NEXT:    bx lr
802; CHECKLE-NEXT:    .p2align 4
803; CHECKLE-NEXT:  @ %bb.1:
804; CHECKLE-NEXT:  .LCPI51_0:
805; CHECKLE-NEXT:    .long 1 @ 0x1
806; CHECKLE-NEXT:    .long 0 @ 0x0
807; CHECKLE-NEXT:    .long 1 @ 0x1
808; CHECKLE-NEXT:    .long 0 @ 0x0
809;
810; CHECKBE-LABEL: xor_int64_1:
811; CHECKBE:       @ %bb.0: @ %entry
812; CHECKBE-NEXT:    adr r0, .LCPI51_0
813; CHECKBE-NEXT:    vldrb.u8 q1, [r0]
814; CHECKBE-NEXT:    vrev64.8 q2, q1
815; CHECKBE-NEXT:    veor q0, q0, q2
816; CHECKBE-NEXT:    bx lr
817; CHECKBE-NEXT:    .p2align 4
818; CHECKBE-NEXT:  @ %bb.1:
819; CHECKBE-NEXT:  .LCPI51_0:
820; CHECKBE-NEXT:    .long 0 @ 0x0
821; CHECKBE-NEXT:    .long 1 @ 0x1
822; CHECKBE-NEXT:    .long 0 @ 0x0
823; CHECKBE-NEXT:    .long 1 @ 0x1
824entry:
825  %b = xor <2 x i64> %a, <i64 1, i64 1>
826  ret <2 x i64> %b
827}
828
829define arm_aapcs_vfpcc <2 x i64> @mov_int64_ff() {
830; CHECK-LABEL: mov_int64_ff:
831; CHECK:       @ %bb.0: @ %entry
832; CHECK-NEXT:    vmov.i64 q0, #0xff
833; CHECK-NEXT:    bx lr
834entry:
835  ret <2 x i64> <i64 255, i64 255>
836}
837
838define arm_aapcs_vfpcc <2 x i64> @xor_int64_ff(<2 x i64> %a) {
839; CHECKLE-LABEL: xor_int64_ff:
840; CHECKLE:       @ %bb.0: @ %entry
841; CHECKLE-NEXT:    vmov.i64 q1, #0xff
842; CHECKLE-NEXT:    veor q0, q0, q1
843; CHECKLE-NEXT:    bx lr
844;
845; CHECKBE-LABEL: xor_int64_ff:
846; CHECKBE:       @ %bb.0: @ %entry
847; CHECKBE-NEXT:    vmov.i64 q1, #0xff00000000
848; CHECKBE-NEXT:    vrev64.32 q2, q1
849; CHECKBE-NEXT:    veor q0, q0, q2
850; CHECKBE-NEXT:    bx lr
851entry:
852  %b = xor <2 x i64> %a, <i64 255, i64 255>
853  ret <2 x i64> %b
854}
855
856define arm_aapcs_vfpcc <2 x i64> @mov_int64_m1() {
857; CHECK-LABEL: mov_int64_m1:
858; CHECK:       @ %bb.0: @ %entry
859; CHECK-NEXT:    vmov.i8 q0, #0xff
860; CHECK-NEXT:    bx lr
861entry:
862  ret <2 x i64> <i64 -1, i64 -1>
863}
864
865define arm_aapcs_vfpcc <2 x i64> @xor_int64_m1(<2 x i64> %a) {
866; CHECKLE-LABEL: xor_int64_m1:
867; CHECKLE:       @ %bb.0: @ %entry
868; CHECKLE-NEXT:    vmvn q0, q0
869; CHECKLE-NEXT:    bx lr
870;
871; CHECKBE-LABEL: xor_int64_m1:
872; CHECKBE:       @ %bb.0: @ %entry
873; CHECKBE-NEXT:    vmov.i8 q1, #0xff
874; CHECKBE-NEXT:    veor q0, q0, q1
875; CHECKBE-NEXT:    bx lr
876entry:
877  %b = xor <2 x i64> %a, <i64 -1, i64 -1>
878  ret <2 x i64> %b
879}
880
881define arm_aapcs_vfpcc <2 x i64> @mov_int64_ff0000ff0000ffff() {
882; CHECK-LABEL: mov_int64_ff0000ff0000ffff:
883; CHECK:       @ %bb.0: @ %entry
884; CHECK-NEXT:    vmov.i64 q0, #0xff0000ff0000ffff
885; CHECK-NEXT:    bx lr
886entry:
887  ret <2 x i64> <i64 18374687574888349695, i64 18374687574888349695>
888}
889
890define arm_aapcs_vfpcc <2 x i64> @xor_int64_ff0000ff0000ffff(<2 x i64> %a) {
891; CHECKLE-LABEL: xor_int64_ff0000ff0000ffff:
892; CHECKLE:       @ %bb.0: @ %entry
893; CHECKLE-NEXT:    vmov.i64 q1, #0xff0000ff0000ffff
894; CHECKLE-NEXT:    veor q0, q0, q1
895; CHECKLE-NEXT:    bx lr
896;
897; CHECKBE-LABEL: xor_int64_ff0000ff0000ffff:
898; CHECKBE:       @ %bb.0: @ %entry
899; CHECKBE-NEXT:    vmov.i64 q1, #0xffffff0000ff
900; CHECKBE-NEXT:    vrev64.32 q2, q1
901; CHECKBE-NEXT:    veor q0, q0, q2
902; CHECKBE-NEXT:    bx lr
903entry:
904  %b = xor <2 x i64> %a, <i64 18374687574888349695, i64 18374687574888349695>
905  ret <2 x i64> %b
906}
907
908define arm_aapcs_vfpcc <2 x i64> @mov_int64_f_0() {
909; CHECKLE-LABEL: mov_int64_f_0:
910; CHECKLE:       @ %bb.0: @ %entry
911; CHECKLE-NEXT:    adr r0, .LCPI58_0
912; CHECKLE-NEXT:    vldrw.u32 q0, [r0]
913; CHECKLE-NEXT:    bx lr
914; CHECKLE-NEXT:    .p2align 4
915; CHECKLE-NEXT:  @ %bb.1:
916; CHECKLE-NEXT:  .LCPI58_0:
917; CHECKLE-NEXT:    .long 255 @ double 1.2598673968951787E-321
918; CHECKLE-NEXT:    .long 0
919; CHECKLE-NEXT:    .long 0 @ double 0
920; CHECKLE-NEXT:    .long 0
921;
922; CHECKBE-LABEL: mov_int64_f_0:
923; CHECKBE:       @ %bb.0: @ %entry
924; CHECKBE-NEXT:    adr r0, .LCPI58_0
925; CHECKBE-NEXT:    vldrb.u8 q1, [r0]
926; CHECKBE-NEXT:    vrev64.8 q0, q1
927; CHECKBE-NEXT:    bx lr
928; CHECKBE-NEXT:    .p2align 4
929; CHECKBE-NEXT:  @ %bb.1:
930; CHECKBE-NEXT:  .LCPI58_0:
931; CHECKBE-NEXT:    .long 0 @ double 1.2598673968951787E-321
932; CHECKBE-NEXT:    .long 255
933; CHECKBE-NEXT:    .long 0 @ double 0
934; CHECKBE-NEXT:    .long 0
935entry:
936  ret <2 x i64> <i64 255, i64 0>
937}
938
939define arm_aapcs_vfpcc <2 x i64> @xor_int64_f_0(<2 x i64> %a) {
940; CHECKLE-LABEL: xor_int64_f_0:
941; CHECKLE:       @ %bb.0: @ %entry
942; CHECKLE-NEXT:    adr r0, .LCPI59_0
943; CHECKLE-NEXT:    vldrw.u32 q1, [r0]
944; CHECKLE-NEXT:    veor q0, q0, q1
945; CHECKLE-NEXT:    bx lr
946; CHECKLE-NEXT:    .p2align 4
947; CHECKLE-NEXT:  @ %bb.1:
948; CHECKLE-NEXT:  .LCPI59_0:
949; CHECKLE-NEXT:    .long 255 @ 0xff
950; CHECKLE-NEXT:    .long 0 @ 0x0
951; CHECKLE-NEXT:    .long 0 @ 0x0
952; CHECKLE-NEXT:    .long 0 @ 0x0
953;
954; CHECKBE-LABEL: xor_int64_f_0:
955; CHECKBE:       @ %bb.0: @ %entry
956; CHECKBE-NEXT:    adr r0, .LCPI59_0
957; CHECKBE-NEXT:    vldrb.u8 q1, [r0]
958; CHECKBE-NEXT:    vrev64.8 q2, q1
959; CHECKBE-NEXT:    veor q0, q0, q2
960; CHECKBE-NEXT:    bx lr
961; CHECKBE-NEXT:    .p2align 4
962; CHECKBE-NEXT:  @ %bb.1:
963; CHECKBE-NEXT:  .LCPI59_0:
964; CHECKBE-NEXT:    .long 0 @ 0x0
965; CHECKBE-NEXT:    .long 255 @ 0xff
966; CHECKBE-NEXT:    .long 0 @ 0x0
967; CHECKBE-NEXT:    .long 0 @ 0x0
968entry:
969  %b = xor <2 x i64> %a, <i64 255, i64 0>
970  ret <2 x i64> %b
971}
972
973define arm_aapcs_vfpcc <16 x i8> @mov_int64_0f000f0f() {
974; CHECKLE-LABEL: mov_int64_0f000f0f:
975; CHECKLE:       @ %bb.0: @ %entry
976; CHECKLE-NEXT:    vmov.i64 q0, #0xff000000ff00ff
977; CHECKLE-NEXT:    bx lr
978;
979; CHECKBE-LABEL: mov_int64_0f000f0f:
980; CHECKBE:       @ %bb.0: @ %entry
981; CHECKBE-NEXT:    vmov.i64 q0, #0xff00ff000000ff00
982; CHECKBE-NEXT:    bx lr
983entry:
984  ret <16 x i8> <i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0>
985}
986
987define arm_aapcs_vfpcc <16 x i8> @xor_int64_0f000f0f(<16 x i8> %a) {
988; CHECKLE-LABEL: xor_int64_0f000f0f:
989; CHECKLE:       @ %bb.0: @ %entry
990; CHECKLE-NEXT:    vmov.i64 q1, #0xff000000ff00ff
991; CHECKLE-NEXT:    veor q0, q0, q1
992; CHECKLE-NEXT:    bx lr
993;
994; CHECKBE-LABEL: xor_int64_0f000f0f:
995; CHECKBE:       @ %bb.0: @ %entry
996; CHECKBE-NEXT:    vmov.i64 q1, #0xff000000ff00ff
997; CHECKBE-NEXT:    vrev64.8 q2, q0
998; CHECKBE-NEXT:    veor q1, q2, q1
999; CHECKBE-NEXT:    vrev64.8 q0, q1
1000; CHECKBE-NEXT:    bx lr
1001entry:
1002  %b = xor <16 x i8> %a, <i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0>
1003  ret <16 x i8> %b
1004}
1005
1006define arm_aapcs_vfpcc <8 x i16> @mov_int64_ff00ffff() {
1007; CHECKLE-LABEL: mov_int64_ff00ffff:
1008; CHECKLE:       @ %bb.0: @ %entry
1009; CHECKLE-NEXT:    vmov.i64 q0, #0xffffffff0000ffff
1010; CHECKLE-NEXT:    bx lr
1011;
1012; CHECKBE-LABEL: mov_int64_ff00ffff:
1013; CHECKBE:       @ %bb.0: @ %entry
1014; CHECKBE-NEXT:    vmov.i64 q0, #0xffff0000ffffffff
1015; CHECKBE-NEXT:    bx lr
1016entry:
1017  ret <8 x i16> <i16 -1, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1>
1018}
1019
1020define arm_aapcs_vfpcc <8 x i16> @xor_int64_ff00ffff(<8 x i16> %a) {
1021; CHECKLE-LABEL: xor_int64_ff00ffff:
1022; CHECKLE:       @ %bb.0: @ %entry
1023; CHECKLE-NEXT:    vmov.i64 q1, #0xffffffff0000ffff
1024; CHECKLE-NEXT:    veor q0, q0, q1
1025; CHECKLE-NEXT:    bx lr
1026;
1027; CHECKBE-LABEL: xor_int64_ff00ffff:
1028; CHECKBE:       @ %bb.0: @ %entry
1029; CHECKBE-NEXT:    vmov.i64 q1, #0xffffffff0000ffff
1030; CHECKBE-NEXT:    vrev64.16 q2, q0
1031; CHECKBE-NEXT:    veor q1, q2, q1
1032; CHECKBE-NEXT:    vrev64.16 q0, q1
1033; CHECKBE-NEXT:    bx lr
1034entry:
1035  %b = xor <8 x i16> %a, <i16 -1, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1>
1036  ret <8 x i16> %b
1037}
1038
1039define arm_aapcs_vfpcc <16 x i8> @mov_int64_0f0f0f0f0f0f0f0f() {
1040; CHECKLE-LABEL: mov_int64_0f0f0f0f0f0f0f0f:
1041; CHECKLE:       @ %bb.0: @ %entry
1042; CHECKLE-NEXT:    vmov.i16 q0, #0xff
1043; CHECKLE-NEXT:    bx lr
1044;
1045; CHECKBE-LABEL: mov_int64_0f0f0f0f0f0f0f0f:
1046; CHECKBE:       @ %bb.0: @ %entry
1047; CHECKBE-NEXT:    vmov.i16 q0, #0xff00
1048; CHECKBE-NEXT:    bx lr
1049entry:
1050  ret <16 x i8> <i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0>
1051}
1052
1053define arm_aapcs_vfpcc <16 x i8> @xor_int64_0f0f0f0f0f0f0f0f(<16 x i8> %a) {
1054; CHECKLE-LABEL: xor_int64_0f0f0f0f0f0f0f0f:
1055; CHECKLE:       @ %bb.0: @ %entry
1056; CHECKLE-NEXT:    vmov.i16 q1, #0xff
1057; CHECKLE-NEXT:    veor q0, q0, q1
1058; CHECKLE-NEXT:    bx lr
1059;
1060; CHECKBE-LABEL: xor_int64_0f0f0f0f0f0f0f0f:
1061; CHECKBE:       @ %bb.0: @ %entry
1062; CHECKBE-NEXT:    vmov.i16 q1, #0xff
1063; CHECKBE-NEXT:    vrev64.8 q2, q0
1064; CHECKBE-NEXT:    veor q1, q2, q1
1065; CHECKBE-NEXT:    vrev64.8 q0, q1
1066; CHECKBE-NEXT:    bx lr
1067entry:
1068  %b = xor <16 x i8> %a, <i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0>
1069  ret <16 x i8> %b
1070}
1071
1072define arm_aapcs_vfpcc <4 x float> @mov_float_1() {
1073; CHECK-LABEL: mov_float_1:
1074; CHECK:       @ %bb.0: @ %entry
1075; CHECK-NEXT:    mov.w r0, #1065353216
1076; CHECK-NEXT:    vdup.32 q0, r0
1077; CHECK-NEXT:    bx lr
1078entry:
1079  ret <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
1080}
1081
1082define arm_aapcs_vfpcc <4 x float> @fadd_float_1(<4 x float> %a) {
1083; CHECKBE-LABEL: fadd_float_1:
1084; CHECKBE:       @ %bb.0: @ %entry
1085; CHECKBE-NEXT:    vmov.f32 q1, #1.000000e+00
1086; CHECKBE-NEXT:    vrev64.32 q2, q0
1087; CHECKBE-NEXT:    vadd.f32 q1, q2, q1
1088; CHECKBE-NEXT:    vrev64.32 q0, q1
1089; CHECKBE-NEXT:    bx lr
1090entry:
1091  %b = fadd <4 x float> %a, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
1092  ret <4 x float> %b
1093}
1094
1095define arm_aapcs_vfpcc <4 x float> @mov_float_m3() {
1096; CHECK-LABEL: mov_float_m3:
1097; CHECK:       @ %bb.0: @ %entry
1098; CHECK-NEXT:    movs r0, #0
1099; CHECK-NEXT:    movt r0, #49216
1100; CHECK-NEXT:    vdup.32 q0, r0
1101; CHECK-NEXT:    bx lr
1102entry:
1103  ret <4 x float> <float -3.000000e+00, float -3.000000e+00, float -3.000000e+00, float -3.000000e+00>
1104}
1105
1106define arm_aapcs_vfpcc <4 x float> @fadd_float_m3(<4 x float> %a) {
1107; CHECKBE-LABEL: fadd_float_m3:
1108; CHECKBE:       @ %bb.0: @ %entry
1109; CHECKBE-NEXT:    vmov.f32 q1, #-3.000000e+00
1110; CHECKBE-NEXT:    vrev64.32 q2, q0
1111; CHECKBE-NEXT:    vadd.f32 q1, q2, q1
1112; CHECKBE-NEXT:    vrev64.32 q0, q1
1113; CHECKBE-NEXT:    bx lr
1114entry:
1115  %b = fadd <4 x float> %a, <float -3.000000e+00, float -3.000000e+00, float -3.000000e+00, float -3.000000e+00>
1116  ret <4 x float> %b
1117}
1118
1119define arm_aapcs_vfpcc <8 x half> @mov_float16_1() {
1120; CHECK-LABEL: mov_float16_1:
1121; CHECK:       @ %bb.0: @ %entry
1122; CHECK-NEXT:    vmov.i16 q0, #0x3c00
1123; CHECK-NEXT:    bx lr
1124entry:
1125  ret <8 x half> <half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00>
1126}
1127
1128define arm_aapcs_vfpcc <8 x half> @fadd_float16_1(<8 x half> %a) {
1129; CHECKBE-LABEL: fadd_float16_1:
1130; CHECKBE:       @ %bb.0: @ %entry
1131; CHECKBE-NEXT:    vmov.i16 q1, #0x3c00
1132; CHECKBE-NEXT:    vrev64.16 q2, q0
1133; CHECKBE-NEXT:    vadd.f16 q1, q2, q1
1134; CHECKBE-NEXT:    vrev64.16 q0, q1
1135; CHECKBE-NEXT:    bx lr
1136entry:
1137  %b = fadd <8 x half> %a, <half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00>
1138  ret <8 x half> %b
1139}
1140
1141define arm_aapcs_vfpcc <8 x half> @mov_float16_m3() {
1142; CHECK-LABEL: mov_float16_m3:
1143; CHECK:       @ %bb.0: @ %entry
1144; CHECK-NEXT:    vmov.i16 q0, #0xc200
1145; CHECK-NEXT:    bx lr
1146entry:
1147  ret <8 x half> <half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00>
1148}
1149
1150define arm_aapcs_vfpcc <8 x half> @fadd_float16_m3(<8 x half> %a) {
1151; CHECKBE-LABEL: fadd_float16_m3:
1152; CHECKBE:       @ %bb.0: @ %entry
1153; CHECKBE-NEXT:    vmov.i16 q1, #0xc200
1154; CHECKBE-NEXT:    vrev64.16 q2, q0
1155; CHECKBE-NEXT:    vadd.f16 q1, q2, q1
1156; CHECKBE-NEXT:    vrev64.16 q0, q1
1157; CHECKBE-NEXT:    bx lr
1158entry:
1159  %b = fadd <8 x half> %a, <half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00>
1160  ret <8 x half> %b
1161}
1162
1163define arm_aapcs_vfpcc <2 x double> @mov_double_1() {
1164; CHECKLE-LABEL: mov_double_1:
1165; CHECKLE:       @ %bb.0: @ %entry
1166; CHECKLE-NEXT:    adr r0, .LCPI74_0
1167; CHECKLE-NEXT:    vldrw.u32 q0, [r0]
1168; CHECKLE-NEXT:    bx lr
1169; CHECKLE-NEXT:    .p2align 4
1170; CHECKLE-NEXT:  @ %bb.1:
1171; CHECKLE-NEXT:  .LCPI74_0:
1172; CHECKLE-NEXT:    .long 0 @ double 1
1173; CHECKLE-NEXT:    .long 1072693248
1174; CHECKLE-NEXT:    .long 0 @ double 1
1175; CHECKLE-NEXT:    .long 1072693248
1176;
1177; CHECKBE-LABEL: mov_double_1:
1178; CHECKBE:       @ %bb.0: @ %entry
1179; CHECKBE-NEXT:    adr r0, .LCPI74_0
1180; CHECKBE-NEXT:    vldrb.u8 q1, [r0]
1181; CHECKBE-NEXT:    vrev64.8 q0, q1
1182; CHECKBE-NEXT:    bx lr
1183; CHECKBE-NEXT:    .p2align 4
1184; CHECKBE-NEXT:  @ %bb.1:
1185; CHECKBE-NEXT:  .LCPI74_0:
1186; CHECKBE-NEXT:    .long 1072693248 @ double 1
1187; CHECKBE-NEXT:    .long 0
1188; CHECKBE-NEXT:    .long 1072693248 @ double 1
1189; CHECKBE-NEXT:    .long 0
1190entry:
1191  ret <2 x double> <double 1.000000e+00, double 1.000000e+00>
1192}
1193
1194define arm_aapcs_vfpcc <16 x i8> @test(<16 x i8> %i) {
1195; CHECKLE-LABEL: test:
1196; CHECKLE:       @ %bb.0: @ %entry
1197; CHECKLE-NEXT:    vmov.i64 q1, #0xff000000ff00ff
1198; CHECKLE-NEXT:    vorr q0, q0, q1
1199; CHECKLE-NEXT:    bx lr
1200;
1201; CHECKBE-LABEL: test:
1202; CHECKBE:       @ %bb.0: @ %entry
1203; CHECKBE-NEXT:    vmov.i64 q1, #0xff000000ff00ff
1204; CHECKBE-NEXT:    vrev64.8 q2, q0
1205; CHECKBE-NEXT:    vorr q1, q2, q1
1206; CHECKBE-NEXT:    vrev64.8 q0, q1
1207; CHECKBE-NEXT:    bx lr
1208entry:
1209  %o = or <16 x i8> %i, <i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0>
1210  ret <16 x i8> %o
1211}
1212
1213define arm_aapcs_vfpcc <8 x i16> @test2(<8 x i16> %i) {
1214; CHECKLE-LABEL: test2:
1215; CHECKLE:       @ %bb.0: @ %entry
1216; CHECKLE-NEXT:    vmov.i64 q1, #0xffffffff0000ffff
1217; CHECKLE-NEXT:    vorr q0, q0, q1
1218; CHECKLE-NEXT:    bx lr
1219;
1220; CHECKBE-LABEL: test2:
1221; CHECKBE:       @ %bb.0: @ %entry
1222; CHECKBE-NEXT:    vmov.i64 q1, #0xffffffff0000ffff
1223; CHECKBE-NEXT:    vrev64.16 q2, q0
1224; CHECKBE-NEXT:    vorr q1, q2, q1
1225; CHECKBE-NEXT:    vrev64.16 q0, q1
1226; CHECKBE-NEXT:    bx lr
1227entry:
1228  %o = or <8 x i16> %i, <i16 -1, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1>
1229  ret <8 x i16> %o
1230}
1231
1232define arm_aapcs_vfpcc <4 x i32> @i1and_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c) {
1233; CHECKLE-LABEL: i1and_vmov:
1234; CHECKLE:       @ %bb.0: @ %entry
1235; CHECKLE-NEXT:    cmp r0, #0
1236; CHECKLE-NEXT:    mov.w r1, #15
1237; CHECKLE-NEXT:    csetm r0, eq
1238; CHECKLE-NEXT:    ands r0, r1
1239; CHECKLE-NEXT:    vmsr p0, r0
1240; CHECKLE-NEXT:    vpsel q0, q0, q1
1241; CHECKLE-NEXT:    bx lr
1242;
1243; CHECKBE-LABEL: i1and_vmov:
1244; CHECKBE:       @ %bb.0: @ %entry
1245; CHECKBE-NEXT:    cmp r0, #0
1246; CHECKBE-NEXT:    mov.w r1, #15
1247; CHECKBE-NEXT:    csetm r0, eq
1248; CHECKBE-NEXT:    vrev64.32 q2, q1
1249; CHECKBE-NEXT:    ands r0, r1
1250; CHECKBE-NEXT:    vrev64.32 q1, q0
1251; CHECKBE-NEXT:    vmsr p0, r0
1252; CHECKBE-NEXT:    vpsel q1, q1, q2
1253; CHECKBE-NEXT:    vrev64.32 q0, q1
1254; CHECKBE-NEXT:    bx lr
1255entry:
1256  %c1 = icmp eq i32 %c, zeroinitializer
1257  %broadcast.splatinsert1967 = insertelement <4 x i1> undef, i1 %c1, i32 0
1258  %broadcast.splat1968 = shufflevector <4 x i1> %broadcast.splatinsert1967, <4 x i1> undef, <4 x i32> zeroinitializer
1259  %l699 = and <4 x i1> %broadcast.splat1968, <i1 true, i1 false, i1 false, i1 false>
1260  %s = select <4 x i1> %l699, <4 x i32> %a, <4 x i32> %b
1261  ret <4 x i32> %s
1262}
1263
1264define arm_aapcs_vfpcc <4 x i32> @i1or_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c) {
1265; CHECKLE-LABEL: i1or_vmov:
1266; CHECKLE:       @ %bb.0: @ %entry
1267; CHECKLE-NEXT:    cmp r0, #0
1268; CHECKLE-NEXT:    mov.w r1, #15
1269; CHECKLE-NEXT:    csetm r0, eq
1270; CHECKLE-NEXT:    orrs r0, r1
1271; CHECKLE-NEXT:    vmsr p0, r0
1272; CHECKLE-NEXT:    vpsel q0, q0, q1
1273; CHECKLE-NEXT:    bx lr
1274;
1275; CHECKBE-LABEL: i1or_vmov:
1276; CHECKBE:       @ %bb.0: @ %entry
1277; CHECKBE-NEXT:    cmp r0, #0
1278; CHECKBE-NEXT:    mov.w r1, #15
1279; CHECKBE-NEXT:    csetm r0, eq
1280; CHECKBE-NEXT:    vrev64.32 q2, q1
1281; CHECKBE-NEXT:    orrs r0, r1
1282; CHECKBE-NEXT:    vrev64.32 q1, q0
1283; CHECKBE-NEXT:    vmsr p0, r0
1284; CHECKBE-NEXT:    vpsel q1, q1, q2
1285; CHECKBE-NEXT:    vrev64.32 q0, q1
1286; CHECKBE-NEXT:    bx lr
1287entry:
1288  %c1 = icmp eq i32 %c, zeroinitializer
1289  %broadcast.splatinsert1967 = insertelement <4 x i1> undef, i1 %c1, i32 0
1290  %broadcast.splat1968 = shufflevector <4 x i1> %broadcast.splatinsert1967, <4 x i1> undef, <4 x i32> zeroinitializer
1291  %l699 = or <4 x i1> %broadcast.splat1968, <i1 true, i1 false, i1 false, i1 false>
1292  %s = select <4 x i1> %l699, <4 x i32> %a, <4 x i32> %b
1293  ret <4 x i32> %s
1294}
1295
1296define arm_aapcs_vfpcc <2 x i64> @v2i1and_vmov(<2 x i64> %a, <2 x i64> %b, i32 %c) {
1297; CHECK-LABEL: v2i1and_vmov:
1298; CHECK:       @ %bb.0: @ %entry
1299; CHECK-NEXT:    cmp r0, #0
1300; CHECK-NEXT:    mov.w r1, #0
1301; CHECK-NEXT:    csetm r0, eq
1302; CHECK-NEXT:    bfi r1, r0, #0, #8
1303; CHECK-NEXT:    vmsr p0, r1
1304; CHECK-NEXT:    vpsel q0, q0, q1
1305; CHECK-NEXT:    bx lr
1306entry:
1307  %c1 = icmp eq i32 %c, zeroinitializer
1308  %broadcast.splatinsert1967 = insertelement <2 x i1> undef, i1 %c1, i32 0
1309  %broadcast.splat1968 = shufflevector <2 x i1> %broadcast.splatinsert1967, <2 x i1> undef, <2 x i32> zeroinitializer
1310  %l699 = and <2 x i1> %broadcast.splat1968, <i1 true, i1 false>
1311  %s = select <2 x i1> %l699, <2 x i64> %a, <2 x i64> %b
1312  ret <2 x i64> %s
1313}
1314
1315define arm_aapcs_vfpcc <2 x i64> @v2i1or_vmov(<2 x i64> %a, <2 x i64> %b, i32 %c) {
1316; CHECK-LABEL: v2i1or_vmov:
1317; CHECK:       @ %bb.0: @ %entry
1318; CHECK-NEXT:    cmp r0, #0
1319; CHECK-NEXT:    mov.w r1, #255
1320; CHECK-NEXT:    csetm r0, eq
1321; CHECK-NEXT:    bfi r1, r0, #8, #8
1322; CHECK-NEXT:    vmsr p0, r1
1323; CHECK-NEXT:    vpsel q0, q0, q1
1324; CHECK-NEXT:    bx lr
1325entry:
1326  %c1 = icmp eq i32 %c, zeroinitializer
1327  %broadcast.splatinsert1967 = insertelement <2 x i1> undef, i1 %c1, i32 0
1328  %broadcast.splat1968 = shufflevector <2 x i1> %broadcast.splatinsert1967, <2 x i1> undef, <2 x i32> zeroinitializer
1329  %l699 = or <2 x i1> %broadcast.splat1968, <i1 true, i1 false>
1330  %s = select <2 x i1> %l699, <2 x i64> %a, <2 x i64> %b
1331  ret <2 x i64> %s
1332}
1333
1334define arm_aapcs_vfpcc <8 x i16> @and_v8i16_m1(<8 x i16> %a) {
1335; CHECKLE-LABEL: and_v8i16_m1:
1336; CHECKLE:       @ %bb.0:
1337; CHECKLE-NEXT:    vbic.i32 q0, #0x10000
1338; CHECKLE-NEXT:    bx lr
1339;
1340; CHECKBE-LABEL: and_v8i16_m1:
1341; CHECKBE:       @ %bb.0:
1342; CHECKBE-NEXT:    vrev64.16 q1, q0
1343; CHECKBE-NEXT:    vbic.i32 q1, #0x10000
1344; CHECKBE-NEXT:    vrev64.16 q0, q1
1345; CHECKBE-NEXT:    bx lr
1346  %b = and <8 x i16> %a, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
1347  ret <8 x i16> %b
1348}
1349
1350define arm_aapcs_vfpcc <8 x i16> @or_v8i16_1(<8 x i16> %a) {
1351; CHECKLE-LABEL: or_v8i16_1:
1352; CHECKLE:       @ %bb.0:
1353; CHECKLE-NEXT:    vorr.i32 q0, #0x10000
1354; CHECKLE-NEXT:    bx lr
1355;
1356; CHECKBE-LABEL: or_v8i16_1:
1357; CHECKBE:       @ %bb.0:
1358; CHECKBE-NEXT:    vrev64.16 q1, q0
1359; CHECKBE-NEXT:    vorr.i32 q1, #0x10000
1360; CHECKBE-NEXT:    vrev64.16 q0, q1
1361; CHECKBE-NEXT:    bx lr
1362  %b = or <8 x i16> %a, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
1363  ret <8 x i16> %b
1364}
1365