xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-vld2.ll (revision 7b3bbd83c0c24087072ec5b22a76799ab31f87d5)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s
3
4; i32
5
6define void @vld2_v2i32(ptr %src, ptr %dst) {
7; CHECK-LABEL: vld2_v2i32:
8; CHECK:       @ %bb.0: @ %entry
9; CHECK-NEXT:    vldrw.u32 q0, [r0]
10; CHECK-NEXT:    vrev64.32 q1, q0
11; CHECK-NEXT:    vmov r2, s2
12; CHECK-NEXT:    vmov r0, s6
13; CHECK-NEXT:    vmov r3, s0
14; CHECK-NEXT:    add r0, r2
15; CHECK-NEXT:    vmov r2, s4
16; CHECK-NEXT:    add r2, r3
17; CHECK-NEXT:    strd r2, r0, [r1]
18; CHECK-NEXT:    bx lr
19entry:
20  %l1 = load <4 x i32>, ptr %src, align 4
21  %s1 = shufflevector <4 x i32> %l1, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
22  %s2 = shufflevector <4 x i32> %l1, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
23  %a = add <2 x i32> %s1, %s2
24  store <2 x i32> %a, ptr %dst
25  ret void
26}
27
28define void @vld2_v4i32(ptr %src, ptr %dst) {
29; CHECK-LABEL: vld2_v4i32:
30; CHECK:       @ %bb.0: @ %entry
31; CHECK-NEXT:    vld20.32 {q0, q1}, [r0]
32; CHECK-NEXT:    vld21.32 {q0, q1}, [r0]
33; CHECK-NEXT:    vadd.i32 q0, q0, q1
34; CHECK-NEXT:    vstrw.32 q0, [r1]
35; CHECK-NEXT:    bx lr
36entry:
37  %l1 = load <8 x i32>, ptr %src, align 4
38  %s1 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
39  %s2 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
40  %a = add <4 x i32> %s1, %s2
41  store <4 x i32> %a, ptr %dst
42  ret void
43}
44
45define void @vld2_v8i32(ptr %src, ptr %dst) {
46; CHECK-LABEL: vld2_v8i32:
47; CHECK:       @ %bb.0: @ %entry
48; CHECK-NEXT:    vld20.32 {q0, q1}, [r0]
49; CHECK-NEXT:    vld21.32 {q0, q1}, [r0]!
50; CHECK-NEXT:    vld20.32 {q2, q3}, [r0]
51; CHECK-NEXT:    vadd.i32 q0, q0, q1
52; CHECK-NEXT:    vld21.32 {q2, q3}, [r0]
53; CHECK-NEXT:    vstrw.32 q0, [r1]
54; CHECK-NEXT:    vadd.i32 q1, q2, q3
55; CHECK-NEXT:    vstrw.32 q1, [r1, #16]
56; CHECK-NEXT:    bx lr
57entry:
58  %l1 = load <16 x i32>, ptr %src, align 4
59  %s1 = shufflevector <16 x i32> %l1, <16 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
60  %s2 = shufflevector <16 x i32> %l1, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
61  %a = add <8 x i32> %s1, %s2
62  store <8 x i32> %a, ptr %dst
63  ret void
64}
65
66define void @vld2_v16i32(ptr %src, ptr %dst) {
67; CHECK-LABEL: vld2_v16i32:
68; CHECK:       @ %bb.0: @ %entry
69; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}
70; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13}
71; CHECK-NEXT:    vld20.32 {q0, q1}, [r0]
72; CHECK-NEXT:    add.w r2, r0, #96
73; CHECK-NEXT:    add.w r3, r0, #64
74; CHECK-NEXT:    vld20.32 {q3, q4}, [r2]
75; CHECK-NEXT:    vld21.32 {q0, q1}, [r0]!
76; CHECK-NEXT:    vld21.32 {q3, q4}, [r2]
77; CHECK-NEXT:    vld20.32 {q5, q6}, [r0]
78; CHECK-NEXT:    vadd.i32 q0, q0, q1
79; CHECK-NEXT:    vld20.32 {q1, q2}, [r3]
80; CHECK-NEXT:    vadd.i32 q3, q3, q4
81; CHECK-NEXT:    vld21.32 {q5, q6}, [r0]
82; CHECK-NEXT:    vld21.32 {q1, q2}, [r3]
83; CHECK-NEXT:    vstrw.32 q3, [r1, #48]
84; CHECK-NEXT:    vadd.i32 q5, q5, q6
85; CHECK-NEXT:    vstrw.32 q0, [r1]
86; CHECK-NEXT:    vadd.i32 q1, q1, q2
87; CHECK-NEXT:    vstrw.32 q5, [r1, #16]
88; CHECK-NEXT:    vstrw.32 q1, [r1, #32]
89; CHECK-NEXT:    vpop {d8, d9, d10, d11, d12, d13}
90; CHECK-NEXT:    bx lr
91entry:
92  %l1 = load <32 x i32>, ptr %src, align 4
93  %s1 = shufflevector <32 x i32> %l1, <32 x i32> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
94  %s2 = shufflevector <32 x i32> %l1, <32 x i32> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
95  %a = add <16 x i32> %s1, %s2
96  store <16 x i32> %a, ptr %dst
97  ret void
98}
99
100define void @vld2_v4i32_align1(ptr %src, ptr %dst) {
101; CHECK-LABEL: vld2_v4i32_align1:
102; CHECK:       @ %bb.0: @ %entry
103; CHECK-NEXT:    vldrb.u8 q0, [r0, #16]
104; CHECK-NEXT:    vldrb.u8 q1, [r0]
105; CHECK-NEXT:    vmov.f32 s8, s5
106; CHECK-NEXT:    vmov.f32 s9, s7
107; CHECK-NEXT:    vmov.f32 s5, s6
108; CHECK-NEXT:    vmov.f32 s10, s1
109; CHECK-NEXT:    vmov.f32 s11, s3
110; CHECK-NEXT:    vmov.f32 s6, s0
111; CHECK-NEXT:    vmov.f32 s7, s2
112; CHECK-NEXT:    vadd.i32 q0, q1, q2
113; CHECK-NEXT:    vstrw.32 q0, [r1]
114; CHECK-NEXT:    bx lr
115entry:
116  %l1 = load <8 x i32>, ptr %src, align 1
117  %s1 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
118  %s2 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
119  %a = add <4 x i32> %s1, %s2
120  store <4 x i32> %a, ptr %dst
121  ret void
122}
123
124; i16
125
126define void @vld2_v2i16(ptr %src, ptr %dst) {
127; CHECK-LABEL: vld2_v2i16:
128; CHECK:       @ %bb.0: @ %entry
129; CHECK-NEXT:    vldrh.u32 q0, [r0]
130; CHECK-NEXT:    vrev64.32 q1, q0
131; CHECK-NEXT:    vmov r2, s2
132; CHECK-NEXT:    vmov r0, s6
133; CHECK-NEXT:    add r0, r2
134; CHECK-NEXT:    strh r0, [r1, #2]
135; CHECK-NEXT:    vmov r0, s4
136; CHECK-NEXT:    vmov r2, s0
137; CHECK-NEXT:    add r0, r2
138; CHECK-NEXT:    strh r0, [r1]
139; CHECK-NEXT:    bx lr
140entry:
141  %l1 = load <4 x i16>, ptr %src, align 2
142  %s1 = shufflevector <4 x i16> %l1, <4 x i16> undef, <2 x i32> <i32 0, i32 2>
143  %s2 = shufflevector <4 x i16> %l1, <4 x i16> undef, <2 x i32> <i32 1, i32 3>
144  %a = add <2 x i16> %s1, %s2
145  store <2 x i16> %a, ptr %dst
146  ret void
147}
148
149define void @vld2_v4i16(ptr %src, ptr %dst) {
150; CHECK-LABEL: vld2_v4i16:
151; CHECK:       @ %bb.0: @ %entry
152; CHECK-NEXT:    vldrh.u16 q0, [r0]
153; CHECK-NEXT:    vrev32.16 q1, q0
154; CHECK-NEXT:    vadd.i32 q0, q0, q1
155; CHECK-NEXT:    vstrh.32 q0, [r1]
156; CHECK-NEXT:    bx lr
157entry:
158  %l1 = load <8 x i16>, ptr %src, align 2
159  %s1 = shufflevector <8 x i16> %l1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
160  %s2 = shufflevector <8 x i16> %l1, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
161  %a = add <4 x i16> %s1, %s2
162  store <4 x i16> %a, ptr %dst
163  ret void
164}
165
166define void @vld2_v8i16(ptr %src, ptr %dst) {
167; CHECK-LABEL: vld2_v8i16:
168; CHECK:       @ %bb.0: @ %entry
169; CHECK-NEXT:    vld20.16 {q0, q1}, [r0]
170; CHECK-NEXT:    vld21.16 {q0, q1}, [r0]
171; CHECK-NEXT:    vadd.i16 q0, q0, q1
172; CHECK-NEXT:    vstrw.32 q0, [r1]
173; CHECK-NEXT:    bx lr
174entry:
175  %l1 = load <16 x i16>, ptr %src, align 2
176  %s1 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
177  %s2 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
178  %a = add <8 x i16> %s1, %s2
179  store <8 x i16> %a, ptr %dst
180  ret void
181}
182
183define void @vld2_v16i16(ptr %src, ptr %dst) {
184; CHECK-LABEL: vld2_v16i16:
185; CHECK:       @ %bb.0: @ %entry
186; CHECK-NEXT:    vld20.16 {q0, q1}, [r0]
187; CHECK-NEXT:    vld21.16 {q0, q1}, [r0]!
188; CHECK-NEXT:    vld20.16 {q2, q3}, [r0]
189; CHECK-NEXT:    vadd.i16 q0, q0, q1
190; CHECK-NEXT:    vld21.16 {q2, q3}, [r0]
191; CHECK-NEXT:    vstrw.32 q0, [r1]
192; CHECK-NEXT:    vadd.i16 q1, q2, q3
193; CHECK-NEXT:    vstrw.32 q1, [r1, #16]
194; CHECK-NEXT:    bx lr
195entry:
196  %l1 = load <32 x i16>, ptr %src, align 2
197  %s1 = shufflevector <32 x i16> %l1, <32 x i16> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
198  %s2 = shufflevector <32 x i16> %l1, <32 x i16> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
199  %a = add <16 x i16> %s1, %s2
200  store <16 x i16> %a, ptr %dst
201  ret void
202}
203
204define void @vld2_v8i16_align1(ptr %src, ptr %dst) {
205; CHECK-LABEL: vld2_v8i16_align1:
206; CHECK:       @ %bb.0: @ %entry
207; CHECK-NEXT:    .pad #32
208; CHECK-NEXT:    sub sp, #32
209; CHECK-NEXT:    vldrb.u8 q0, [r0, #16]
210; CHECK-NEXT:    add r2, sp, #16
211; CHECK-NEXT:    vshr.u32 q1, q0, #16
212; CHECK-NEXT:    vstrh.32 q1, [r2, #8]
213; CHECK-NEXT:    vldrb.u8 q1, [r0]
214; CHECK-NEXT:    mov r0, sp
215; CHECK-NEXT:    vshr.u32 q2, q1, #16
216; CHECK-NEXT:    vstrh.32 q2, [r2]
217; CHECK-NEXT:    vstrh.32 q0, [r0, #8]
218; CHECK-NEXT:    vstrh.32 q1, [r0]
219; CHECK-NEXT:    vldrw.u32 q0, [r2]
220; CHECK-NEXT:    vldrw.u32 q1, [r0]
221; CHECK-NEXT:    vadd.i16 q0, q1, q0
222; CHECK-NEXT:    vstrw.32 q0, [r1]
223; CHECK-NEXT:    add sp, #32
224; CHECK-NEXT:    bx lr
225entry:
226  %l1 = load <16 x i16>, ptr %src, align 1
227  %s1 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
228  %s2 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
229  %a = add <8 x i16> %s1, %s2
230  store <8 x i16> %a, ptr %dst
231  ret void
232}
233
234; i8
235
236define void @vld2_v2i8(ptr %src, ptr %dst) {
237; CHECK-LABEL: vld2_v2i8:
238; CHECK:       @ %bb.0: @ %entry
239; CHECK-NEXT:    vldrb.u32 q0, [r0]
240; CHECK-NEXT:    vrev64.32 q1, q0
241; CHECK-NEXT:    vmov r2, s2
242; CHECK-NEXT:    vmov r0, s6
243; CHECK-NEXT:    add r0, r2
244; CHECK-NEXT:    strb r0, [r1, #1]
245; CHECK-NEXT:    vmov r0, s4
246; CHECK-NEXT:    vmov r2, s0
247; CHECK-NEXT:    add r0, r2
248; CHECK-NEXT:    strb r0, [r1]
249; CHECK-NEXT:    bx lr
250entry:
251  %l1 = load <4 x i8>, ptr %src, align 1
252  %s1 = shufflevector <4 x i8> %l1, <4 x i8> undef, <2 x i32> <i32 0, i32 2>
253  %s2 = shufflevector <4 x i8> %l1, <4 x i8> undef, <2 x i32> <i32 1, i32 3>
254  %a = add <2 x i8> %s1, %s2
255  store <2 x i8> %a, ptr %dst
256  ret void
257}
258
259define void @vld2_v4i8(ptr %src, ptr %dst) {
260; CHECK-LABEL: vld2_v4i8:
261; CHECK:       @ %bb.0: @ %entry
262; CHECK-NEXT:    vldrb.u16 q0, [r0]
263; CHECK-NEXT:    vrev32.16 q1, q0
264; CHECK-NEXT:    vadd.i32 q0, q0, q1
265; CHECK-NEXT:    vstrb.32 q0, [r1]
266; CHECK-NEXT:    bx lr
267entry:
268  %l1 = load <8 x i8>, ptr %src, align 1
269  %s1 = shufflevector <8 x i8> %l1, <8 x i8> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
270  %s2 = shufflevector <8 x i8> %l1, <8 x i8> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
271  %a = add <4 x i8> %s1, %s2
272  store <4 x i8> %a, ptr %dst
273  ret void
274}
275
276define void @vld2_v8i8(ptr %src, ptr %dst) {
277; CHECK-LABEL: vld2_v8i8:
278; CHECK:       @ %bb.0: @ %entry
279; CHECK-NEXT:    vldrb.u8 q0, [r0]
280; CHECK-NEXT:    vrev16.8 q1, q0
281; CHECK-NEXT:    vadd.i16 q0, q0, q1
282; CHECK-NEXT:    vstrb.16 q0, [r1]
283; CHECK-NEXT:    bx lr
284entry:
285  %l1 = load <16 x i8>, ptr %src, align 1
286  %s1 = shufflevector <16 x i8> %l1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
287  %s2 = shufflevector <16 x i8> %l1, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
288  %a = add <8 x i8> %s1, %s2
289  store <8 x i8> %a, ptr %dst
290  ret void
291}
292
293define void @vld2_v16i8(ptr %src, ptr %dst) {
294; CHECK-LABEL: vld2_v16i8:
295; CHECK:       @ %bb.0: @ %entry
296; CHECK-NEXT:    vld20.8 {q0, q1}, [r0]
297; CHECK-NEXT:    vld21.8 {q0, q1}, [r0]
298; CHECK-NEXT:    vadd.i8 q0, q0, q1
299; CHECK-NEXT:    vstrw.32 q0, [r1]
300; CHECK-NEXT:    bx lr
301entry:
302  %l1 = load <32 x i8>, ptr %src, align 1
303  %s1 = shufflevector <32 x i8> %l1, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
304  %s2 = shufflevector <32 x i8> %l1, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
305  %a = add <16 x i8> %s1, %s2
306  store <16 x i8> %a, ptr %dst
307  ret void
308}
309
310; i64
311
312define void @vld2_v2i64(ptr %src, ptr %dst) {
313; CHECK-LABEL: vld2_v2i64:
314; CHECK:       @ %bb.0: @ %entry
315; CHECK-NEXT:    .save {r4, r5, r6, lr}
316; CHECK-NEXT:    push {r4, r5, r6, lr}
317; CHECK-NEXT:    vldrw.u32 q0, [r0, #16]
318; CHECK-NEXT:    vmov lr, r12, d1
319; CHECK-NEXT:    vmov r3, r2, d0
320; CHECK-NEXT:    vldrw.u32 q0, [r0]
321; CHECK-NEXT:    vmov r0, r4, d1
322; CHECK-NEXT:    vmov r5, r6, d0
323; CHECK-NEXT:    adds.w r3, r3, lr
324; CHECK-NEXT:    adc.w r2, r2, r12
325; CHECK-NEXT:    adds r0, r0, r5
326; CHECK-NEXT:    adcs r6, r4
327; CHECK-NEXT:    vmov q0[2], q0[0], r0, r3
328; CHECK-NEXT:    vmov q0[3], q0[1], r6, r2
329; CHECK-NEXT:    vstrw.32 q0, [r1]
330; CHECK-NEXT:    pop {r4, r5, r6, pc}
331entry:
332  %l1 = load <4 x i64>, ptr %src, align 8
333  %s1 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 0, i32 2>
334  %s2 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 1, i32 3>
335  %a = add <2 x i64> %s1, %s2
336  store <2 x i64> %a, ptr %dst
337  ret void
338}
339
340define void @vld2_v4i64(ptr %src, ptr %dst) {
341; CHECK-LABEL: vld2_v4i64:
342; CHECK:       @ %bb.0: @ %entry
343; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, lr}
344; CHECK-NEXT:    push.w {r4, r5, r6, r7, r8, lr}
345; CHECK-NEXT:    .vsave {d8}
346; CHECK-NEXT:    vpush {d8}
347; CHECK-NEXT:    vldrw.u32 q0, [r0]
348; CHECK-NEXT:    vldrw.u32 q2, [r0, #16]
349; CHECK-NEXT:    vldrw.u32 q3, [r0, #48]
350; CHECK-NEXT:    vmov.f32 s4, s2
351; CHECK-NEXT:    vmov.f32 s5, s3
352; CHECK-NEXT:    vmov lr, r12, d5
353; CHECK-NEXT:    vmov.f32 s2, s8
354; CHECK-NEXT:    vmov.f32 s3, s9
355; CHECK-NEXT:    vldrw.u32 q2, [r0, #32]
356; CHECK-NEXT:    vmov.f32 s16, s10
357; CHECK-NEXT:    vmov.f32 s17, s11
358; CHECK-NEXT:    vmov r5, r6, d4
359; CHECK-NEXT:    vmov r2, r3, d1
360; CHECK-NEXT:    vmov.f32 s2, s12
361; CHECK-NEXT:    vmov.f32 s3, s13
362; CHECK-NEXT:    vmov r0, r7, d8
363; CHECK-NEXT:    adds.w lr, lr, r2
364; CHECK-NEXT:    adc.w r12, r12, r3
365; CHECK-NEXT:    vmov r3, r4, d7
366; CHECK-NEXT:    adds r0, r0, r5
367; CHECK-NEXT:    adc.w r8, r6, r7
368; CHECK-NEXT:    vmov r6, r5, d1
369; CHECK-NEXT:    vmov r2, r7, d0
370; CHECK-NEXT:    adds r3, r3, r6
371; CHECK-NEXT:    adc.w r6, r5, r4
372; CHECK-NEXT:    vmov r5, r4, d2
373; CHECK-NEXT:    vmov q1[2], q1[0], r0, r3
374; CHECK-NEXT:    vmov q1[3], q1[1], r8, r6
375; CHECK-NEXT:    vstrw.32 q1, [r1, #16]
376; CHECK-NEXT:    adds r2, r2, r5
377; CHECK-NEXT:    vmov q0[2], q0[0], r2, lr
378; CHECK-NEXT:    adc.w r0, r7, r4
379; CHECK-NEXT:    vmov q0[3], q0[1], r0, r12
380; CHECK-NEXT:    vstrw.32 q0, [r1]
381; CHECK-NEXT:    vpop {d8}
382; CHECK-NEXT:    pop.w {r4, r5, r6, r7, r8, pc}
383entry:
384  %l1 = load <8 x i64>, ptr %src, align 8
385  %s1 = shufflevector <8 x i64> %l1, <8 x i64> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
386  %s2 = shufflevector <8 x i64> %l1, <8 x i64> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
387  %a = add <4 x i64> %s1, %s2
388  store <4 x i64> %a, ptr %dst
389  ret void
390}
391
392; f32
393
394define void @vld2_v2f32(ptr %src, ptr %dst) {
395; CHECK-LABEL: vld2_v2f32:
396; CHECK:       @ %bb.0: @ %entry
397; CHECK-NEXT:    vldrw.u32 q0, [r0]
398; CHECK-NEXT:    vmov.f32 s4, s1
399; CHECK-NEXT:    vmov.f32 s5, s3
400; CHECK-NEXT:    vmov.f32 s1, s2
401; CHECK-NEXT:    vadd.f32 q0, q0, q1
402; CHECK-NEXT:    vstmia r1, {s0, s1}
403; CHECK-NEXT:    bx lr
404entry:
405  %l1 = load <4 x float>, ptr %src, align 4
406  %s1 = shufflevector <4 x float> %l1, <4 x float> undef, <2 x i32> <i32 0, i32 2>
407  %s2 = shufflevector <4 x float> %l1, <4 x float> undef, <2 x i32> <i32 1, i32 3>
408  %a = fadd <2 x float> %s1, %s2
409  store <2 x float> %a, ptr %dst
410  ret void
411}
412
413define void @vld2_v4f32(ptr %src, ptr %dst) {
414; CHECK-LABEL: vld2_v4f32:
415; CHECK:       @ %bb.0: @ %entry
416; CHECK-NEXT:    vld20.32 {q0, q1}, [r0]
417; CHECK-NEXT:    vld21.32 {q0, q1}, [r0]
418; CHECK-NEXT:    vadd.f32 q0, q0, q1
419; CHECK-NEXT:    vstrw.32 q0, [r1]
420; CHECK-NEXT:    bx lr
421entry:
422  %l1 = load <8 x float>, ptr %src, align 4
423  %s1 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
424  %s2 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
425  %a = fadd <4 x float> %s1, %s2
426  store <4 x float> %a, ptr %dst
427  ret void
428}
429
430define void @vld2_v8f32(ptr %src, ptr %dst) {
431; CHECK-LABEL: vld2_v8f32:
432; CHECK:       @ %bb.0: @ %entry
433; CHECK-NEXT:    vld20.32 {q0, q1}, [r0]
434; CHECK-NEXT:    vld21.32 {q0, q1}, [r0]!
435; CHECK-NEXT:    vld20.32 {q2, q3}, [r0]
436; CHECK-NEXT:    vadd.f32 q0, q0, q1
437; CHECK-NEXT:    vld21.32 {q2, q3}, [r0]
438; CHECK-NEXT:    vstrw.32 q0, [r1]
439; CHECK-NEXT:    vadd.f32 q1, q2, q3
440; CHECK-NEXT:    vstrw.32 q1, [r1, #16]
441; CHECK-NEXT:    bx lr
442entry:
443  %l1 = load <16 x float>, ptr %src, align 4
444  %s1 = shufflevector <16 x float> %l1, <16 x float> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
445  %s2 = shufflevector <16 x float> %l1, <16 x float> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
446  %a = fadd <8 x float> %s1, %s2
447  store <8 x float> %a, ptr %dst
448  ret void
449}
450
451define void @vld2_v16f32(ptr %src, ptr %dst) {
452; CHECK-LABEL: vld2_v16f32:
453; CHECK:       @ %bb.0: @ %entry
454; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}
455; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13}
456; CHECK-NEXT:    vld20.32 {q0, q1}, [r0]
457; CHECK-NEXT:    add.w r2, r0, #96
458; CHECK-NEXT:    add.w r3, r0, #64
459; CHECK-NEXT:    vld20.32 {q3, q4}, [r2]
460; CHECK-NEXT:    vld21.32 {q0, q1}, [r0]!
461; CHECK-NEXT:    vld21.32 {q3, q4}, [r2]
462; CHECK-NEXT:    vld20.32 {q5, q6}, [r0]
463; CHECK-NEXT:    vadd.f32 q0, q0, q1
464; CHECK-NEXT:    vld20.32 {q1, q2}, [r3]
465; CHECK-NEXT:    vadd.f32 q3, q3, q4
466; CHECK-NEXT:    vld21.32 {q5, q6}, [r0]
467; CHECK-NEXT:    vld21.32 {q1, q2}, [r3]
468; CHECK-NEXT:    vstrw.32 q3, [r1, #48]
469; CHECK-NEXT:    vadd.f32 q5, q5, q6
470; CHECK-NEXT:    vstrw.32 q0, [r1]
471; CHECK-NEXT:    vadd.f32 q1, q1, q2
472; CHECK-NEXT:    vstrw.32 q5, [r1, #16]
473; CHECK-NEXT:    vstrw.32 q1, [r1, #32]
474; CHECK-NEXT:    vpop {d8, d9, d10, d11, d12, d13}
475; CHECK-NEXT:    bx lr
476entry:
477  %l1 = load <32 x float>, ptr %src, align 4
478  %s1 = shufflevector <32 x float> %l1, <32 x float> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
479  %s2 = shufflevector <32 x float> %l1, <32 x float> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
480  %a = fadd <16 x float> %s1, %s2
481  store <16 x float> %a, ptr %dst
482  ret void
483}
484
485define void @vld2_v4f32_align1(ptr %src, ptr %dst) {
486; CHECK-LABEL: vld2_v4f32_align1:
487; CHECK:       @ %bb.0: @ %entry
488; CHECK-NEXT:    vldrb.u8 q0, [r0, #16]
489; CHECK-NEXT:    vldrb.u8 q1, [r0]
490; CHECK-NEXT:    vmov.f32 s8, s5
491; CHECK-NEXT:    vmov.f32 s9, s7
492; CHECK-NEXT:    vmov.f32 s5, s6
493; CHECK-NEXT:    vmov.f32 s10, s1
494; CHECK-NEXT:    vmov.f32 s11, s3
495; CHECK-NEXT:    vmov.f32 s6, s0
496; CHECK-NEXT:    vmov.f32 s7, s2
497; CHECK-NEXT:    vadd.f32 q0, q1, q2
498; CHECK-NEXT:    vstrw.32 q0, [r1]
499; CHECK-NEXT:    bx lr
500entry:
501  %l1 = load <8 x float>, ptr %src, align 1
502  %s1 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
503  %s2 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
504  %a = fadd <4 x float> %s1, %s2
505  store <4 x float> %a, ptr %dst
506  ret void
507}
508
509; f16
510
511define void @vld2_v2f16(ptr %src, ptr %dst) {
512; CHECK-LABEL: vld2_v2f16:
513; CHECK:       @ %bb.0: @ %entry
514; CHECK-NEXT:    ldr r2, [r0]
515; CHECK-NEXT:    ldr r0, [r0, #4]
516; CHECK-NEXT:    vmov.32 q0[0], r2
517; CHECK-NEXT:    vmov.32 q0[1], r0
518; CHECK-NEXT:    vmovx.f16 s4, s0
519; CHECK-NEXT:    vmovx.f16 s2, s1
520; CHECK-NEXT:    vins.f16 s4, s2
521; CHECK-NEXT:    vins.f16 s0, s1
522; CHECK-NEXT:    vadd.f16 q0, q0, q1
523; CHECK-NEXT:    vmov r0, s0
524; CHECK-NEXT:    str r0, [r1]
525; CHECK-NEXT:    bx lr
526entry:
527  %l1 = load <4 x half>, ptr %src, align 2
528  %s1 = shufflevector <4 x half> %l1, <4 x half> undef, <2 x i32> <i32 0, i32 2>
529  %s2 = shufflevector <4 x half> %l1, <4 x half> undef, <2 x i32> <i32 1, i32 3>
530  %a = fadd <2 x half> %s1, %s2
531  store <2 x half> %a, ptr %dst
532  ret void
533}
534
535define void @vld2_v4f16(ptr %src, ptr %dst) {
536; CHECK-LABEL: vld2_v4f16:
537; CHECK:       @ %bb.0: @ %entry
538; CHECK-NEXT:    vldrh.u16 q0, [r0]
539; CHECK-NEXT:    vmovx.f16 s4, s0
540; CHECK-NEXT:    vmovx.f16 s6, s1
541; CHECK-NEXT:    vins.f16 s4, s6
542; CHECK-NEXT:    vmovx.f16 s5, s2
543; CHECK-NEXT:    vmovx.f16 s6, s3
544; CHECK-NEXT:    vins.f16 s2, s3
545; CHECK-NEXT:    vins.f16 s0, s1
546; CHECK-NEXT:    vins.f16 s5, s6
547; CHECK-NEXT:    vmov.f32 s1, s2
548; CHECK-NEXT:    vadd.f16 q0, q0, q1
549; CHECK-NEXT:    vmov r0, r2, d0
550; CHECK-NEXT:    strd r0, r2, [r1]
551; CHECK-NEXT:    bx lr
552entry:
553  %l1 = load <8 x half>, ptr %src, align 2
554  %s1 = shufflevector <8 x half> %l1, <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
555  %s2 = shufflevector <8 x half> %l1, <8 x half> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
556  %a = fadd <4 x half> %s1, %s2
557  store <4 x half> %a, ptr %dst
558  ret void
559}
560
561define void @vld2_v8f16(ptr %src, ptr %dst) {
562; CHECK-LABEL: vld2_v8f16:
563; CHECK:       @ %bb.0: @ %entry
564; CHECK-NEXT:    vld20.16 {q0, q1}, [r0]
565; CHECK-NEXT:    vld21.16 {q0, q1}, [r0]
566; CHECK-NEXT:    vadd.f16 q0, q0, q1
567; CHECK-NEXT:    vstrw.32 q0, [r1]
568; CHECK-NEXT:    bx lr
569entry:
570  %l1 = load <16 x half>, ptr %src, align 2
571  %s1 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
572  %s2 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
573  %a = fadd <8 x half> %s1, %s2
574  store <8 x half> %a, ptr %dst
575  ret void
576}
577
578define void @vld2_v16f16(ptr %src, ptr %dst) {
579; CHECK-LABEL: vld2_v16f16:
580; CHECK:       @ %bb.0: @ %entry
581; CHECK-NEXT:    vld20.16 {q0, q1}, [r0]
582; CHECK-NEXT:    vld21.16 {q0, q1}, [r0]!
583; CHECK-NEXT:    vld20.16 {q2, q3}, [r0]
584; CHECK-NEXT:    vadd.f16 q0, q0, q1
585; CHECK-NEXT:    vld21.16 {q2, q3}, [r0]
586; CHECK-NEXT:    vstrw.32 q0, [r1]
587; CHECK-NEXT:    vadd.f16 q2, q2, q3
588; CHECK-NEXT:    vstrw.32 q2, [r1, #16]
589; CHECK-NEXT:    bx lr
590entry:
591  %l1 = load <32 x half>, ptr %src, align 2
592  %s1 = shufflevector <32 x half> %l1, <32 x half> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
593  %s2 = shufflevector <32 x half> %l1, <32 x half> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
594  %a = fadd <16 x half> %s1, %s2
595  store <16 x half> %a, ptr %dst
596  ret void
597}
598
599define void @vld2_v8f16_align1(ptr %src, ptr %dst) {
600; CHECK-LABEL: vld2_v8f16_align1:
601; CHECK:       @ %bb.0: @ %entry
602; CHECK-NEXT:    vldrb.u8 q0, [r0]
603; CHECK-NEXT:    vldrb.u8 q2, [r0, #16]
604; CHECK-NEXT:    vmovx.f16 s4, s0
605; CHECK-NEXT:    vmovx.f16 s6, s1
606; CHECK-NEXT:    vins.f16 s4, s6
607; CHECK-NEXT:    vmovx.f16 s5, s2
608; CHECK-NEXT:    vmovx.f16 s6, s3
609; CHECK-NEXT:    vmovx.f16 s12, s9
610; CHECK-NEXT:    vins.f16 s5, s6
611; CHECK-NEXT:    vmovx.f16 s6, s8
612; CHECK-NEXT:    vins.f16 s6, s12
613; CHECK-NEXT:    vmovx.f16 s7, s10
614; CHECK-NEXT:    vmovx.f16 s12, s11
615; CHECK-NEXT:    vins.f16 s2, s3
616; CHECK-NEXT:    vins.f16 s10, s11
617; CHECK-NEXT:    vins.f16 s8, s9
618; CHECK-NEXT:    vins.f16 s0, s1
619; CHECK-NEXT:    vmov.f32 s1, s2
620; CHECK-NEXT:    vins.f16 s7, s12
621; CHECK-NEXT:    vmov.f32 s2, s8
622; CHECK-NEXT:    vmov.f32 s3, s10
623; CHECK-NEXT:    vadd.f16 q0, q0, q1
624; CHECK-NEXT:    vstrw.32 q0, [r1]
625; CHECK-NEXT:    bx lr
626entry:
627  %l1 = load <16 x half>, ptr %src, align 1
628  %s1 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
629  %s2 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
630  %a = fadd <8 x half> %s1, %s2
631  store <8 x half> %a, ptr %dst
632  ret void
633}
634
635; f64
636
637define void @vld2_v2f64(ptr %src, ptr %dst) {
638; CHECK-LABEL: vld2_v2f64:
639; CHECK:       @ %bb.0: @ %entry
640; CHECK-NEXT:    vldrw.u32 q0, [r0, #16]
641; CHECK-NEXT:    vldrw.u32 q1, [r0]
642; CHECK-NEXT:    vadd.f64 d1, d0, d1
643; CHECK-NEXT:    vadd.f64 d0, d2, d3
644; CHECK-NEXT:    vstrw.32 q0, [r1]
645; CHECK-NEXT:    bx lr
646entry:
647  %l1 = load <4 x double>, ptr %src, align 8
648  %s1 = shufflevector <4 x double> %l1, <4 x double> undef, <2 x i32> <i32 0, i32 2>
649  %s2 = shufflevector <4 x double> %l1, <4 x double> undef, <2 x i32> <i32 1, i32 3>
650  %a = fadd <2 x double> %s1, %s2
651  store <2 x double> %a, ptr %dst
652  ret void
653}
654
655define void @vld2_v4f64(ptr %src, ptr %dst) {
656; CHECK-LABEL: vld2_v4f64:
657; CHECK:       @ %bb.0: @ %entry
658; CHECK-NEXT:    vldrw.u32 q0, [r0, #48]
659; CHECK-NEXT:    vldrw.u32 q1, [r0, #32]
660; CHECK-NEXT:    vldrw.u32 q2, [r0]
661; CHECK-NEXT:    vadd.f64 d1, d0, d1
662; CHECK-NEXT:    vadd.f64 d0, d2, d3
663; CHECK-NEXT:    vldrw.u32 q1, [r0, #16]
664; CHECK-NEXT:    vadd.f64 d3, d2, d3
665; CHECK-NEXT:    vstrw.32 q0, [r1, #16]
666; CHECK-NEXT:    vadd.f64 d2, d4, d5
667; CHECK-NEXT:    vstrw.32 q1, [r1]
668; CHECK-NEXT:    bx lr
669entry:
670  %l1 = load <8 x double>, ptr %src, align 8
671  %s1 = shufflevector <8 x double> %l1, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
672  %s2 = shufflevector <8 x double> %l1, <8 x double> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
673  %a = fadd <4 x double> %s1, %s2
674  store <4 x double> %a, ptr %dst
675  ret void
676}
677