1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s 3 4; i32 5 6define ptr @vld2_v4i32(ptr %src, ptr %dst) { 7; CHECK-LABEL: vld2_v4i32: 8; CHECK: @ %bb.0: @ %entry 9; CHECK-NEXT: vld20.32 {q0, q1}, [r0] 10; CHECK-NEXT: vld21.32 {q0, q1}, [r0]! 11; CHECK-NEXT: vadd.i32 q0, q0, q1 12; CHECK-NEXT: vstrw.32 q0, [r1] 13; CHECK-NEXT: bx lr 14entry: 15 %l1 = load <8 x i32>, ptr %src, align 4 16 %s1 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> 17 %s2 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> 18 %a = add <4 x i32> %s1, %s2 19 store <4 x i32> %a, ptr %dst 20 %ret = getelementptr inbounds <8 x i32>, ptr %src, i32 1 21 ret ptr %ret 22} 23 24; i16 25 26define ptr @vld2_v8i16(ptr %src, ptr %dst) { 27; CHECK-LABEL: vld2_v8i16: 28; CHECK: @ %bb.0: @ %entry 29; CHECK-NEXT: vld20.16 {q0, q1}, [r0] 30; CHECK-NEXT: vld21.16 {q0, q1}, [r0]! 31; CHECK-NEXT: vadd.i16 q0, q0, q1 32; CHECK-NEXT: vstrw.32 q0, [r1] 33; CHECK-NEXT: bx lr 34entry: 35 %l1 = load <16 x i16>, ptr %src, align 4 36 %s1 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> 37 %s2 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> 38 %a = add <8 x i16> %s1, %s2 39 store <8 x i16> %a, ptr %dst 40 %ret = getelementptr inbounds <16 x i16>, ptr %src, i32 1 41 ret ptr %ret 42} 43 44; i8 45 46define ptr @vld2_v16i8(ptr %src, ptr %dst) { 47; CHECK-LABEL: vld2_v16i8: 48; CHECK: @ %bb.0: @ %entry 49; CHECK-NEXT: vld20.8 {q0, q1}, [r0] 50; CHECK-NEXT: vld21.8 {q0, q1}, [r0]! 51; CHECK-NEXT: vadd.i8 q0, q0, q1 52; CHECK-NEXT: vstrw.32 q0, [r1] 53; CHECK-NEXT: bx lr 54entry: 55 %l1 = load <32 x i8>, ptr %src, align 4 56 %s1 = shufflevector <32 x i8> %l1, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> 57 %s2 = shufflevector <32 x i8> %l1, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> 58 %a = add <16 x i8> %s1, %s2 59 store <16 x i8> %a, ptr %dst 60 %ret = getelementptr inbounds <32 x i8>, ptr %src, i32 1 61 ret ptr %ret 62} 63 64; i64 65 66define ptr @vld2_v2i64(ptr %src, ptr %dst) { 67; CHECK-LABEL: vld2_v2i64: 68; CHECK: @ %bb.0: @ %entry 69; CHECK-NEXT: .save {r4, r5, r6, r7, lr} 70; CHECK-NEXT: push {r4, r5, r6, r7, lr} 71; CHECK-NEXT: vldrw.u32 q0, [r0, #16] 72; CHECK-NEXT: vmov r2, r12, d1 73; CHECK-NEXT: vmov r3, lr, d0 74; CHECK-NEXT: vldrw.u32 q0, [r0], #32 75; CHECK-NEXT: vmov r4, r7, d1 76; CHECK-NEXT: adds r2, r2, r3 77; CHECK-NEXT: vmov r3, r6, d0 78; CHECK-NEXT: adc.w r5, lr, r12 79; CHECK-NEXT: adds r3, r3, r4 80; CHECK-NEXT: adcs r7, r6 81; CHECK-NEXT: vmov q0[2], q0[0], r3, r2 82; CHECK-NEXT: vmov q0[3], q0[1], r7, r5 83; CHECK-NEXT: vstrw.32 q0, [r1] 84; CHECK-NEXT: pop {r4, r5, r6, r7, pc} 85entry: 86 %l1 = load <4 x i64>, ptr %src, align 4 87 %s1 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 0, i32 2> 88 %s2 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 1, i32 3> 89 %a = add <2 x i64> %s1, %s2 90 store <2 x i64> %a, ptr %dst 91 %ret = getelementptr inbounds <4 x i64>, ptr %src, i32 1 92 ret ptr %ret 93} 94 95; f32 96 97define ptr @vld2_v4f32(ptr %src, ptr %dst) { 98; CHECK-LABEL: vld2_v4f32: 99; CHECK: @ %bb.0: @ %entry 100; CHECK-NEXT: vld20.32 {q0, q1}, [r0] 101; CHECK-NEXT: vld21.32 {q0, q1}, [r0]! 102; CHECK-NEXT: vadd.f32 q0, q0, q1 103; CHECK-NEXT: vstrw.32 q0, [r1] 104; CHECK-NEXT: bx lr 105entry: 106 %l1 = load <8 x float>, ptr %src, align 4 107 %s1 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> 108 %s2 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> 109 %a = fadd <4 x float> %s1, %s2 110 store <4 x float> %a, ptr %dst 111 %ret = getelementptr inbounds <8 x float>, ptr %src, i32 1 112 ret ptr %ret 113} 114 115; f16 116 117define ptr @vld2_v8f16(ptr %src, ptr %dst) { 118; CHECK-LABEL: vld2_v8f16: 119; CHECK: @ %bb.0: @ %entry 120; CHECK-NEXT: vld20.16 {q0, q1}, [r0] 121; CHECK-NEXT: vld21.16 {q0, q1}, [r0]! 122; CHECK-NEXT: vadd.f16 q0, q0, q1 123; CHECK-NEXT: vstrw.32 q0, [r1] 124; CHECK-NEXT: bx lr 125entry: 126 %l1 = load <16 x half>, ptr %src, align 4 127 %s1 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> 128 %s2 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> 129 %a = fadd <8 x half> %s1, %s2 130 store <8 x half> %a, ptr %dst 131 %ret = getelementptr inbounds <16 x half>, ptr %src, i32 1 132 ret ptr %ret 133} 134 135; f64 136 137define ptr @vld2_v2f64(ptr %src, ptr %dst) { 138; CHECK-LABEL: vld2_v2f64: 139; CHECK: @ %bb.0: @ %entry 140; CHECK-NEXT: vldrw.u32 q0, [r0, #16] 141; CHECK-NEXT: vldrw.u32 q1, [r0], #32 142; CHECK-NEXT: vadd.f64 d1, d0, d1 143; CHECK-NEXT: vadd.f64 d0, d2, d3 144; CHECK-NEXT: vstrw.32 q0, [r1] 145; CHECK-NEXT: bx lr 146entry: 147 %l1 = load <4 x double>, ptr %src, align 4 148 %s1 = shufflevector <4 x double> %l1, <4 x double> undef, <2 x i32> <i32 0, i32 2> 149 %s2 = shufflevector <4 x double> %l1, <4 x double> undef, <2 x i32> <i32 1, i32 3> 150 %a = fadd <2 x double> %s1, %s2 151 store <2 x double> %a, ptr %dst 152 %ret = getelementptr inbounds <4 x double>, ptr %src, i32 1 153 ret ptr %ret 154} 155