xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-vcvt-float-to-fixed.ll (revision a500f7f48fdb64def09cb3b7487759b0972f2347) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi %s -o - -mattr=+mve.fp | FileCheck %s
3
4define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_1(<4 x float> %0) {
5; CHECK-LABEL: vcvt_i32_1:
6; CHECK:       @ %bb.0:
7; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #1
8; CHECK-NEXT:    bx lr
9  %2 = fmul fast <4 x float> %0, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>
10  %3 = fptosi <4 x float> %2 to <4 x i32>
11  ret <4 x i32> %3
12}
13
14define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_2(<4 x float> %0) {
15; CHECK-LABEL: vcvt_i32_2:
16; CHECK:       @ %bb.0:
17; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #2
18; CHECK-NEXT:    bx lr
19  %2 = fmul fast <4 x float> %0, <float 4.000000e+00, float 4.000000e+00, float 4.000000e+00, float 4.000000e+00>
20  %3 = fptosi <4 x float> %2 to <4 x i32>
21  ret <4 x i32> %3
22}
23
24define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_3(<4 x float> %0) {
25; CHECK-LABEL: vcvt_i32_3:
26; CHECK:       @ %bb.0:
27; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #3
28; CHECK-NEXT:    bx lr
29  %2 = fmul fast <4 x float> %0, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
30  %3 = fptosi <4 x float> %2 to <4 x i32>
31  ret <4 x i32> %3
32}
33
34define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_4(<4 x float> %0) {
35; CHECK-LABEL: vcvt_i32_4:
36; CHECK:       @ %bb.0:
37; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #4
38; CHECK-NEXT:    bx lr
39  %2 = fmul fast <4 x float> %0, <float 1.600000e+01, float 1.600000e+01, float 1.600000e+01, float 1.600000e+01>
40  %3 = fptosi <4 x float> %2 to <4 x i32>
41  ret <4 x i32> %3
42}
43
44define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_5(<4 x float> %0) {
45; CHECK-LABEL: vcvt_i32_5:
46; CHECK:       @ %bb.0:
47; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #5
48; CHECK-NEXT:    bx lr
49  %2 = fmul fast <4 x float> %0, <float 3.200000e+01, float 3.200000e+01, float 3.200000e+01, float 3.200000e+01>
50  %3 = fptosi <4 x float> %2 to <4 x i32>
51  ret <4 x i32> %3
52}
53
54define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_6(<4 x float> %0) {
55; CHECK-LABEL: vcvt_i32_6:
56; CHECK:       @ %bb.0:
57; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #6
58; CHECK-NEXT:    bx lr
59  %2 = fmul fast <4 x float> %0, <float 6.400000e+01, float 6.400000e+01, float 6.400000e+01, float 6.400000e+01>
60  %3 = fptosi <4 x float> %2 to <4 x i32>
61  ret <4 x i32> %3
62}
63
64define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_7(<4 x float> %0) {
65; CHECK-LABEL: vcvt_i32_7:
66; CHECK:       @ %bb.0:
67; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #7
68; CHECK-NEXT:    bx lr
69  %2 = fmul fast <4 x float> %0, <float 1.280000e+02, float 1.280000e+02, float 1.280000e+02, float 1.280000e+02>
70  %3 = fptosi <4 x float> %2 to <4 x i32>
71  ret <4 x i32> %3
72}
73
74define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_8(<4 x float> %0) {
75; CHECK-LABEL: vcvt_i32_8:
76; CHECK:       @ %bb.0:
77; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #8
78; CHECK-NEXT:    bx lr
79  %2 = fmul fast <4 x float> %0, <float 2.560000e+02, float 2.560000e+02, float 2.560000e+02, float 2.560000e+02>
80  %3 = fptosi <4 x float> %2 to <4 x i32>
81  ret <4 x i32> %3
82}
83
84define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_9(<4 x float> %0) {
85; CHECK-LABEL: vcvt_i32_9:
86; CHECK:       @ %bb.0:
87; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #9
88; CHECK-NEXT:    bx lr
89  %2 = fmul fast <4 x float> %0, <float 5.120000e+02, float 5.120000e+02, float 5.120000e+02, float 5.120000e+02>
90  %3 = fptosi <4 x float> %2 to <4 x i32>
91  ret <4 x i32> %3
92}
93
94define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_10(<4 x float> %0) {
95; CHECK-LABEL: vcvt_i32_10:
96; CHECK:       @ %bb.0:
97; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #10
98; CHECK-NEXT:    bx lr
99  %2 = fmul fast <4 x float> %0, <float 1.024000e+03, float 1.024000e+03, float 1.024000e+03, float 1.024000e+03>
100  %3 = fptosi <4 x float> %2 to <4 x i32>
101  ret <4 x i32> %3
102}
103
104define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_11(<4 x float> %0) {
105; CHECK-LABEL: vcvt_i32_11:
106; CHECK:       @ %bb.0:
107; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #11
108; CHECK-NEXT:    bx lr
109  %2 = fmul fast <4 x float> %0, <float 2.048000e+03, float 2.048000e+03, float 2.048000e+03, float 2.048000e+03>
110  %3 = fptosi <4 x float> %2 to <4 x i32>
111  ret <4 x i32> %3
112}
113
114define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_12(<4 x float> %0) {
115; CHECK-LABEL: vcvt_i32_12:
116; CHECK:       @ %bb.0:
117; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #12
118; CHECK-NEXT:    bx lr
119  %2 = fmul fast <4 x float> %0, <float 4.096000e+03, float 4.096000e+03, float 4.096000e+03, float 4.096000e+03>
120  %3 = fptosi <4 x float> %2 to <4 x i32>
121  ret <4 x i32> %3
122}
123
124define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_13(<4 x float> %0) {
125; CHECK-LABEL: vcvt_i32_13:
126; CHECK:       @ %bb.0:
127; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #13
128; CHECK-NEXT:    bx lr
129  %2 = fmul fast <4 x float> %0, <float 8.192000e+03, float 8.192000e+03, float 8.192000e+03, float 8.192000e+03>
130  %3 = fptosi <4 x float> %2 to <4 x i32>
131  ret <4 x i32> %3
132}
133
134define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_14(<4 x float> %0) {
135; CHECK-LABEL: vcvt_i32_14:
136; CHECK:       @ %bb.0:
137; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #14
138; CHECK-NEXT:    bx lr
139  %2 = fmul fast <4 x float> %0, <float 1.638400e+04, float 1.638400e+04, float 1.638400e+04, float 1.638400e+04>
140  %3 = fptosi <4 x float> %2 to <4 x i32>
141  ret <4 x i32> %3
142}
143
144define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_15(<4 x float> %0) {
145; CHECK-LABEL: vcvt_i32_15:
146; CHECK:       @ %bb.0:
147; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #15
148; CHECK-NEXT:    bx lr
149  %2 = fmul fast <4 x float> %0, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
150  %3 = fptosi <4 x float> %2 to <4 x i32>
151  ret <4 x i32> %3
152}
153
154define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_16(<4 x float> %0) {
155; CHECK-LABEL: vcvt_i32_16:
156; CHECK:       @ %bb.0:
157; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #16
158; CHECK-NEXT:    bx lr
159  %2 = fmul fast <4 x float> %0, <float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04>
160  %3 = fptosi <4 x float> %2 to <4 x i32>
161  ret <4 x i32> %3
162}
163
164define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_17(<4 x float> %0) {
165; CHECK-LABEL: vcvt_i32_17:
166; CHECK:       @ %bb.0:
167; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #17
168; CHECK-NEXT:    bx lr
169  %2 = fmul fast <4 x float> %0, <float 1.310720e+05, float 1.310720e+05, float 1.310720e+05, float 1.310720e+05>
170  %3 = fptosi <4 x float> %2 to <4 x i32>
171  ret <4 x i32> %3
172}
173
174define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_18(<4 x float> %0) {
175; CHECK-LABEL: vcvt_i32_18:
176; CHECK:       @ %bb.0:
177; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #18
178; CHECK-NEXT:    bx lr
179  %2 = fmul fast <4 x float> %0, <float 2.621440e+05, float 2.621440e+05, float 2.621440e+05, float 2.621440e+05>
180  %3 = fptosi <4 x float> %2 to <4 x i32>
181  ret <4 x i32> %3
182}
183
184define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_19(<4 x float> %0) {
185; CHECK-LABEL: vcvt_i32_19:
186; CHECK:       @ %bb.0:
187; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #19
188; CHECK-NEXT:    bx lr
189  %2 = fmul fast <4 x float> %0, <float 5.242880e+05, float 5.242880e+05, float 5.242880e+05, float 5.242880e+05>
190  %3 = fptosi <4 x float> %2 to <4 x i32>
191  ret <4 x i32> %3
192}
193
194define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_20(<4 x float> %0) {
195; CHECK-LABEL: vcvt_i32_20:
196; CHECK:       @ %bb.0:
197; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #20
198; CHECK-NEXT:    bx lr
199  %2 = fmul fast <4 x float> %0, <float 0x4130000000000000, float 0x4130000000000000, float 0x4130000000000000, float 0x4130000000000000>
200  %3 = fptosi <4 x float> %2 to <4 x i32>
201  ret <4 x i32> %3
202}
203
204define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_21(<4 x float> %0) {
205; CHECK-LABEL: vcvt_i32_21:
206; CHECK:       @ %bb.0:
207; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #21
208; CHECK-NEXT:    bx lr
209  %2 = fmul fast <4 x float> %0, <float 0x4140000000000000, float 0x4140000000000000, float 0x4140000000000000, float 0x4140000000000000>
210  %3 = fptosi <4 x float> %2 to <4 x i32>
211  ret <4 x i32> %3
212}
213
214define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_22(<4 x float> %0) {
215; CHECK-LABEL: vcvt_i32_22:
216; CHECK:       @ %bb.0:
217; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #22
218; CHECK-NEXT:    bx lr
219  %2 = fmul fast <4 x float> %0, <float 0x4150000000000000, float 0x4150000000000000, float 0x4150000000000000, float 0x4150000000000000>
220  %3 = fptosi <4 x float> %2 to <4 x i32>
221  ret <4 x i32> %3
222}
223
224define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_23(<4 x float> %0) {
225; CHECK-LABEL: vcvt_i32_23:
226; CHECK:       @ %bb.0:
227; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #23
228; CHECK-NEXT:    bx lr
229  %2 = fmul fast <4 x float> %0, <float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000>
230  %3 = fptosi <4 x float> %2 to <4 x i32>
231  ret <4 x i32> %3
232}
233
234define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_24(<4 x float> %0) {
235; CHECK-LABEL: vcvt_i32_24:
236; CHECK:       @ %bb.0:
237; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #24
238; CHECK-NEXT:    bx lr
239  %2 = fmul fast <4 x float> %0, <float 0x4170000000000000, float 0x4170000000000000, float 0x4170000000000000, float 0x4170000000000000>
240  %3 = fptosi <4 x float> %2 to <4 x i32>
241  ret <4 x i32> %3
242}
243
244define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_25(<4 x float> %0) {
245; CHECK-LABEL: vcvt_i32_25:
246; CHECK:       @ %bb.0:
247; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #25
248; CHECK-NEXT:    bx lr
249  %2 = fmul fast <4 x float> %0, <float 0x4180000000000000, float 0x4180000000000000, float 0x4180000000000000, float 0x4180000000000000>
250  %3 = fptosi <4 x float> %2 to <4 x i32>
251  ret <4 x i32> %3
252}
253
254define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_26(<4 x float> %0) {
255; CHECK-LABEL: vcvt_i32_26:
256; CHECK:       @ %bb.0:
257; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #26
258; CHECK-NEXT:    bx lr
259  %2 = fmul fast <4 x float> %0, <float 0x4190000000000000, float 0x4190000000000000, float 0x4190000000000000, float 0x4190000000000000>
260  %3 = fptosi <4 x float> %2 to <4 x i32>
261  ret <4 x i32> %3
262}
263
264define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_27(<4 x float> %0) {
265; CHECK-LABEL: vcvt_i32_27:
266; CHECK:       @ %bb.0:
267; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #27
268; CHECK-NEXT:    bx lr
269  %2 = fmul fast <4 x float> %0, <float 0x41A0000000000000, float 0x41A0000000000000, float 0x41A0000000000000, float 0x41A0000000000000>
270  %3 = fptosi <4 x float> %2 to <4 x i32>
271  ret <4 x i32> %3
272}
273
274define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_28(<4 x float> %0) {
275; CHECK-LABEL: vcvt_i32_28:
276; CHECK:       @ %bb.0:
277; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #28
278; CHECK-NEXT:    bx lr
279  %2 = fmul fast <4 x float> %0, <float 0x41B0000000000000, float 0x41B0000000000000, float 0x41B0000000000000, float 0x41B0000000000000>
280  %3 = fptosi <4 x float> %2 to <4 x i32>
281  ret <4 x i32> %3
282}
283
284define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_29(<4 x float> %0) {
285; CHECK-LABEL: vcvt_i32_29:
286; CHECK:       @ %bb.0:
287; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #29
288; CHECK-NEXT:    bx lr
289  %2 = fmul fast <4 x float> %0, <float 0x41C0000000000000, float 0x41C0000000000000, float 0x41C0000000000000, float 0x41C0000000000000>
290  %3 = fptosi <4 x float> %2 to <4 x i32>
291  ret <4 x i32> %3
292}
293
294define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_30(<4 x float> %0) {
295; CHECK-LABEL: vcvt_i32_30:
296; CHECK:       @ %bb.0:
297; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #30
298; CHECK-NEXT:    bx lr
299  %2 = fmul fast <4 x float> %0, <float 0x41D0000000000000, float 0x41D0000000000000, float 0x41D0000000000000, float 0x41D0000000000000>
300  %3 = fptosi <4 x float> %2 to <4 x i32>
301  ret <4 x i32> %3
302}
303
304define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_31(<4 x float> %0) {
305; CHECK-LABEL: vcvt_i32_31:
306; CHECK:       @ %bb.0:
307; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #31
308; CHECK-NEXT:    bx lr
309  %2 = fmul fast <4 x float> %0, <float 0x41E0000000000000, float 0x41E0000000000000, float 0x41E0000000000000, float 0x41E0000000000000>
310  %3 = fptosi <4 x float> %2 to <4 x i32>
311  ret <4 x i32> %3
312}
313
314define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_32(<4 x float> %0) {
315; CHECK-LABEL: vcvt_i32_32:
316; CHECK:       @ %bb.0:
317; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #32
318; CHECK-NEXT:    bx lr
319  %2 = fmul <4 x float> %0, <float 0x41F0000000000000, float 0x41F0000000000000, float 0x41F0000000000000, float 0x41F0000000000000>
320  %3 = fptosi <4 x float> %2 to <4 x i32>
321  ret <4 x i32> %3
322}
323
324define arm_aapcs_vfpcc <4 x i32> @vcvt_i32_33(<4 x float> %0) {
325; CHECK-LABEL: vcvt_i32_33:
326; CHECK:       @ %bb.0:
327; CHECK-NEXT:    vmov.i32 q1, #0x50000000
328; CHECK-NEXT:    vmul.f32 q0, q0, q1
329; CHECK-NEXT:    vcvt.s32.f32 q0, q0
330; CHECK-NEXT:    bx lr
331  %2 = fmul <4 x float> %0, <float 0x4200000000000000, float 0x4200000000000000, float 0x4200000000000000, float 0x4200000000000000>
332  %3 = fptosi <4 x float> %2 to <4 x i32>
333  ret <4 x i32> %3
334}
335
336define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_1(<8 x half> %0) {
337; CHECK-LABEL: vcvt_i16_1:
338; CHECK:       @ %bb.0:
339; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #1
340; CHECK-NEXT:    bx lr
341  %2 = fmul fast <8 x half> %0, <half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000>
342  %3 = fptosi <8 x half> %2 to <8 x i16>
343  ret <8 x i16> %3
344}
345
346define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_2(<8 x half> %0) {
347; CHECK-LABEL: vcvt_i16_2:
348; CHECK:       @ %bb.0:
349; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #2
350; CHECK-NEXT:    bx lr
351  %2 = fmul fast <8 x half> %0, <half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400>
352  %3 = fptosi <8 x half> %2 to <8 x i16>
353  ret <8 x i16> %3
354}
355
356define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_3(<8 x half> %0) {
357; CHECK-LABEL: vcvt_i16_3:
358; CHECK:       @ %bb.0:
359; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #3
360; CHECK-NEXT:    bx lr
361  %2 = fmul fast <8 x half> %0, <half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800>
362  %3 = fptosi <8 x half> %2 to <8 x i16>
363  ret <8 x i16> %3
364}
365
366define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_4(<8 x half> %0) {
367; CHECK-LABEL: vcvt_i16_4:
368; CHECK:       @ %bb.0:
369; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #4
370; CHECK-NEXT:    bx lr
371  %2 = fmul fast <8 x half> %0, <half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00>
372  %3 = fptosi <8 x half> %2 to <8 x i16>
373  ret <8 x i16> %3
374}
375
376define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_5(<8 x half> %0) {
377; CHECK-LABEL: vcvt_i16_5:
378; CHECK:       @ %bb.0:
379; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #5
380; CHECK-NEXT:    bx lr
381  %2 = fmul fast <8 x half> %0, <half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000>
382  %3 = fptosi <8 x half> %2 to <8 x i16>
383  ret <8 x i16> %3
384}
385
386define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_6(<8 x half> %0) {
387; CHECK-LABEL: vcvt_i16_6:
388; CHECK:       @ %bb.0:
389; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #6
390; CHECK-NEXT:    bx lr
391  %2 = fmul fast <8 x half> %0, <half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400>
392  %3 = fptosi <8 x half> %2 to <8 x i16>
393  ret <8 x i16> %3
394}
395
396define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_7(<8 x half> %0) {
397; CHECK-LABEL: vcvt_i16_7:
398; CHECK:       @ %bb.0:
399; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #7
400; CHECK-NEXT:    bx lr
401  %2 = fmul fast <8 x half> %0, <half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800>
402  %3 = fptosi <8 x half> %2 to <8 x i16>
403  ret <8 x i16> %3
404}
405
406define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_8(<8 x half> %0) {
407; CHECK-LABEL: vcvt_i16_8:
408; CHECK:       @ %bb.0:
409; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #8
410; CHECK-NEXT:    bx lr
411  %2 = fmul fast <8 x half> %0, <half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00>
412  %3 = fptosi <8 x half> %2 to <8 x i16>
413  ret <8 x i16> %3
414}
415
416define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_9(<8 x half> %0) {
417; CHECK-LABEL: vcvt_i16_9:
418; CHECK:       @ %bb.0:
419; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #9
420; CHECK-NEXT:    bx lr
421  %2 = fmul fast <8 x half> %0, <half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000>
422  %3 = fptosi <8 x half> %2 to <8 x i16>
423  ret <8 x i16> %3
424}
425
426define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_10(<8 x half> %0) {
427; CHECK-LABEL: vcvt_i16_10:
428; CHECK:       @ %bb.0:
429; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #10
430; CHECK-NEXT:    bx lr
431  %2 = fmul fast <8 x half> %0, <half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400>
432  %3 = fptosi <8 x half> %2 to <8 x i16>
433  ret <8 x i16> %3
434}
435
436define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_11(<8 x half> %0) {
437; CHECK-LABEL: vcvt_i16_11:
438; CHECK:       @ %bb.0:
439; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #11
440; CHECK-NEXT:    bx lr
441  %2 = fmul fast <8 x half> %0, <half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800>
442  %3 = fptosi <8 x half> %2 to <8 x i16>
443  ret <8 x i16> %3
444}
445
446define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_12(<8 x half> %0) {
447; CHECK-LABEL: vcvt_i16_12:
448; CHECK:       @ %bb.0:
449; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #12
450; CHECK-NEXT:    bx lr
451  %2 = fmul fast <8 x half> %0, <half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00>
452  %3 = fptosi <8 x half> %2 to <8 x i16>
453  ret <8 x i16> %3
454}
455
456define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_13(<8 x half> %0) {
457; CHECK-LABEL: vcvt_i16_13:
458; CHECK:       @ %bb.0:
459; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #13
460; CHECK-NEXT:    bx lr
461  %2 = fmul fast <8 x half> %0, <half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000>
462  %3 = fptosi <8 x half> %2 to <8 x i16>
463  ret <8 x i16> %3
464}
465
466define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_14(<8 x half> %0) {
467; CHECK-LABEL: vcvt_i16_14:
468; CHECK:       @ %bb.0:
469; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #14
470; CHECK-NEXT:    bx lr
471  %2 = fmul fast <8 x half> %0, <half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400>
472  %3 = fptosi <8 x half> %2 to <8 x i16>
473  ret <8 x i16> %3
474}
475
476define arm_aapcs_vfpcc <8 x i16> @vcvt_i16_15(<8 x half> %0) {
477; CHECK-LABEL: vcvt_i16_15:
478; CHECK:       @ %bb.0:
479; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #15
480; CHECK-NEXT:    bx lr
481  %2 = fmul fast <8 x half> %0, <half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800>
482  %3 = fptosi <8 x half> %2 to <8 x i16>
483  ret <8 x i16> %3
484}
485
486define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_1(<4 x float> %0) {
487; CHECK-LABEL: vcvt_u32_1:
488; CHECK:       @ %bb.0:
489; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #1
490; CHECK-NEXT:    bx lr
491  %2 = fmul fast <4 x float> %0, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>
492  %3 = fptoui <4 x float> %2 to <4 x i32>
493  ret <4 x i32> %3
494}
495
496define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_2(<4 x float> %0) {
497; CHECK-LABEL: vcvt_u32_2:
498; CHECK:       @ %bb.0:
499; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #2
500; CHECK-NEXT:    bx lr
501  %2 = fmul fast <4 x float> %0, <float 4.000000e+00, float 4.000000e+00, float 4.000000e+00, float 4.000000e+00>
502  %3 = fptoui <4 x float> %2 to <4 x i32>
503  ret <4 x i32> %3
504}
505
506define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_3(<4 x float> %0) {
507; CHECK-LABEL: vcvt_u32_3:
508; CHECK:       @ %bb.0:
509; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #3
510; CHECK-NEXT:    bx lr
511  %2 = fmul fast <4 x float> %0, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
512  %3 = fptoui <4 x float> %2 to <4 x i32>
513  ret <4 x i32> %3
514}
515
516define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_4(<4 x float> %0) {
517; CHECK-LABEL: vcvt_u32_4:
518; CHECK:       @ %bb.0:
519; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #4
520; CHECK-NEXT:    bx lr
521  %2 = fmul fast <4 x float> %0, <float 1.600000e+01, float 1.600000e+01, float 1.600000e+01, float 1.600000e+01>
522  %3 = fptoui <4 x float> %2 to <4 x i32>
523  ret <4 x i32> %3
524}
525
526define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_5(<4 x float> %0) {
527; CHECK-LABEL: vcvt_u32_5:
528; CHECK:       @ %bb.0:
529; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #5
530; CHECK-NEXT:    bx lr
531  %2 = fmul fast <4 x float> %0, <float 3.200000e+01, float 3.200000e+01, float 3.200000e+01, float 3.200000e+01>
532  %3 = fptoui <4 x float> %2 to <4 x i32>
533  ret <4 x i32> %3
534}
535
536define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_6(<4 x float> %0) {
537; CHECK-LABEL: vcvt_u32_6:
538; CHECK:       @ %bb.0:
539; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #6
540; CHECK-NEXT:    bx lr
541  %2 = fmul fast <4 x float> %0, <float 6.400000e+01, float 6.400000e+01, float 6.400000e+01, float 6.400000e+01>
542  %3 = fptoui <4 x float> %2 to <4 x i32>
543  ret <4 x i32> %3
544}
545
546define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_7(<4 x float> %0) {
547; CHECK-LABEL: vcvt_u32_7:
548; CHECK:       @ %bb.0:
549; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #7
550; CHECK-NEXT:    bx lr
551  %2 = fmul fast <4 x float> %0, <float 1.280000e+02, float 1.280000e+02, float 1.280000e+02, float 1.280000e+02>
552  %3 = fptoui <4 x float> %2 to <4 x i32>
553  ret <4 x i32> %3
554}
555
556define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_8(<4 x float> %0) {
557; CHECK-LABEL: vcvt_u32_8:
558; CHECK:       @ %bb.0:
559; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #8
560; CHECK-NEXT:    bx lr
561  %2 = fmul fast <4 x float> %0, <float 2.560000e+02, float 2.560000e+02, float 2.560000e+02, float 2.560000e+02>
562  %3 = fptoui <4 x float> %2 to <4 x i32>
563  ret <4 x i32> %3
564}
565
566define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_9(<4 x float> %0) {
567; CHECK-LABEL: vcvt_u32_9:
568; CHECK:       @ %bb.0:
569; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #9
570; CHECK-NEXT:    bx lr
571  %2 = fmul fast <4 x float> %0, <float 5.120000e+02, float 5.120000e+02, float 5.120000e+02, float 5.120000e+02>
572  %3 = fptoui <4 x float> %2 to <4 x i32>
573  ret <4 x i32> %3
574}
575
576define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_10(<4 x float> %0) {
577; CHECK-LABEL: vcvt_u32_10:
578; CHECK:       @ %bb.0:
579; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #10
580; CHECK-NEXT:    bx lr
581  %2 = fmul fast <4 x float> %0, <float 1.024000e+03, float 1.024000e+03, float 1.024000e+03, float 1.024000e+03>
582  %3 = fptoui <4 x float> %2 to <4 x i32>
583  ret <4 x i32> %3
584}
585
586define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_11(<4 x float> %0) {
587; CHECK-LABEL: vcvt_u32_11:
588; CHECK:       @ %bb.0:
589; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #11
590; CHECK-NEXT:    bx lr
591  %2 = fmul fast <4 x float> %0, <float 2.048000e+03, float 2.048000e+03, float 2.048000e+03, float 2.048000e+03>
592  %3 = fptoui <4 x float> %2 to <4 x i32>
593  ret <4 x i32> %3
594}
595
596define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_12(<4 x float> %0) {
597; CHECK-LABEL: vcvt_u32_12:
598; CHECK:       @ %bb.0:
599; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #12
600; CHECK-NEXT:    bx lr
601  %2 = fmul fast <4 x float> %0, <float 4.096000e+03, float 4.096000e+03, float 4.096000e+03, float 4.096000e+03>
602  %3 = fptoui <4 x float> %2 to <4 x i32>
603  ret <4 x i32> %3
604}
605
606define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_13(<4 x float> %0) {
607; CHECK-LABEL: vcvt_u32_13:
608; CHECK:       @ %bb.0:
609; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #13
610; CHECK-NEXT:    bx lr
611  %2 = fmul fast <4 x float> %0, <float 8.192000e+03, float 8.192000e+03, float 8.192000e+03, float 8.192000e+03>
612  %3 = fptoui <4 x float> %2 to <4 x i32>
613  ret <4 x i32> %3
614}
615
616define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_14(<4 x float> %0) {
617; CHECK-LABEL: vcvt_u32_14:
618; CHECK:       @ %bb.0:
619; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #14
620; CHECK-NEXT:    bx lr
621  %2 = fmul fast <4 x float> %0, <float 1.638400e+04, float 1.638400e+04, float 1.638400e+04, float 1.638400e+04>
622  %3 = fptoui <4 x float> %2 to <4 x i32>
623  ret <4 x i32> %3
624}
625
626define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_15(<4 x float> %0) {
627; CHECK-LABEL: vcvt_u32_15:
628; CHECK:       @ %bb.0:
629; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #15
630; CHECK-NEXT:    bx lr
631  %2 = fmul fast <4 x float> %0, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
632  %3 = fptoui <4 x float> %2 to <4 x i32>
633  ret <4 x i32> %3
634}
635
636define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_16(<4 x float> %0) {
637; CHECK-LABEL: vcvt_u32_16:
638; CHECK:       @ %bb.0:
639; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #16
640; CHECK-NEXT:    bx lr
641  %2 = fmul fast <4 x float> %0, <float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04>
642  %3 = fptoui <4 x float> %2 to <4 x i32>
643  ret <4 x i32> %3
644}
645
646define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_17(<4 x float> %0) {
647; CHECK-LABEL: vcvt_u32_17:
648; CHECK:       @ %bb.0:
649; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #17
650; CHECK-NEXT:    bx lr
651  %2 = fmul fast <4 x float> %0, <float 1.310720e+05, float 1.310720e+05, float 1.310720e+05, float 1.310720e+05>
652  %3 = fptoui <4 x float> %2 to <4 x i32>
653  ret <4 x i32> %3
654}
655
656define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_18(<4 x float> %0) {
657; CHECK-LABEL: vcvt_u32_18:
658; CHECK:       @ %bb.0:
659; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #18
660; CHECK-NEXT:    bx lr
661  %2 = fmul fast <4 x float> %0, <float 2.621440e+05, float 2.621440e+05, float 2.621440e+05, float 2.621440e+05>
662  %3 = fptoui <4 x float> %2 to <4 x i32>
663  ret <4 x i32> %3
664}
665
666define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_19(<4 x float> %0) {
667; CHECK-LABEL: vcvt_u32_19:
668; CHECK:       @ %bb.0:
669; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #19
670; CHECK-NEXT:    bx lr
671  %2 = fmul fast <4 x float> %0, <float 5.242880e+05, float 5.242880e+05, float 5.242880e+05, float 5.242880e+05>
672  %3 = fptoui <4 x float> %2 to <4 x i32>
673  ret <4 x i32> %3
674}
675
676define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_20(<4 x float> %0) {
677; CHECK-LABEL: vcvt_u32_20:
678; CHECK:       @ %bb.0:
679; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #20
680; CHECK-NEXT:    bx lr
681  %2 = fmul fast <4 x float> %0, <float 0x4130000000000000, float 0x4130000000000000, float 0x4130000000000000, float 0x4130000000000000>
682  %3 = fptoui <4 x float> %2 to <4 x i32>
683  ret <4 x i32> %3
684}
685
686define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_21(<4 x float> %0) {
687; CHECK-LABEL: vcvt_u32_21:
688; CHECK:       @ %bb.0:
689; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #21
690; CHECK-NEXT:    bx lr
691  %2 = fmul fast <4 x float> %0, <float 0x4140000000000000, float 0x4140000000000000, float 0x4140000000000000, float 0x4140000000000000>
692  %3 = fptoui <4 x float> %2 to <4 x i32>
693  ret <4 x i32> %3
694}
695
696define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_22(<4 x float> %0) {
697; CHECK-LABEL: vcvt_u32_22:
698; CHECK:       @ %bb.0:
699; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #22
700; CHECK-NEXT:    bx lr
701  %2 = fmul fast <4 x float> %0, <float 0x4150000000000000, float 0x4150000000000000, float 0x4150000000000000, float 0x4150000000000000>
702  %3 = fptoui <4 x float> %2 to <4 x i32>
703  ret <4 x i32> %3
704}
705
706define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_23(<4 x float> %0) {
707; CHECK-LABEL: vcvt_u32_23:
708; CHECK:       @ %bb.0:
709; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #23
710; CHECK-NEXT:    bx lr
711  %2 = fmul fast <4 x float> %0, <float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000>
712  %3 = fptoui <4 x float> %2 to <4 x i32>
713  ret <4 x i32> %3
714}
715
716define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_24(<4 x float> %0) {
717; CHECK-LABEL: vcvt_u32_24:
718; CHECK:       @ %bb.0:
719; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #24
720; CHECK-NEXT:    bx lr
721  %2 = fmul fast <4 x float> %0, <float 0x4170000000000000, float 0x4170000000000000, float 0x4170000000000000, float 0x4170000000000000>
722  %3 = fptoui <4 x float> %2 to <4 x i32>
723  ret <4 x i32> %3
724}
725
726define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_25(<4 x float> %0) {
727; CHECK-LABEL: vcvt_u32_25:
728; CHECK:       @ %bb.0:
729; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #25
730; CHECK-NEXT:    bx lr
731  %2 = fmul fast <4 x float> %0, <float 0x4180000000000000, float 0x4180000000000000, float 0x4180000000000000, float 0x4180000000000000>
732  %3 = fptoui <4 x float> %2 to <4 x i32>
733  ret <4 x i32> %3
734}
735
736define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_26(<4 x float> %0) {
737; CHECK-LABEL: vcvt_u32_26:
738; CHECK:       @ %bb.0:
739; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #26
740; CHECK-NEXT:    bx lr
741  %2 = fmul fast <4 x float> %0, <float 0x4190000000000000, float 0x4190000000000000, float 0x4190000000000000, float 0x4190000000000000>
742  %3 = fptoui <4 x float> %2 to <4 x i32>
743  ret <4 x i32> %3
744}
745
746define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_27(<4 x float> %0) {
747; CHECK-LABEL: vcvt_u32_27:
748; CHECK:       @ %bb.0:
749; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #27
750; CHECK-NEXT:    bx lr
751  %2 = fmul fast <4 x float> %0, <float 0x41A0000000000000, float 0x41A0000000000000, float 0x41A0000000000000, float 0x41A0000000000000>
752  %3 = fptoui <4 x float> %2 to <4 x i32>
753  ret <4 x i32> %3
754}
755
756define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_28(<4 x float> %0) {
757; CHECK-LABEL: vcvt_u32_28:
758; CHECK:       @ %bb.0:
759; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #28
760; CHECK-NEXT:    bx lr
761  %2 = fmul fast <4 x float> %0, <float 0x41B0000000000000, float 0x41B0000000000000, float 0x41B0000000000000, float 0x41B0000000000000>
762  %3 = fptoui <4 x float> %2 to <4 x i32>
763  ret <4 x i32> %3
764}
765
766define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_29(<4 x float> %0) {
767; CHECK-LABEL: vcvt_u32_29:
768; CHECK:       @ %bb.0:
769; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #29
770; CHECK-NEXT:    bx lr
771  %2 = fmul fast <4 x float> %0, <float 0x41C0000000000000, float 0x41C0000000000000, float 0x41C0000000000000, float 0x41C0000000000000>
772  %3 = fptoui <4 x float> %2 to <4 x i32>
773  ret <4 x i32> %3
774}
775
776define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_30(<4 x float> %0) {
777; CHECK-LABEL: vcvt_u32_30:
778; CHECK:       @ %bb.0:
779; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #30
780; CHECK-NEXT:    bx lr
781  %2 = fmul fast <4 x float> %0, <float 0x41D0000000000000, float 0x41D0000000000000, float 0x41D0000000000000, float 0x41D0000000000000>
782  %3 = fptoui <4 x float> %2 to <4 x i32>
783  ret <4 x i32> %3
784}
785
786define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_31(<4 x float> %0) {
787; CHECK-LABEL: vcvt_u32_31:
788; CHECK:       @ %bb.0:
789; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #31
790; CHECK-NEXT:    bx lr
791  %2 = fmul fast <4 x float> %0, <float 0x41E0000000000000, float 0x41E0000000000000, float 0x41E0000000000000, float 0x41E0000000000000>
792  %3 = fptoui <4 x float> %2 to <4 x i32>
793  ret <4 x i32> %3
794}
795
796define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_32(<4 x float> %0) {
797; CHECK-LABEL: vcvt_u32_32:
798; CHECK:       @ %bb.0:
799; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #32
800; CHECK-NEXT:    bx lr
801  %2 = fmul <4 x float> %0, <float 0x41F0000000000000, float 0x41F0000000000000, float 0x41F0000000000000, float 0x41F0000000000000>
802  %3 = fptoui <4 x float> %2 to <4 x i32>
803  ret <4 x i32> %3
804}
805
806define arm_aapcs_vfpcc <4 x i32> @vcvt_u32_33(<4 x float> %0) {
807; CHECK-LABEL: vcvt_u32_33:
808; CHECK:       @ %bb.0:
809; CHECK-NEXT:    vmov.i32 q1, #0x50000000
810; CHECK-NEXT:    vmul.f32 q0, q0, q1
811; CHECK-NEXT:    vcvt.u32.f32 q0, q0
812; CHECK-NEXT:    bx lr
813  %2 = fmul <4 x float> %0, <float 0x4200000000000000, float 0x4200000000000000, float 0x4200000000000000, float 0x4200000000000000>
814  %3 = fptoui <4 x float> %2 to <4 x i32>
815  ret <4 x i32> %3
816}
817
818define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_1(<8 x half> %0) {
819; CHECK-LABEL: vcvt_u16_1:
820; CHECK:       @ %bb.0:
821; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #1
822; CHECK-NEXT:    bx lr
823  %2 = fmul fast <8 x half> %0, <half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000>
824  %3 = fptoui <8 x half> %2 to <8 x i16>
825  ret <8 x i16> %3
826}
827
828define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_2(<8 x half> %0) {
829; CHECK-LABEL: vcvt_u16_2:
830; CHECK:       @ %bb.0:
831; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #2
832; CHECK-NEXT:    bx lr
833  %2 = fmul fast <8 x half> %0, <half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400, half 0xH4400>
834  %3 = fptoui <8 x half> %2 to <8 x i16>
835  ret <8 x i16> %3
836}
837
838define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_3(<8 x half> %0) {
839; CHECK-LABEL: vcvt_u16_3:
840; CHECK:       @ %bb.0:
841; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #3
842; CHECK-NEXT:    bx lr
843  %2 = fmul fast <8 x half> %0, <half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800, half 0xH4800>
844  %3 = fptoui <8 x half> %2 to <8 x i16>
845  ret <8 x i16> %3
846}
847
848define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_4(<8 x half> %0) {
849; CHECK-LABEL: vcvt_u16_4:
850; CHECK:       @ %bb.0:
851; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #4
852; CHECK-NEXT:    bx lr
853  %2 = fmul fast <8 x half> %0, <half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00, half 0xH4C00>
854  %3 = fptoui <8 x half> %2 to <8 x i16>
855  ret <8 x i16> %3
856}
857
858define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_5(<8 x half> %0) {
859; CHECK-LABEL: vcvt_u16_5:
860; CHECK:       @ %bb.0:
861; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #5
862; CHECK-NEXT:    bx lr
863  %2 = fmul fast <8 x half> %0, <half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000, half 0xH5000>
864  %3 = fptoui <8 x half> %2 to <8 x i16>
865  ret <8 x i16> %3
866}
867
868define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_6(<8 x half> %0) {
869; CHECK-LABEL: vcvt_u16_6:
870; CHECK:       @ %bb.0:
871; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #6
872; CHECK-NEXT:    bx lr
873  %2 = fmul fast <8 x half> %0, <half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400>
874  %3 = fptoui <8 x half> %2 to <8 x i16>
875  ret <8 x i16> %3
876}
877
878define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_7(<8 x half> %0) {
879; CHECK-LABEL: vcvt_u16_7:
880; CHECK:       @ %bb.0:
881; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #7
882; CHECK-NEXT:    bx lr
883  %2 = fmul fast <8 x half> %0, <half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800>
884  %3 = fptoui <8 x half> %2 to <8 x i16>
885  ret <8 x i16> %3
886}
887
888define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_8(<8 x half> %0) {
889; CHECK-LABEL: vcvt_u16_8:
890; CHECK:       @ %bb.0:
891; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #8
892; CHECK-NEXT:    bx lr
893  %2 = fmul fast <8 x half> %0, <half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00, half 0xH5C00>
894  %3 = fptoui <8 x half> %2 to <8 x i16>
895  ret <8 x i16> %3
896}
897
898define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_9(<8 x half> %0) {
899; CHECK-LABEL: vcvt_u16_9:
900; CHECK:       @ %bb.0:
901; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #9
902; CHECK-NEXT:    bx lr
903  %2 = fmul fast <8 x half> %0, <half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000, half 0xH6000>
904  %3 = fptoui <8 x half> %2 to <8 x i16>
905  ret <8 x i16> %3
906}
907
908define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_10(<8 x half> %0) {
909; CHECK-LABEL: vcvt_u16_10:
910; CHECK:       @ %bb.0:
911; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #10
912; CHECK-NEXT:    bx lr
913  %2 = fmul fast <8 x half> %0, <half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400, half 0xH6400>
914  %3 = fptoui <8 x half> %2 to <8 x i16>
915  ret <8 x i16> %3
916}
917
918define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_11(<8 x half> %0) {
919; CHECK-LABEL: vcvt_u16_11:
920; CHECK:       @ %bb.0:
921; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #11
922; CHECK-NEXT:    bx lr
923  %2 = fmul fast <8 x half> %0, <half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800, half 0xH6800>
924  %3 = fptoui <8 x half> %2 to <8 x i16>
925  ret <8 x i16> %3
926}
927
928define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_12(<8 x half> %0) {
929; CHECK-LABEL: vcvt_u16_12:
930; CHECK:       @ %bb.0:
931; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #12
932; CHECK-NEXT:    bx lr
933  %2 = fmul fast <8 x half> %0, <half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00, half 0xH6C00>
934  %3 = fptoui <8 x half> %2 to <8 x i16>
935  ret <8 x i16> %3
936}
937
938define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_13(<8 x half> %0) {
939; CHECK-LABEL: vcvt_u16_13:
940; CHECK:       @ %bb.0:
941; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #13
942; CHECK-NEXT:    bx lr
943  %2 = fmul fast <8 x half> %0, <half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000>
944  %3 = fptoui <8 x half> %2 to <8 x i16>
945  ret <8 x i16> %3
946}
947
948define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_14(<8 x half> %0) {
949; CHECK-LABEL: vcvt_u16_14:
950; CHECK:       @ %bb.0:
951; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #14
952; CHECK-NEXT:    bx lr
953  %2 = fmul fast <8 x half> %0, <half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400, half 0xH7400>
954  %3 = fptoui <8 x half> %2 to <8 x i16>
955  ret <8 x i16> %3
956}
957
958define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_15(<8 x half> %0) {
959; CHECK-LABEL: vcvt_u16_15:
960; CHECK:       @ %bb.0:
961; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #15
962; CHECK-NEXT:    bx lr
963  %2 = fmul fast <8 x half> %0, <half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800>
964  %3 = fptoui <8 x half> %2 to <8 x i16>
965  ret <8 x i16> %3
966}
967
968define arm_aapcs_vfpcc <8 x i16> @vcvt_u16_inf(<8 x half> %0) {
969; CHECK-LABEL: vcvt_u16_inf:
970; CHECK:       @ %bb.0:
971; CHECK-NEXT:    vmov.i16 q1, #0x7800
972; CHECK-NEXT:    vmul.f16 q0, q0, q1
973; CHECK-NEXT:    vcvt.u16.f16 q0, q0
974; CHECK-NEXT:    bx lr
975  %2 = fmul <8 x half> %0, <half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800>
976  %3 = fptoui <8 x half> %2 to <8 x i16>
977  ret <8 x i16> %3
978}
979
980define arm_aapcs_vfpcc <8 x i16> @vcvt_s16_inf(<8 x half> %0) {
981; CHECK-LABEL: vcvt_s16_inf:
982; CHECK:       @ %bb.0:
983; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #15
984; CHECK-NEXT:    bx lr
985  %2 = fmul <8 x half> %0, <half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800, half 0xH7800>
986  %3 = fptosi <8 x half> %2 to <8 x i16>
987  ret <8 x i16> %3
988}
989
990
991define arm_aapcs_vfpcc <4 x i32> @vcvt_bad_imm(<4 x float> %0) {
992; CHECK-LABEL: vcvt_bad_imm:
993; CHECK:       @ %bb.0:
994; CHECK-NEXT:    movw r0, #2048
995; CHECK-NEXT:    movt r0, #15104
996; CHECK-NEXT:    vmul.f32 q0, q0, r0
997; CHECK-NEXT:    vcvt.s32.f32 q0, q0
998; CHECK-NEXT:    bx lr
999  %2 = fmul <4 x float> %0, <float 0x3F60010000000000, float 0x3F60010000000000, float 0x3F60010000000000, float 0x3F60010000000000>
1000  %3 = fptosi <4 x float> %2 to <4 x i32>
1001  ret <4 x i32> %3
1002}
1003
1004define arm_aapcs_vfpcc <4 x i32> @vcvt_negative(<4 x float> %0) {
1005; CHECK-LABEL: vcvt_negative:
1006; CHECK:       @ %bb.0:
1007; CHECK-NEXT:    vmov.i32 q1, #0xb8000000
1008; CHECK-NEXT:    vmul.f32 q0, q0, q1
1009; CHECK-NEXT:    vcvt.s32.f32 q0, q0
1010; CHECK-NEXT:    bx lr
1011  %2 = fmul <4 x float> %0, <float 0xBF00000000000000, float 0xBF00000000000000, float 0xBF00000000000000, float 0xBF00000000000000>
1012  %3 = fptosi <4 x float> %2 to <4 x i32>
1013  ret <4 x i32> %3
1014}
1015
1016define arm_aapcs_vfpcc <4 x i32> @vcvt_negative2(<4 x float> %0) {
1017; CHECK-LABEL: vcvt_negative2:
1018; CHECK:       @ %bb.0:
1019; CHECK-NEXT:    vmov.i32 q1, #0xb0000000
1020; CHECK-NEXT:    vmul.f32 q0, q0, q1
1021; CHECK-NEXT:    vcvt.s32.f32 q0, q0
1022; CHECK-NEXT:    bx lr
1023  %2 = fmul <4 x float> %0, <float 0xBE00000000000000, float 0xBE00000000000000, float 0xBE00000000000000, float 0xBE00000000000000>
1024  %3 = fptosi <4 x float> %2 to <4 x i32>
1025  ret <4 x i32> %3
1026}
1027
1028
1029
1030define arm_aapcs_vfpcc <8 x i16> @vcvt_sat_s16_1(<8 x half> %0) {
1031; CHECK-LABEL: vcvt_sat_s16_1:
1032; CHECK:       @ %bb.0:
1033; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #1
1034; CHECK-NEXT:    bx lr
1035  %2 = fmul fast <8 x half> %0, <half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000>
1036  %3 = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2)
1037  ret <8 x i16> %3
1038}
1039
1040define arm_aapcs_vfpcc <8 x i16> @vcvt_sat_u16_1(<8 x half> %0) {
1041; CHECK-LABEL: vcvt_sat_u16_1:
1042; CHECK:       @ %bb.0:
1043; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #1
1044; CHECK-NEXT:    bx lr
1045  %2 = fmul fast <8 x half> %0, <half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000>
1046  %3 = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2)
1047  ret <8 x i16> %3
1048}
1049
1050define arm_aapcs_vfpcc <8 x i16> @vcvt_sat_s16_6(<8 x half> %0) {
1051; CHECK-LABEL: vcvt_sat_s16_6:
1052; CHECK:       @ %bb.0:
1053; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #6
1054; CHECK-NEXT:    bx lr
1055  %2 = fmul fast <8 x half> %0, <half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400>
1056  %3 = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2)
1057  ret <8 x i16> %3
1058}
1059
1060define arm_aapcs_vfpcc <8 x i16> @vcvt_sat_u16_7(<8 x half> %0) {
1061; CHECK-LABEL: vcvt_sat_u16_7:
1062; CHECK:       @ %bb.0:
1063; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #7
1064; CHECK-NEXT:    bx lr
1065  %2 = fmul fast <8 x half> %0, <half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800>
1066  %3 = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2)
1067  ret <8 x i16> %3
1068}
1069
1070
1071define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_s32_1(<4 x float> %0) {
1072; CHECK-LABEL: vcvt_sat_s32_1:
1073; CHECK:       @ %bb.0:
1074; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #1
1075; CHECK-NEXT:    bx lr
1076  %2 = fmul fast <4 x float> %0, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>
1077  %3 = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %2)
1078  ret <4 x i32> %3
1079}
1080
1081define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_u32_1(<4 x float> %0) {
1082; CHECK-LABEL: vcvt_sat_u32_1:
1083; CHECK:       @ %bb.0:
1084; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #1
1085; CHECK-NEXT:    bx lr
1086  %2 = fmul fast <4 x float> %0, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>
1087  %3 = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> %2)
1088  ret <4 x i32> %3
1089}
1090
1091define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_u32_11(<4 x float> %0) {
1092; CHECK-LABEL: vcvt_sat_u32_11:
1093; CHECK:       @ %bb.0:
1094; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #11
1095; CHECK-NEXT:    bx lr
1096  %2 = fmul fast <4 x float> %0, <float 2.048000e+03, float 2.048000e+03, float 2.048000e+03, float 2.048000e+03>
1097  %3 = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %2)
1098  ret <4 x i32> %3
1099}
1100
1101define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_u32_7(<4 x float> %0) {
1102; CHECK-LABEL: vcvt_sat_u32_7:
1103; CHECK:       @ %bb.0:
1104; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #23
1105; CHECK-NEXT:    bx lr
1106  %2 = fmul fast <4 x float> %0, <float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000>
1107  %3 = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> %2)
1108  ret <4 x i32> %3
1109}
1110
1111define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_u32_7_24(<4 x float> %0) {
1112; CHECK-LABEL: vcvt_sat_u32_7_24:
1113; CHECK:       @ %bb.0:
1114; CHECK-NEXT:    vmov.i32 q1, #0xffffff
1115; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #23
1116; CHECK-NEXT:    vmin.u32 q0, q0, q1
1117; CHECK-NEXT:    bx lr
1118  %2 = fmul fast <4 x float> %0, <float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000>
1119  %3 = call <4 x i24> @llvm.fptoui.sat.v4i24.v4f32(<4 x float> %2)
1120  %4 = zext <4 x i24> %3 to <4 x i32>
1121  ret <4 x i32> %4
1122}
1123
1124declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float>)
1125declare <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float>)
1126declare <4 x i24> @llvm.fptoui.sat.v4i24.v4f32(<4 x float>)
1127declare <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half>)
1128declare <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half>)
1129