xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-vcvt-fixed-to-float.ll (revision 24d76419d6b7a3191ec1f4bfc33a640e716f11c8) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi %s -o - -mattr=+mve.fp | FileCheck %s
3
4define arm_aapcs_vfpcc <4 x float> @vcvt_i32_1(<4 x i32> %0) {
5; CHECK-LABEL: vcvt_i32_1:
6; CHECK:       @ %bb.0:
7; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #1
8; CHECK-NEXT:    bx lr
9  %2 = sitofp <4 x i32> %0 to <4 x float>
10  %3 = fmul <4 x float> %2, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01>
11  ret <4 x float> %3
12}
13
14define arm_aapcs_vfpcc <4 x float> @vcvt_i32_2(<4 x i32> %0) {
15; CHECK-LABEL: vcvt_i32_2:
16; CHECK:       @ %bb.0:
17; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #2
18; CHECK-NEXT:    bx lr
19  %2 = sitofp <4 x i32> %0 to <4 x float>
20  %3 = fmul <4 x float> %2, <float 2.500000e-01, float 2.500000e-01, float 2.500000e-01, float 2.500000e-01>
21  ret <4 x float> %3
22}
23
24define arm_aapcs_vfpcc <4 x float> @vcvt_i32_3(<4 x i32> %0) {
25; CHECK-LABEL: vcvt_i32_3:
26; CHECK:       @ %bb.0:
27; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #3
28; CHECK-NEXT:    bx lr
29  %2 = sitofp <4 x i32> %0 to <4 x float>
30  %3 = fmul <4 x float> %2, <float 1.250000e-01, float 1.250000e-01, float 1.250000e-01, float 1.250000e-01>
31  ret <4 x float> %3
32}
33
34define arm_aapcs_vfpcc <4 x float> @vcvt_i32_4(<4 x i32> %0) {
35; CHECK-LABEL: vcvt_i32_4:
36; CHECK:       @ %bb.0:
37; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #4
38; CHECK-NEXT:    bx lr
39  %2 = sitofp <4 x i32> %0 to <4 x float>
40  %3 = fmul <4 x float> %2, <float 6.250000e-02, float 6.250000e-02, float 6.250000e-02, float 6.250000e-02>
41  ret <4 x float> %3
42}
43
44define arm_aapcs_vfpcc <4 x float> @vcvt_i32_5(<4 x i32> %0) {
45; CHECK-LABEL: vcvt_i32_5:
46; CHECK:       @ %bb.0:
47; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #5
48; CHECK-NEXT:    bx lr
49  %2 = sitofp <4 x i32> %0 to <4 x float>
50  %3 = fmul <4 x float> %2, <float 3.125000e-02, float 3.125000e-02, float 3.125000e-02, float 3.125000e-02>
51  ret <4 x float> %3
52}
53
54define arm_aapcs_vfpcc <4 x float> @vcvt_i32_6(<4 x i32> %0) {
55; CHECK-LABEL: vcvt_i32_6:
56; CHECK:       @ %bb.0:
57; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #6
58; CHECK-NEXT:    bx lr
59  %2 = sitofp <4 x i32> %0 to <4 x float>
60  %3 = fmul <4 x float> %2, <float 1.562500e-02, float 1.562500e-02, float 1.562500e-02, float 1.562500e-02>
61  ret <4 x float> %3
62}
63
64define arm_aapcs_vfpcc <4 x float> @vcvt_i32_7(<4 x i32> %0) {
65; CHECK-LABEL: vcvt_i32_7:
66; CHECK:       @ %bb.0:
67; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #7
68; CHECK-NEXT:    bx lr
69  %2 = sitofp <4 x i32> %0 to <4 x float>
70  %3 = fmul <4 x float> %2, <float 7.812500e-03, float 7.812500e-03, float 7.812500e-03, float 7.812500e-03>
71  ret <4 x float> %3
72}
73
74define arm_aapcs_vfpcc <4 x float> @vcvt_i32_8(<4 x i32> %0) {
75; CHECK-LABEL: vcvt_i32_8:
76; CHECK:       @ %bb.0:
77; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #8
78; CHECK-NEXT:    bx lr
79  %2 = sitofp <4 x i32> %0 to <4 x float>
80  %3 = fmul <4 x float> %2, <float 3.906250e-03, float 3.906250e-03, float 3.906250e-03, float 3.906250e-03>
81  ret <4 x float> %3
82}
83
84define arm_aapcs_vfpcc <4 x float> @vcvt_i32_9(<4 x i32> %0) {
85; CHECK-LABEL: vcvt_i32_9:
86; CHECK:       @ %bb.0:
87; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #9
88; CHECK-NEXT:    bx lr
89  %2 = sitofp <4 x i32> %0 to <4 x float>
90  %3 = fmul <4 x float> %2, <float 0x3F60000000000000, float 0x3F60000000000000, float 0x3F60000000000000, float 0x3F60000000000000>
91  ret <4 x float> %3
92}
93
94define arm_aapcs_vfpcc <4 x float> @vcvt_i32_10(<4 x i32> %0) {
95; CHECK-LABEL: vcvt_i32_10:
96; CHECK:       @ %bb.0:
97; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #10
98; CHECK-NEXT:    bx lr
99  %2 = sitofp <4 x i32> %0 to <4 x float>
100  %3 = fmul <4 x float> %2, <float 0x3F50000000000000, float 0x3F50000000000000, float 0x3F50000000000000, float 0x3F50000000000000>
101  ret <4 x float> %3
102}
103
104define arm_aapcs_vfpcc <4 x float> @vcvt_i32_11(<4 x i32> %0) {
105; CHECK-LABEL: vcvt_i32_11:
106; CHECK:       @ %bb.0:
107; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #11
108; CHECK-NEXT:    bx lr
109  %2 = sitofp <4 x i32> %0 to <4 x float>
110  %3 = fmul <4 x float> %2, <float 0x3F40000000000000, float 0x3F40000000000000, float 0x3F40000000000000, float 0x3F40000000000000>
111  ret <4 x float> %3
112}
113
114define arm_aapcs_vfpcc <4 x float> @vcvt_i32_12(<4 x i32> %0) {
115; CHECK-LABEL: vcvt_i32_12:
116; CHECK:       @ %bb.0:
117; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #12
118; CHECK-NEXT:    bx lr
119  %2 = sitofp <4 x i32> %0 to <4 x float>
120  %3 = fmul <4 x float> %2, <float 0x3F30000000000000, float 0x3F30000000000000, float 0x3F30000000000000, float 0x3F30000000000000>
121  ret <4 x float> %3
122}
123
124define arm_aapcs_vfpcc <4 x float> @vcvt_i32_13(<4 x i32> %0) {
125; CHECK-LABEL: vcvt_i32_13:
126; CHECK:       @ %bb.0:
127; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #13
128; CHECK-NEXT:    bx lr
129  %2 = sitofp <4 x i32> %0 to <4 x float>
130  %3 = fmul <4 x float> %2, <float 0x3F20000000000000, float 0x3F20000000000000, float 0x3F20000000000000, float 0x3F20000000000000>
131  ret <4 x float> %3
132}
133
134define arm_aapcs_vfpcc <4 x float> @vcvt_i32_14(<4 x i32> %0)  {
135; CHECK-LABEL: vcvt_i32_14:
136; CHECK:       @ %bb.0:
137; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #14
138; CHECK-NEXT:    bx lr
139  %2 = sitofp <4 x i32> %0 to <4 x float>
140  %3 = fmul <4 x float> %2, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
141  ret <4 x float> %3
142}
143
144define arm_aapcs_vfpcc <4 x float> @vcvt_i32_15(<4 x i32> %0) {
145; CHECK-LABEL: vcvt_i32_15:
146; CHECK:       @ %bb.0:
147; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #15
148; CHECK-NEXT:    bx lr
149  %2 = sitofp <4 x i32> %0 to <4 x float>
150  %3 = fmul <4 x float> %2, <float 0x3F00000000000000, float 0x3F00000000000000, float 0x3F00000000000000, float 0x3F00000000000000>
151  ret <4 x float> %3
152}
153
154define arm_aapcs_vfpcc <4 x float> @vcvt_i32_16(<4 x i32> %0) {
155; CHECK-LABEL: vcvt_i32_16:
156; CHECK:       @ %bb.0:
157; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #16
158; CHECK-NEXT:    bx lr
159  %2 = sitofp <4 x i32> %0 to <4 x float>
160  %3 = fmul <4 x float> %2, <float 0x3EF0000000000000, float 0x3EF0000000000000, float 0x3EF0000000000000, float 0x3EF0000000000000>
161  ret <4 x float> %3
162}
163
164define arm_aapcs_vfpcc <4 x float> @vcvt_i32_17(<4 x i32> %0) {
165; CHECK-LABEL: vcvt_i32_17:
166; CHECK:       @ %bb.0:
167; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #17
168; CHECK-NEXT:    bx lr
169  %2 = sitofp <4 x i32> %0 to <4 x float>
170  %3 = fmul <4 x float> %2, <float 0x3EE0000000000000, float 0x3EE0000000000000, float 0x3EE0000000000000, float 0x3EE0000000000000>
171  ret <4 x float> %3
172}
173
174define arm_aapcs_vfpcc <4 x float> @vcvt_i32_18(<4 x i32> %0) {
175; CHECK-LABEL: vcvt_i32_18:
176; CHECK:       @ %bb.0:
177; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #18
178; CHECK-NEXT:    bx lr
179  %2 = sitofp <4 x i32> %0 to <4 x float>
180  %3 = fmul <4 x float> %2, <float 0x3ED0000000000000, float 0x3ED0000000000000, float 0x3ED0000000000000, float 0x3ED0000000000000>
181  ret <4 x float> %3
182}
183
184define arm_aapcs_vfpcc <4 x float> @vcvt_i32_19(<4 x i32> %0) {
185; CHECK-LABEL: vcvt_i32_19:
186; CHECK:       @ %bb.0:
187; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #19
188; CHECK-NEXT:    bx lr
189  %2 = sitofp <4 x i32> %0 to <4 x float>
190  %3 = fmul <4 x float> %2, <float 0x3EC0000000000000, float 0x3EC0000000000000, float 0x3EC0000000000000, float 0x3EC0000000000000>
191  ret <4 x float> %3
192}
193
194define arm_aapcs_vfpcc <4 x float> @vcvt_i32_20(<4 x i32> %0) {
195; CHECK-LABEL: vcvt_i32_20:
196; CHECK:       @ %bb.0:
197; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #20
198; CHECK-NEXT:    bx lr
199  %2 = sitofp <4 x i32> %0 to <4 x float>
200  %3 = fmul <4 x float> %2, <float 0x3EB0000000000000, float 0x3EB0000000000000, float 0x3EB0000000000000, float 0x3EB0000000000000>
201  ret <4 x float> %3
202}
203
204define arm_aapcs_vfpcc <4 x float> @vcvt_i32_21(<4 x i32> %0) {
205; CHECK-LABEL: vcvt_i32_21:
206; CHECK:       @ %bb.0:
207; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #21
208; CHECK-NEXT:    bx lr
209  %2 = sitofp <4 x i32> %0 to <4 x float>
210  %3 = fmul <4 x float> %2, <float 0x3EA0000000000000, float 0x3EA0000000000000, float 0x3EA0000000000000, float 0x3EA0000000000000>
211  ret <4 x float> %3
212}
213
214define arm_aapcs_vfpcc <4 x float> @vcvt_i32_22(<4 x i32> %0) {
215; CHECK-LABEL: vcvt_i32_22:
216; CHECK:       @ %bb.0:
217; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #22
218; CHECK-NEXT:    bx lr
219  %2 = sitofp <4 x i32> %0 to <4 x float>
220  %3 = fmul <4 x float> %2, <float 0x3E90000000000000, float 0x3E90000000000000, float 0x3E90000000000000, float 0x3E90000000000000>
221  ret <4 x float> %3
222}
223
224define arm_aapcs_vfpcc <4 x float> @vcvt_i32_23(<4 x i32> %0) {
225; CHECK-LABEL: vcvt_i32_23:
226; CHECK:       @ %bb.0:
227; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #23
228; CHECK-NEXT:    bx lr
229  %2 = sitofp <4 x i32> %0 to <4 x float>
230  %3 = fmul <4 x float> %2, <float 0x3E80000000000000, float 0x3E80000000000000, float 0x3E80000000000000, float 0x3E80000000000000>
231  ret <4 x float> %3
232}
233
234define arm_aapcs_vfpcc <4 x float> @vcvt_i32_24(<4 x i32> %0) {
235; CHECK-LABEL: vcvt_i32_24:
236; CHECK:       @ %bb.0:
237; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #24
238; CHECK-NEXT:    bx lr
239  %2 = sitofp <4 x i32> %0 to <4 x float>
240  %3 = fmul <4 x float> %2, <float 0x3E70000000000000, float 0x3E70000000000000, float 0x3E70000000000000, float 0x3E70000000000000>
241  ret <4 x float> %3
242}
243
244define arm_aapcs_vfpcc <4 x float> @vcvt_i32_25(<4 x i32> %0) {
245; CHECK-LABEL: vcvt_i32_25:
246; CHECK:       @ %bb.0:
247; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #25
248; CHECK-NEXT:    bx lr
249  %2 = sitofp <4 x i32> %0 to <4 x float>
250  %3 = fmul <4 x float> %2, <float 0x3E60000000000000, float 0x3E60000000000000, float 0x3E60000000000000, float 0x3E60000000000000>
251  ret <4 x float> %3
252}
253
254define arm_aapcs_vfpcc <4 x float> @vcvt_i32_26(<4 x i32> %0) {
255; CHECK-LABEL: vcvt_i32_26:
256; CHECK:       @ %bb.0:
257; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #26
258; CHECK-NEXT:    bx lr
259  %2 = sitofp <4 x i32> %0 to <4 x float>
260  %3 = fmul <4 x float> %2, <float 0x3E50000000000000, float 0x3E50000000000000, float 0x3E50000000000000, float 0x3E50000000000000>
261  ret <4 x float> %3
262}
263
264define arm_aapcs_vfpcc <4 x float> @vcvt_i32_27(<4 x i32> %0) {
265; CHECK-LABEL: vcvt_i32_27:
266; CHECK:       @ %bb.0:
267; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #27
268; CHECK-NEXT:    bx lr
269  %2 = sitofp <4 x i32> %0 to <4 x float>
270  %3 = fmul <4 x float> %2, <float 0x3E40000000000000, float 0x3E40000000000000, float 0x3E40000000000000, float 0x3E40000000000000>
271  ret <4 x float> %3
272}
273
274define arm_aapcs_vfpcc <4 x float> @vcvt_i32_28(<4 x i32> %0) {
275; CHECK-LABEL: vcvt_i32_28:
276; CHECK:       @ %bb.0:
277; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #28
278; CHECK-NEXT:    bx lr
279  %2 = sitofp <4 x i32> %0 to <4 x float>
280  %3 = fmul <4 x float> %2, <float 0x3E30000000000000, float 0x3E30000000000000, float 0x3E30000000000000, float 0x3E30000000000000>
281  ret <4 x float> %3
282}
283
284define arm_aapcs_vfpcc <4 x float> @vcvt_i32_29(<4 x i32> %0) {
285; CHECK-LABEL: vcvt_i32_29:
286; CHECK:       @ %bb.0:
287; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #29
288; CHECK-NEXT:    bx lr
289  %2 = sitofp <4 x i32> %0 to <4 x float>
290  %3 = fmul <4 x float> %2, <float 0x3E20000000000000, float 0x3E20000000000000, float 0x3E20000000000000, float 0x3E20000000000000>
291  ret <4 x float> %3
292}
293
294define arm_aapcs_vfpcc <4 x float> @vcvt_i32_30(<4 x i32> %0) {
295; CHECK-LABEL: vcvt_i32_30:
296; CHECK:       @ %bb.0:
297; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #30
298; CHECK-NEXT:    bx lr
299  %2 = sitofp <4 x i32> %0 to <4 x float>
300  %3 = fmul <4 x float> %2, <float 0x3E10000000000000, float 0x3E10000000000000, float 0x3E10000000000000, float 0x3E10000000000000>
301  ret <4 x float> %3
302}
303
304define arm_aapcs_vfpcc <4 x float> @vcvt_i32_31(<4 x i32> %0) {
305; CHECK-LABEL: vcvt_i32_31:
306; CHECK:       @ %bb.0:
307; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #31
308; CHECK-NEXT:    bx lr
309  %2 = sitofp <4 x i32> %0 to <4 x float>
310  %3 = fmul <4 x float> %2, <float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000>
311  ret <4 x float> %3
312}
313
314define arm_aapcs_vfpcc <4 x float> @vcvt_i32_32(<4 x i32> %0) {
315; CHECK-LABEL: vcvt_i32_32:
316; CHECK:       @ %bb.0:
317; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #32
318; CHECK-NEXT:    bx lr
319  %2 = sitofp <4 x i32> %0 to <4 x float>
320  %3 = fmul <4 x float> %2, <float 0x3DF0000000000000, float 0x3DF0000000000000, float 0x3DF0000000000000, float 0x3DF0000000000000>
321  ret <4 x float> %3
322}
323
324define arm_aapcs_vfpcc <4 x float> @vcvt_i32_33(<4 x i32> %0) {
325; CHECK-LABEL: vcvt_i32_33:
326; CHECK:       @ %bb.0:
327; CHECK-NEXT:    vmov.i32 q1, #0x2f000000
328; CHECK-NEXT:    vcvt.f32.s32 q0, q0
329; CHECK-NEXT:    vmul.f32 q0, q0, q1
330; CHECK-NEXT:    bx lr
331  %2 = sitofp <4 x i32> %0 to <4 x float>
332  %3 = fmul <4 x float> %2, <float 0x3DE0000000000000, float 0x3DE0000000000000, float 0x3DE0000000000000, float 0x3DE0000000000000>
333  ret <4 x float> %3
334}
335
336define arm_aapcs_vfpcc <8 x half> @vcvt_i16_1(<8 x i16> %0) {
337; CHECK-LABEL: vcvt_i16_1:
338; CHECK:       @ %bb.0:
339; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #1
340; CHECK-NEXT:    bx lr
341  %2 = sitofp <8 x i16> %0 to <8 x half>
342  %3 = fmul ninf <8 x half> %2, <half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800>
343  ret <8 x half> %3
344}
345
346define arm_aapcs_vfpcc <8 x half> @vcvt_i16_2(<8 x i16> %0) {
347; CHECK-LABEL: vcvt_i16_2:
348; CHECK:       @ %bb.0:
349; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #2
350; CHECK-NEXT:    bx lr
351  %2 = sitofp <8 x i16> %0 to <8 x half>
352  %3 = fmul ninf <8 x half> %2, <half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400>
353  ret <8 x half> %3
354}
355
356define arm_aapcs_vfpcc <8 x half> @vcvt_i16_3(<8 x i16> %0) {
357; CHECK-LABEL: vcvt_i16_3:
358; CHECK:       @ %bb.0:
359; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #3
360; CHECK-NEXT:    bx lr
361  %2 = sitofp <8 x i16> %0 to <8 x half>
362  %3 = fmul ninf <8 x half> %2, <half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000>
363  ret <8 x half> %3
364}
365
366define arm_aapcs_vfpcc <8 x half> @vcvt_i16_4(<8 x i16> %0) {
367; CHECK-LABEL: vcvt_i16_4:
368; CHECK:       @ %bb.0:
369; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #4
370; CHECK-NEXT:    bx lr
371  %2 = sitofp <8 x i16> %0 to <8 x half>
372  %3 = fmul ninf <8 x half> %2, <half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00>
373  ret <8 x half> %3
374}
375
376define arm_aapcs_vfpcc <8 x half> @vcvt_i16_5(<8 x i16> %0) {
377; CHECK-LABEL: vcvt_i16_5:
378; CHECK:       @ %bb.0:
379; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #5
380; CHECK-NEXT:    bx lr
381  %2 = sitofp <8 x i16> %0 to <8 x half>
382  %3 = fmul ninf <8 x half> %2, <half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800>
383  ret <8 x half> %3
384}
385
386define arm_aapcs_vfpcc <8 x half> @vcvt_i16_6(<8 x i16> %0) {
387; CHECK-LABEL: vcvt_i16_6:
388; CHECK:       @ %bb.0:
389; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #6
390; CHECK-NEXT:    bx lr
391  %2 = sitofp <8 x i16> %0 to <8 x half>
392  %3 = fmul ninf <8 x half> %2, <half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400>
393  ret <8 x half> %3
394}
395
396define arm_aapcs_vfpcc <8 x half> @vcvt_i16_7(<8 x i16> %0) {
397; CHECK-LABEL: vcvt_i16_7:
398; CHECK:       @ %bb.0:
399; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #7
400; CHECK-NEXT:    bx lr
401  %2 = sitofp <8 x i16> %0 to <8 x half>
402  %3 = fmul ninf <8 x half> %2, <half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000>
403  ret <8 x half> %3
404}
405
406define arm_aapcs_vfpcc <8 x half> @vcvt_i16_8(<8 x i16> %0) {
407; CHECK-LABEL: vcvt_i16_8:
408; CHECK:       @ %bb.0:
409; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #8
410; CHECK-NEXT:    bx lr
411  %2 = sitofp <8 x i16> %0 to <8 x half>
412  %3 = fmul ninf <8 x half> %2, <half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00>
413  ret <8 x half> %3
414}
415
416define arm_aapcs_vfpcc <8 x half> @vcvt_i16_9(<8 x i16> %0) {
417; CHECK-LABEL: vcvt_i16_9:
418; CHECK:       @ %bb.0:
419; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #9
420; CHECK-NEXT:    bx lr
421  %2 = sitofp <8 x i16> %0 to <8 x half>
422  %3 = fmul ninf <8 x half> %2, <half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800>
423  ret <8 x half> %3
424}
425
426define arm_aapcs_vfpcc <8 x half> @vcvt_i16_10(<8 x i16> %0) {
427; CHECK-LABEL: vcvt_i16_10:
428; CHECK:       @ %bb.0:
429; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #10
430; CHECK-NEXT:    bx lr
431  %2 = sitofp <8 x i16> %0 to <8 x half>
432  %3 = fmul ninf <8 x half> %2, <half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400>
433  ret <8 x half> %3
434}
435
436define arm_aapcs_vfpcc <8 x half> @vcvt_i16_11(<8 x i16> %0) {
437; CHECK-LABEL: vcvt_i16_11:
438; CHECK:       @ %bb.0:
439; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #11
440; CHECK-NEXT:    bx lr
441  %2 = sitofp <8 x i16> %0 to <8 x half>
442  %3 = fmul ninf <8 x half> %2, <half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000>
443  ret <8 x half> %3
444}
445
446define arm_aapcs_vfpcc <8 x half> @vcvt_i16_12(<8 x i16> %0) {
447; CHECK-LABEL: vcvt_i16_12:
448; CHECK:       @ %bb.0:
449; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #12
450; CHECK-NEXT:    bx lr
451  %2 = sitofp <8 x i16> %0 to <8 x half>
452  %3 = fmul ninf <8 x half> %2, <half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00>
453  ret <8 x half> %3
454}
455
456define arm_aapcs_vfpcc <8 x half> @vcvt_i16_13(<8 x i16> %0) {
457; CHECK-LABEL: vcvt_i16_13:
458; CHECK:       @ %bb.0:
459; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #13
460; CHECK-NEXT:    bx lr
461  %2 = sitofp <8 x i16> %0 to <8 x half>
462  %3 = fmul ninf <8 x half> %2, <half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800>
463  ret <8 x half> %3
464}
465
466define arm_aapcs_vfpcc <8 x half> @vcvt_i16_14(<8 x i16> %0) {
467; CHECK-LABEL: vcvt_i16_14:
468; CHECK:       @ %bb.0:
469; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #14
470; CHECK-NEXT:    bx lr
471  %2 = sitofp <8 x i16> %0 to <8 x half>
472  %3 = fmul ninf <8 x half> %2, <half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400>
473  ret <8 x half> %3
474}
475
476define arm_aapcs_vfpcc <8 x half> @vcvt_i16_15(<8 x i16> %0) {
477; CHECK-LABEL: vcvt_i16_15:
478; CHECK:       @ %bb.0:
479; CHECK-NEXT:    vmov.i16 q1, #0x200
480; CHECK-NEXT:    vcvt.f16.s16 q0, q0
481; CHECK-NEXT:    vmul.f16 q0, q0, q1
482; CHECK-NEXT:    bx lr
483  %2 = sitofp <8 x i16> %0 to <8 x half>
484  %3 = fmul ninf <8 x half> %2, <half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200>
485  ret <8 x half> %3
486}
487
488define arm_aapcs_vfpcc <4 x float> @vcvt_u32_1(<4 x i32> %0) {
489; CHECK-LABEL: vcvt_u32_1:
490; CHECK:       @ %bb.0:
491; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #1
492; CHECK-NEXT:    bx lr
493  %2 = uitofp <4 x i32> %0 to <4 x float>
494  %3 = fmul <4 x float> %2, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01>
495  ret <4 x float> %3
496}
497
498define arm_aapcs_vfpcc <4 x float> @vcvt_u32_2(<4 x i32> %0) {
499; CHECK-LABEL: vcvt_u32_2:
500; CHECK:       @ %bb.0:
501; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #2
502; CHECK-NEXT:    bx lr
503  %2 = uitofp <4 x i32> %0 to <4 x float>
504  %3 = fmul <4 x float> %2, <float 2.500000e-01, float 2.500000e-01, float 2.500000e-01, float 2.500000e-01>
505  ret <4 x float> %3
506}
507
508define arm_aapcs_vfpcc <4 x float> @vcvt_u32_3(<4 x i32> %0) {
509; CHECK-LABEL: vcvt_u32_3:
510; CHECK:       @ %bb.0:
511; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #3
512; CHECK-NEXT:    bx lr
513  %2 = uitofp <4 x i32> %0 to <4 x float>
514  %3 = fmul <4 x float> %2, <float 1.250000e-01, float 1.250000e-01, float 1.250000e-01, float 1.250000e-01>
515  ret <4 x float> %3
516}
517
518define arm_aapcs_vfpcc <4 x float> @vcvt_u32_4(<4 x i32> %0) {
519; CHECK-LABEL: vcvt_u32_4:
520; CHECK:       @ %bb.0:
521; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #4
522; CHECK-NEXT:    bx lr
523  %2 = uitofp <4 x i32> %0 to <4 x float>
524  %3 = fmul <4 x float> %2, <float 6.250000e-02, float 6.250000e-02, float 6.250000e-02, float 6.250000e-02>
525  ret <4 x float> %3
526}
527
528define arm_aapcs_vfpcc <4 x float> @vcvt_u32_5(<4 x i32> %0) {
529; CHECK-LABEL: vcvt_u32_5:
530; CHECK:       @ %bb.0:
531; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #5
532; CHECK-NEXT:    bx lr
533  %2 = uitofp <4 x i32> %0 to <4 x float>
534  %3 = fmul <4 x float> %2, <float 3.125000e-02, float 3.125000e-02, float 3.125000e-02, float 3.125000e-02>
535  ret <4 x float> %3
536}
537
538define arm_aapcs_vfpcc <4 x float> @vcvt_u32_6(<4 x i32> %0) {
539; CHECK-LABEL: vcvt_u32_6:
540; CHECK:       @ %bb.0:
541; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #6
542; CHECK-NEXT:    bx lr
543  %2 = uitofp <4 x i32> %0 to <4 x float>
544  %3 = fmul <4 x float> %2, <float 1.562500e-02, float 1.562500e-02, float 1.562500e-02, float 1.562500e-02>
545  ret <4 x float> %3
546}
547
548define arm_aapcs_vfpcc <4 x float> @vcvt_u32_7(<4 x i32> %0) {
549; CHECK-LABEL: vcvt_u32_7:
550; CHECK:       @ %bb.0:
551; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #7
552; CHECK-NEXT:    bx lr
553  %2 = uitofp <4 x i32> %0 to <4 x float>
554  %3 = fmul <4 x float> %2, <float 7.812500e-03, float 7.812500e-03, float 7.812500e-03, float 7.812500e-03>
555  ret <4 x float> %3
556}
557
558define arm_aapcs_vfpcc <4 x float> @vcvt_u32_8(<4 x i32> %0) {
559; CHECK-LABEL: vcvt_u32_8:
560; CHECK:       @ %bb.0:
561; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #8
562; CHECK-NEXT:    bx lr
563  %2 = uitofp <4 x i32> %0 to <4 x float>
564  %3 = fmul <4 x float> %2, <float 3.906250e-03, float 3.906250e-03, float 3.906250e-03, float 3.906250e-03>
565  ret <4 x float> %3
566}
567
568define arm_aapcs_vfpcc <4 x float> @vcvt_u32_9(<4 x i32> %0) {
569; CHECK-LABEL: vcvt_u32_9:
570; CHECK:       @ %bb.0:
571; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #9
572; CHECK-NEXT:    bx lr
573  %2 = uitofp <4 x i32> %0 to <4 x float>
574  %3 = fmul <4 x float> %2, <float 0x3F60000000000000, float 0x3F60000000000000, float 0x3F60000000000000, float 0x3F60000000000000>
575  ret <4 x float> %3
576}
577
578define arm_aapcs_vfpcc <4 x float> @vcvt_u32_10(<4 x i32> %0) {
579; CHECK-LABEL: vcvt_u32_10:
580; CHECK:       @ %bb.0:
581; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #10
582; CHECK-NEXT:    bx lr
583  %2 = uitofp <4 x i32> %0 to <4 x float>
584  %3 = fmul <4 x float> %2, <float 0x3F50000000000000, float 0x3F50000000000000, float 0x3F50000000000000, float 0x3F50000000000000>
585  ret <4 x float> %3
586}
587
588define arm_aapcs_vfpcc <4 x float> @vcvt_u32_11(<4 x i32> %0) {
589; CHECK-LABEL: vcvt_u32_11:
590; CHECK:       @ %bb.0:
591; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #11
592; CHECK-NEXT:    bx lr
593  %2 = uitofp <4 x i32> %0 to <4 x float>
594  %3 = fmul <4 x float> %2, <float 0x3F40000000000000, float 0x3F40000000000000, float 0x3F40000000000000, float 0x3F40000000000000>
595  ret <4 x float> %3
596}
597
598define arm_aapcs_vfpcc <4 x float> @vcvt_u32_12(<4 x i32> %0) {
599; CHECK-LABEL: vcvt_u32_12:
600; CHECK:       @ %bb.0:
601; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #12
602; CHECK-NEXT:    bx lr
603  %2 = uitofp <4 x i32> %0 to <4 x float>
604  %3 = fmul <4 x float> %2, <float 0x3F30000000000000, float 0x3F30000000000000, float 0x3F30000000000000, float 0x3F30000000000000>
605  ret <4 x float> %3
606}
607
608define arm_aapcs_vfpcc <4 x float> @vcvt_u32_13(<4 x i32> %0) {
609; CHECK-LABEL: vcvt_u32_13:
610; CHECK:       @ %bb.0:
611; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #13
612; CHECK-NEXT:    bx lr
613  %2 = uitofp <4 x i32> %0 to <4 x float>
614  %3 = fmul <4 x float> %2, <float 0x3F20000000000000, float 0x3F20000000000000, float 0x3F20000000000000, float 0x3F20000000000000>
615  ret <4 x float> %3
616}
617
618define arm_aapcs_vfpcc <4 x float> @vcvt_u32_14(<4 x i32> %0) {
619; CHECK-LABEL: vcvt_u32_14:
620; CHECK:       @ %bb.0:
621; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #14
622; CHECK-NEXT:    bx lr
623  %2 = uitofp <4 x i32> %0 to <4 x float>
624  %3 = fmul <4 x float> %2, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
625  ret <4 x float> %3
626}
627
628define arm_aapcs_vfpcc <4 x float> @vcvt_u32_15(<4 x i32> %0) {
629; CHECK-LABEL: vcvt_u32_15:
630; CHECK:       @ %bb.0:
631; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #15
632; CHECK-NEXT:    bx lr
633  %2 = uitofp <4 x i32> %0 to <4 x float>
634  %3 = fmul <4 x float> %2, <float 0x3F00000000000000, float 0x3F00000000000000, float 0x3F00000000000000, float 0x3F00000000000000>
635  ret <4 x float> %3
636}
637
638define arm_aapcs_vfpcc <4 x float> @vcvt_u32_16(<4 x i32> %0) {
639; CHECK-LABEL: vcvt_u32_16:
640; CHECK:       @ %bb.0:
641; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #16
642; CHECK-NEXT:    bx lr
643  %2 = uitofp <4 x i32> %0 to <4 x float>
644  %3 = fmul <4 x float> %2, <float 0x3EF0000000000000, float 0x3EF0000000000000, float 0x3EF0000000000000, float 0x3EF0000000000000>
645  ret <4 x float> %3
646}
647
648define arm_aapcs_vfpcc <4 x float> @vcvt_u32_17(<4 x i32> %0) {
649; CHECK-LABEL: vcvt_u32_17:
650; CHECK:       @ %bb.0:
651; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #17
652; CHECK-NEXT:    bx lr
653  %2 = uitofp <4 x i32> %0 to <4 x float>
654  %3 = fmul <4 x float> %2, <float 0x3EE0000000000000, float 0x3EE0000000000000, float 0x3EE0000000000000, float 0x3EE0000000000000>
655  ret <4 x float> %3
656}
657
658define arm_aapcs_vfpcc <4 x float> @vcvt_u32_18(<4 x i32> %0) {
659; CHECK-LABEL: vcvt_u32_18:
660; CHECK:       @ %bb.0:
661; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #18
662; CHECK-NEXT:    bx lr
663  %2 = uitofp <4 x i32> %0 to <4 x float>
664  %3 = fmul <4 x float> %2, <float 0x3ED0000000000000, float 0x3ED0000000000000, float 0x3ED0000000000000, float 0x3ED0000000000000>
665  ret <4 x float> %3
666}
667
668define arm_aapcs_vfpcc <4 x float> @vcvt_u32_19(<4 x i32> %0) {
669; CHECK-LABEL: vcvt_u32_19:
670; CHECK:       @ %bb.0:
671; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #19
672; CHECK-NEXT:    bx lr
673  %2 = uitofp <4 x i32> %0 to <4 x float>
674  %3 = fmul <4 x float> %2, <float 0x3EC0000000000000, float 0x3EC0000000000000, float 0x3EC0000000000000, float 0x3EC0000000000000>
675  ret <4 x float> %3
676}
677
678define arm_aapcs_vfpcc <4 x float> @vcvt_u32_20(<4 x i32> %0) {
679; CHECK-LABEL: vcvt_u32_20:
680; CHECK:       @ %bb.0:
681; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #20
682; CHECK-NEXT:    bx lr
683  %2 = uitofp <4 x i32> %0 to <4 x float>
684  %3 = fmul <4 x float> %2, <float 0x3EB0000000000000, float 0x3EB0000000000000, float 0x3EB0000000000000, float 0x3EB0000000000000>
685  ret <4 x float> %3
686}
687
688define arm_aapcs_vfpcc <4 x float> @vcvt_u32_21(<4 x i32> %0) {
689; CHECK-LABEL: vcvt_u32_21:
690; CHECK:       @ %bb.0:
691; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #21
692; CHECK-NEXT:    bx lr
693  %2 = uitofp <4 x i32> %0 to <4 x float>
694  %3 = fmul <4 x float> %2, <float 0x3EA0000000000000, float 0x3EA0000000000000, float 0x3EA0000000000000, float 0x3EA0000000000000>
695  ret <4 x float> %3
696}
697
698define arm_aapcs_vfpcc <4 x float> @vcvt_u32_22(<4 x i32> %0) {
699; CHECK-LABEL: vcvt_u32_22:
700; CHECK:       @ %bb.0:
701; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #22
702; CHECK-NEXT:    bx lr
703  %2 = uitofp <4 x i32> %0 to <4 x float>
704  %3 = fmul <4 x float> %2, <float 0x3E90000000000000, float 0x3E90000000000000, float 0x3E90000000000000, float 0x3E90000000000000>
705  ret <4 x float> %3
706}
707
708define arm_aapcs_vfpcc <4 x float> @vcvt_u32_23(<4 x i32> %0) {
709; CHECK-LABEL: vcvt_u32_23:
710; CHECK:       @ %bb.0:
711; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #23
712; CHECK-NEXT:    bx lr
713  %2 = uitofp <4 x i32> %0 to <4 x float>
714  %3 = fmul <4 x float> %2, <float 0x3E80000000000000, float 0x3E80000000000000, float 0x3E80000000000000, float 0x3E80000000000000>
715  ret <4 x float> %3
716}
717
718define arm_aapcs_vfpcc <4 x float> @vcvt_u32_24(<4 x i32> %0) {
719; CHECK-LABEL: vcvt_u32_24:
720; CHECK:       @ %bb.0:
721; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #24
722; CHECK-NEXT:    bx lr
723  %2 = uitofp <4 x i32> %0 to <4 x float>
724  %3 = fmul <4 x float> %2, <float 0x3E70000000000000, float 0x3E70000000000000, float 0x3E70000000000000, float 0x3E70000000000000>
725  ret <4 x float> %3
726}
727
728define arm_aapcs_vfpcc <4 x float> @vcvt_u32_25(<4 x i32> %0) {
729; CHECK-LABEL: vcvt_u32_25:
730; CHECK:       @ %bb.0:
731; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #25
732; CHECK-NEXT:    bx lr
733  %2 = uitofp <4 x i32> %0 to <4 x float>
734  %3 = fmul <4 x float> %2, <float 0x3E60000000000000, float 0x3E60000000000000, float 0x3E60000000000000, float 0x3E60000000000000>
735  ret <4 x float> %3
736}
737
738define arm_aapcs_vfpcc <4 x float> @vcvt_u32_26(<4 x i32> %0) {
739; CHECK-LABEL: vcvt_u32_26:
740; CHECK:       @ %bb.0:
741; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #26
742; CHECK-NEXT:    bx lr
743  %2 = uitofp <4 x i32> %0 to <4 x float>
744  %3 = fmul <4 x float> %2, <float 0x3E50000000000000, float 0x3E50000000000000, float 0x3E50000000000000, float 0x3E50000000000000>
745  ret <4 x float> %3
746}
747
748define arm_aapcs_vfpcc <4 x float> @vcvt_u32_27(<4 x i32> %0) {
749; CHECK-LABEL: vcvt_u32_27:
750; CHECK:       @ %bb.0:
751; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #27
752; CHECK-NEXT:    bx lr
753  %2 = uitofp <4 x i32> %0 to <4 x float>
754  %3 = fmul <4 x float> %2, <float 0x3E40000000000000, float 0x3E40000000000000, float 0x3E40000000000000, float 0x3E40000000000000>
755  ret <4 x float> %3
756}
757
758define arm_aapcs_vfpcc <4 x float> @vcvt_u32_28(<4 x i32> %0) {
759; CHECK-LABEL: vcvt_u32_28:
760; CHECK:       @ %bb.0:
761; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #28
762; CHECK-NEXT:    bx lr
763  %2 = uitofp <4 x i32> %0 to <4 x float>
764  %3 = fmul <4 x float> %2, <float 0x3E30000000000000, float 0x3E30000000000000, float 0x3E30000000000000, float 0x3E30000000000000>
765  ret <4 x float> %3
766}
767
768define arm_aapcs_vfpcc <4 x float> @vcvt_u32_29(<4 x i32> %0) {
769; CHECK-LABEL: vcvt_u32_29:
770; CHECK:       @ %bb.0:
771; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #29
772; CHECK-NEXT:    bx lr
773  %2 = uitofp <4 x i32> %0 to <4 x float>
774  %3 = fmul <4 x float> %2, <float 0x3E20000000000000, float 0x3E20000000000000, float 0x3E20000000000000, float 0x3E20000000000000>
775  ret <4 x float> %3
776}
777
778define arm_aapcs_vfpcc <4 x float> @vcvt_u32_30(<4 x i32> %0) {
779; CHECK-LABEL: vcvt_u32_30:
780; CHECK:       @ %bb.0:
781; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #30
782; CHECK-NEXT:    bx lr
783  %2 = uitofp <4 x i32> %0 to <4 x float>
784  %3 = fmul <4 x float> %2, <float 0x3E10000000000000, float 0x3E10000000000000, float 0x3E10000000000000, float 0x3E10000000000000>
785  ret <4 x float> %3
786}
787
788define arm_aapcs_vfpcc <4 x float> @vcvt_u32_31(<4 x i32> %0) {
789; CHECK-LABEL: vcvt_u32_31:
790; CHECK:       @ %bb.0:
791; CHECK-NEXT:    vmov.i32 q1, #0xb0000000
792; CHECK-NEXT:    vcvt.f32.u32 q0, q0
793; CHECK-NEXT:    vmul.f32 q0, q0, q1
794; CHECK-NEXT:    bx lr
795  %2 = uitofp <4 x i32> %0 to <4 x float>
796  %3 = fmul <4 x float> %2, <float 0xBE00000000000000, float 0xBE00000000000000, float 0xBE00000000000000, float 0xBE00000000000000>
797  ret <4 x float> %3
798}
799
800define arm_aapcs_vfpcc <4 x float> @vcvt_u32_32(<4 x i32> %0) {
801; CHECK-LABEL: vcvt_u32_32:
802; CHECK:       @ %bb.0:
803; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #32
804; CHECK-NEXT:    bx lr
805  %2 = uitofp <4 x i32> %0 to <4 x float>
806  %3 = fmul <4 x float> %2, <float 0x3DF0000000000000, float 0x3DF0000000000000, float 0x3DF0000000000000, float 0x3DF0000000000000>
807  ret <4 x float> %3
808}
809
810define arm_aapcs_vfpcc <4 x float> @vcvt_u32_33(<4 x i32> %0) {
811; CHECK-LABEL: vcvt_u32_33:
812; CHECK:       @ %bb.0:
813; CHECK-NEXT:    vmov.i32 q1, #0x2f000000
814; CHECK-NEXT:    vcvt.f32.u32 q0, q0
815; CHECK-NEXT:    vmul.f32 q0, q0, q1
816; CHECK-NEXT:    bx lr
817  %2 = uitofp <4 x i32> %0 to <4 x float>
818  %3 = fmul <4 x float> %2, <float 0x3DE0000000000000, float 0x3DE0000000000000, float 0x3DE0000000000000, float 0x3DE0000000000000>
819  ret <4 x float> %3
820}
821
822define arm_aapcs_vfpcc <8 x half> @vcvt_u16_1(<8 x i16> %0) {
823; CHECK-LABEL: vcvt_u16_1:
824; CHECK:       @ %bb.0:
825; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #1
826; CHECK-NEXT:    bx lr
827  %2 = uitofp <8 x i16> %0 to <8 x half>
828  %3 = fmul ninf <8 x half> %2, <half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800>
829  ret <8 x half> %3
830}
831
832define arm_aapcs_vfpcc <8 x half> @vcvt_u16_2(<8 x i16> %0) {
833; CHECK-LABEL: vcvt_u16_2:
834; CHECK:       @ %bb.0:
835; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #2
836; CHECK-NEXT:    bx lr
837  %2 = uitofp <8 x i16> %0 to <8 x half>
838  %3 = fmul ninf <8 x half> %2, <half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400>
839  ret <8 x half> %3
840}
841
842define arm_aapcs_vfpcc <8 x half> @vcvt_u16_3(<8 x i16> %0) {
843; CHECK-LABEL: vcvt_u16_3:
844; CHECK:       @ %bb.0:
845; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #3
846; CHECK-NEXT:    bx lr
847  %2 = uitofp <8 x i16> %0 to <8 x half>
848  %3 = fmul ninf <8 x half> %2, <half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000>
849  ret <8 x half> %3
850}
851
852define arm_aapcs_vfpcc <8 x half> @vcvt_u16_4(<8 x i16> %0) {
853; CHECK-LABEL: vcvt_u16_4:
854; CHECK:       @ %bb.0:
855; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #4
856; CHECK-NEXT:    bx lr
857  %2 = uitofp <8 x i16> %0 to <8 x half>
858  %3 = fmul ninf <8 x half> %2, <half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00>
859  ret <8 x half> %3
860}
861
862define arm_aapcs_vfpcc <8 x half> @vcvt_u16_5(<8 x i16> %0) {
863; CHECK-LABEL: vcvt_u16_5:
864; CHECK:       @ %bb.0:
865; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #5
866; CHECK-NEXT:    bx lr
867  %2 = uitofp <8 x i16> %0 to <8 x half>
868  %3 = fmul ninf <8 x half> %2, <half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800>
869  ret <8 x half> %3
870}
871
872define arm_aapcs_vfpcc <8 x half> @vcvt_u16_6(<8 x i16> %0) {
873; CHECK-LABEL: vcvt_u16_6:
874; CHECK:       @ %bb.0:
875; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #6
876; CHECK-NEXT:    bx lr
877  %2 = uitofp <8 x i16> %0 to <8 x half>
878  %3 = fmul ninf <8 x half> %2, <half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400>
879  ret <8 x half> %3
880}
881
882define arm_aapcs_vfpcc <8 x half> @vcvt_u16_7(<8 x i16> %0) {
883; CHECK-LABEL: vcvt_u16_7:
884; CHECK:       @ %bb.0:
885; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #7
886; CHECK-NEXT:    bx lr
887  %2 = uitofp <8 x i16> %0 to <8 x half>
888  %3 = fmul ninf <8 x half> %2, <half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000>
889  ret <8 x half> %3
890}
891
892define arm_aapcs_vfpcc <8 x half> @vcvt_u16_8(<8 x i16> %0) {
893; CHECK-LABEL: vcvt_u16_8:
894; CHECK:       @ %bb.0:
895; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #8
896; CHECK-NEXT:    bx lr
897  %2 = uitofp <8 x i16> %0 to <8 x half>
898  %3 = fmul ninf <8 x half> %2, <half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00>
899  ret <8 x half> %3
900}
901
902define arm_aapcs_vfpcc <8 x half> @vcvt_u16_9(<8 x i16> %0) {
903; CHECK-LABEL: vcvt_u16_9:
904; CHECK:       @ %bb.0:
905; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #9
906; CHECK-NEXT:    bx lr
907  %2 = uitofp <8 x i16> %0 to <8 x half>
908  %3 = fmul ninf <8 x half> %2, <half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800>
909  ret <8 x half> %3
910}
911
912define arm_aapcs_vfpcc <8 x half> @vcvt_u16_10(<8 x i16> %0) {
913; CHECK-LABEL: vcvt_u16_10:
914; CHECK:       @ %bb.0:
915; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #10
916; CHECK-NEXT:    bx lr
917  %2 = uitofp <8 x i16> %0 to <8 x half>
918  %3 = fmul ninf <8 x half> %2, <half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400>
919  ret <8 x half> %3
920}
921
922define arm_aapcs_vfpcc <8 x half> @vcvt_u16_11(<8 x i16> %0) {
923; CHECK-LABEL: vcvt_u16_11:
924; CHECK:       @ %bb.0:
925; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #11
926; CHECK-NEXT:    bx lr
927  %2 = uitofp <8 x i16> %0 to <8 x half>
928  %3 = fmul ninf <8 x half> %2, <half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000>
929  ret <8 x half> %3
930}
931
932define arm_aapcs_vfpcc <8 x half> @vcvt_u16_12(<8 x i16> %0) {
933; CHECK-LABEL: vcvt_u16_12:
934; CHECK:       @ %bb.0:
935; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #12
936; CHECK-NEXT:    bx lr
937  %2 = uitofp <8 x i16> %0 to <8 x half>
938  %3 = fmul ninf <8 x half> %2, <half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00>
939  ret <8 x half> %3
940}
941
942define arm_aapcs_vfpcc <8 x half> @vcvt_u16_13(<8 x i16> %0) {
943; CHECK-LABEL: vcvt_u16_13:
944; CHECK:       @ %bb.0:
945; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #13
946; CHECK-NEXT:    bx lr
947  %2 = uitofp <8 x i16> %0 to <8 x half>
948  %3 = fmul ninf <8 x half> %2, <half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800>
949  ret <8 x half> %3
950}
951
952define arm_aapcs_vfpcc <8 x half> @vcvt_u16_14(<8 x i16> %0) {
953; CHECK-LABEL: vcvt_u16_14:
954; CHECK:       @ %bb.0:
955; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #14
956; CHECK-NEXT:    bx lr
957  %2 = uitofp <8 x i16> %0 to <8 x half>
958  %3 = fmul ninf <8 x half> %2, <half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400>
959  ret <8 x half> %3
960}
961
962define arm_aapcs_vfpcc <8 x half> @vcvt_u16_15(<8 x i16> %0) {
963; CHECK-LABEL: vcvt_u16_15:
964; CHECK:       @ %bb.0:
965; CHECK-NEXT:    vmov.i16 q1, #0x200
966; CHECK-NEXT:    vcvt.f16.u16 q0, q0
967; CHECK-NEXT:    vmul.f16 q0, q0, q1
968; CHECK-NEXT:    bx lr
969  %2 = uitofp <8 x i16> %0 to <8 x half>
970  %3 = fmul ninf <8 x half> %2, <half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200>
971  ret <8 x half> %3
972}
973
974define arm_aapcs_vfpcc <8 x half> @vcvt_u16_inf(<8 x i16> %0) {
975; CHECK-LABEL: vcvt_u16_inf:
976; CHECK:       @ %bb.0:
977; CHECK-NEXT:    vmov.i16 q1, #0x400
978; CHECK-NEXT:    vcvt.f16.u16 q0, q0
979; CHECK-NEXT:    vmul.f16 q0, q0, q1
980; CHECK-NEXT:    bx lr
981  %2 = uitofp <8 x i16> %0 to <8 x half>
982  %3 = fmul <8 x half> %2, <half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400>
983  ret <8 x half> %3
984}
985
986define arm_aapcs_vfpcc <8 x half> @vcvt_s16_inf(<8 x i16> %0) {
987; CHECK-LABEL: vcvt_s16_inf:
988; CHECK:       @ %bb.0:
989; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #14
990; CHECK-NEXT:    bx lr
991  %2 = sitofp <8 x i16> %0 to <8 x half>
992  %3 = fmul <8 x half> %2, <half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400>
993  ret <8 x half> %3
994}
995
996define arm_aapcs_vfpcc <4 x float> @vcvt_bad_imm(<4 x i32> %0) {
997; CHECK-LABEL: vcvt_bad_imm:
998; CHECK:       @ %bb.0:
999; CHECK-NEXT:    movw r0, #2048
1000; CHECK-NEXT:    vcvt.f32.s32 q0, q0
1001; CHECK-NEXT:    movt r0, #15104
1002; CHECK-NEXT:    vmul.f32 q0, q0, r0
1003; CHECK-NEXT:    bx lr
1004  %2 = sitofp <4 x i32> %0 to <4 x float>
1005  %3 = fmul <4 x float> %2, <float 0x3F60010000000000, float 0x3F60010000000000, float 0x3F60010000000000, float 0x3F60010000000000>
1006  ret <4 x float> %3
1007}
1008
1009define arm_aapcs_vfpcc <4 x float> @vcvt_negative(<4 x i32> %0) {
1010; CHECK-LABEL: vcvt_negative:
1011; CHECK:       @ %bb.0:
1012; CHECK-NEXT:    vmov.i32 q1, #0xb8000000
1013; CHECK-NEXT:    vcvt.f32.s32 q0, q0
1014; CHECK-NEXT:    vmul.f32 q0, q0, q1
1015; CHECK-NEXT:    bx lr
1016  %2 = sitofp <4 x i32> %0 to <4 x float>
1017  %3 = fmul <4 x float> %2, <float 0xBF00000000000000, float 0xBF00000000000000, float 0xBF00000000000000, float 0xBF00000000000000>
1018  ret <4 x float> %3
1019}
1020
1021define arm_aapcs_vfpcc <4 x float> @vcvt_negative2(<4 x i32> %0) {
1022; CHECK-LABEL: vcvt_negative2:
1023; CHECK:       @ %bb.0:
1024; CHECK-NEXT:    vmov.i32 q1, #0xb0000000
1025; CHECK-NEXT:    vcvt.f32.s32 q0, q0
1026; CHECK-NEXT:    vmul.f32 q0, q0, q1
1027; CHECK-NEXT:    bx lr
1028  %2 = sitofp <4 x i32> %0 to <4 x float>
1029  %3 = fmul <4 x float> %2, <float 0xBE00000000000000, float 0xBE00000000000000, float 0xBE00000000000000, float 0xBE00000000000000>
1030  ret <4 x float> %3
1031}
1032