xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll (revision 90f24bef47227d58f2ccdcc481ca22eff32248ca) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
3
4define arm_aapcs_vfpcc <4 x i32> @vcmp_eq_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
5; CHECK-LABEL: vcmp_eq_v4i32:
6; CHECK:       @ %bb.0: @ %entry
7; CHECK-NEXT:    vcmp.i32 eq, q0, r0
8; CHECK-NEXT:    vpsel q0, q1, q2
9; CHECK-NEXT:    bx lr
10entry:
11  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
12  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
13  %c = icmp eq <4 x i32> %src, %sp
14  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
15  ret <4 x i32> %s
16}
17
18define arm_aapcs_vfpcc <4 x i32> @vcmp_ne_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
19; CHECK-LABEL: vcmp_ne_v4i32:
20; CHECK:       @ %bb.0: @ %entry
21; CHECK-NEXT:    vcmp.i32 ne, q0, r0
22; CHECK-NEXT:    vpsel q0, q1, q2
23; CHECK-NEXT:    bx lr
24entry:
25  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
26  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
27  %c = icmp ne <4 x i32> %src, %sp
28  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
29  ret <4 x i32> %s
30}
31
32define arm_aapcs_vfpcc <4 x i32> @vcmp_sgt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
33; CHECK-LABEL: vcmp_sgt_v4i32:
34; CHECK:       @ %bb.0: @ %entry
35; CHECK-NEXT:    vcmp.s32 gt, q0, r0
36; CHECK-NEXT:    vpsel q0, q1, q2
37; CHECK-NEXT:    bx lr
38entry:
39  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
40  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
41  %c = icmp sgt <4 x i32> %src, %sp
42  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
43  ret <4 x i32> %s
44}
45
46define arm_aapcs_vfpcc <4 x i32> @vcmp_sge_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
47; CHECK-LABEL: vcmp_sge_v4i32:
48; CHECK:       @ %bb.0: @ %entry
49; CHECK-NEXT:    vcmp.s32 ge, q0, r0
50; CHECK-NEXT:    vpsel q0, q1, q2
51; CHECK-NEXT:    bx lr
52entry:
53  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
54  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
55  %c = icmp sge <4 x i32> %src, %sp
56  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
57  ret <4 x i32> %s
58}
59
60define arm_aapcs_vfpcc <4 x i32> @vcmp_slt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
61; CHECK-LABEL: vcmp_slt_v4i32:
62; CHECK:       @ %bb.0: @ %entry
63; CHECK-NEXT:    vcmp.s32 lt, q0, r0
64; CHECK-NEXT:    vpsel q0, q1, q2
65; CHECK-NEXT:    bx lr
66entry:
67  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
68  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
69  %c = icmp slt <4 x i32> %src, %sp
70  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
71  ret <4 x i32> %s
72}
73
74define arm_aapcs_vfpcc <4 x i32> @vcmp_sle_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
75; CHECK-LABEL: vcmp_sle_v4i32:
76; CHECK:       @ %bb.0: @ %entry
77; CHECK-NEXT:    vcmp.s32 le, q0, r0
78; CHECK-NEXT:    vpsel q0, q1, q2
79; CHECK-NEXT:    bx lr
80entry:
81  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
82  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
83  %c = icmp sle <4 x i32> %src, %sp
84  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
85  ret <4 x i32> %s
86}
87
88define arm_aapcs_vfpcc <4 x i32> @vcmp_ugt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
89; CHECK-LABEL: vcmp_ugt_v4i32:
90; CHECK:       @ %bb.0: @ %entry
91; CHECK-NEXT:    vcmp.u32 hi, q0, r0
92; CHECK-NEXT:    vpsel q0, q1, q2
93; CHECK-NEXT:    bx lr
94entry:
95  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
96  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
97  %c = icmp ugt <4 x i32> %src, %sp
98  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
99  ret <4 x i32> %s
100}
101
102define arm_aapcs_vfpcc <4 x i32> @vcmp_uge_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
103; CHECK-LABEL: vcmp_uge_v4i32:
104; CHECK:       @ %bb.0: @ %entry
105; CHECK-NEXT:    vcmp.u32 cs, q0, r0
106; CHECK-NEXT:    vpsel q0, q1, q2
107; CHECK-NEXT:    bx lr
108entry:
109  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
110  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
111  %c = icmp uge <4 x i32> %src, %sp
112  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
113  ret <4 x i32> %s
114}
115
116define arm_aapcs_vfpcc <4 x i32> @vcmp_ult_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
117; CHECK-LABEL: vcmp_ult_v4i32:
118; CHECK:       @ %bb.0: @ %entry
119; CHECK-NEXT:    vdup.32 q3, r0
120; CHECK-NEXT:    vcmp.u32 hi, q3, q0
121; CHECK-NEXT:    vpsel q0, q1, q2
122; CHECK-NEXT:    bx lr
123entry:
124  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
125  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
126  %c = icmp ult <4 x i32> %src, %sp
127  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
128  ret <4 x i32> %s
129}
130
131define arm_aapcs_vfpcc <4 x i32> @vcmp_ule_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
132; CHECK-LABEL: vcmp_ule_v4i32:
133; CHECK:       @ %bb.0: @ %entry
134; CHECK-NEXT:    vdup.32 q3, r0
135; CHECK-NEXT:    vcmp.u32 cs, q3, q0
136; CHECK-NEXT:    vpsel q0, q1, q2
137; CHECK-NEXT:    bx lr
138entry:
139  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
140  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
141  %c = icmp ule <4 x i32> %src, %sp
142  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
143  ret <4 x i32> %s
144}
145
146
147define arm_aapcs_vfpcc <8 x i16> @vcmp_eq_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
148; CHECK-LABEL: vcmp_eq_v8i16:
149; CHECK:       @ %bb.0: @ %entry
150; CHECK-NEXT:    vcmp.i16 eq, q0, r0
151; CHECK-NEXT:    vpsel q0, q1, q2
152; CHECK-NEXT:    bx lr
153entry:
154  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
155  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
156  %c = icmp eq <8 x i16> %src, %sp
157  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
158  ret <8 x i16> %s
159}
160
161define arm_aapcs_vfpcc <8 x i16> @vcmp_ne_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
162; CHECK-LABEL: vcmp_ne_v8i16:
163; CHECK:       @ %bb.0: @ %entry
164; CHECK-NEXT:    vcmp.i16 ne, q0, r0
165; CHECK-NEXT:    vpsel q0, q1, q2
166; CHECK-NEXT:    bx lr
167entry:
168  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
169  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
170  %c = icmp ne <8 x i16> %src, %sp
171  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
172  ret <8 x i16> %s
173}
174
175define arm_aapcs_vfpcc <8 x i16> @vcmp_sgt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
176; CHECK-LABEL: vcmp_sgt_v8i16:
177; CHECK:       @ %bb.0: @ %entry
178; CHECK-NEXT:    vcmp.s16 gt, q0, r0
179; CHECK-NEXT:    vpsel q0, q1, q2
180; CHECK-NEXT:    bx lr
181entry:
182  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
183  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
184  %c = icmp sgt <8 x i16> %src, %sp
185  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
186  ret <8 x i16> %s
187}
188
189define arm_aapcs_vfpcc <8 x i16> @vcmp_sge_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
190; CHECK-LABEL: vcmp_sge_v8i16:
191; CHECK:       @ %bb.0: @ %entry
192; CHECK-NEXT:    vcmp.s16 ge, q0, r0
193; CHECK-NEXT:    vpsel q0, q1, q2
194; CHECK-NEXT:    bx lr
195entry:
196  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
197  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
198  %c = icmp sge <8 x i16> %src, %sp
199  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
200  ret <8 x i16> %s
201}
202
203define arm_aapcs_vfpcc <8 x i16> @vcmp_slt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
204; CHECK-LABEL: vcmp_slt_v8i16:
205; CHECK:       @ %bb.0: @ %entry
206; CHECK-NEXT:    vcmp.s16 lt, q0, r0
207; CHECK-NEXT:    vpsel q0, q1, q2
208; CHECK-NEXT:    bx lr
209entry:
210  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
211  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
212  %c = icmp slt <8 x i16> %src, %sp
213  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
214  ret <8 x i16> %s
215}
216
217define arm_aapcs_vfpcc <8 x i16> @vcmp_sle_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
218; CHECK-LABEL: vcmp_sle_v8i16:
219; CHECK:       @ %bb.0: @ %entry
220; CHECK-NEXT:    vcmp.s16 le, q0, r0
221; CHECK-NEXT:    vpsel q0, q1, q2
222; CHECK-NEXT:    bx lr
223entry:
224  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
225  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
226  %c = icmp sle <8 x i16> %src, %sp
227  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
228  ret <8 x i16> %s
229}
230
231define arm_aapcs_vfpcc <8 x i16> @vcmp_ugt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
232; CHECK-LABEL: vcmp_ugt_v8i16:
233; CHECK:       @ %bb.0: @ %entry
234; CHECK-NEXT:    vcmp.u16 hi, q0, r0
235; CHECK-NEXT:    vpsel q0, q1, q2
236; CHECK-NEXT:    bx lr
237entry:
238  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
239  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
240  %c = icmp ugt <8 x i16> %src, %sp
241  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
242  ret <8 x i16> %s
243}
244
245define arm_aapcs_vfpcc <8 x i16> @vcmp_uge_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
246; CHECK-LABEL: vcmp_uge_v8i16:
247; CHECK:       @ %bb.0: @ %entry
248; CHECK-NEXT:    vcmp.u16 cs, q0, r0
249; CHECK-NEXT:    vpsel q0, q1, q2
250; CHECK-NEXT:    bx lr
251entry:
252  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
253  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
254  %c = icmp uge <8 x i16> %src, %sp
255  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
256  ret <8 x i16> %s
257}
258
259define arm_aapcs_vfpcc <8 x i16> @vcmp_ult_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
260; CHECK-LABEL: vcmp_ult_v8i16:
261; CHECK:       @ %bb.0: @ %entry
262; CHECK-NEXT:    vdup.16 q3, r0
263; CHECK-NEXT:    vcmp.u16 hi, q3, q0
264; CHECK-NEXT:    vpsel q0, q1, q2
265; CHECK-NEXT:    bx lr
266entry:
267  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
268  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
269  %c = icmp ult <8 x i16> %src, %sp
270  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
271  ret <8 x i16> %s
272}
273
274define arm_aapcs_vfpcc <8 x i16> @vcmp_ule_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
275; CHECK-LABEL: vcmp_ule_v8i16:
276; CHECK:       @ %bb.0: @ %entry
277; CHECK-NEXT:    vdup.16 q3, r0
278; CHECK-NEXT:    vcmp.u16 cs, q3, q0
279; CHECK-NEXT:    vpsel q0, q1, q2
280; CHECK-NEXT:    bx lr
281entry:
282  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
283  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
284  %c = icmp ule <8 x i16> %src, %sp
285  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
286  ret <8 x i16> %s
287}
288
289
290define arm_aapcs_vfpcc <16 x i8> @vcmp_eq_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
291; CHECK-LABEL: vcmp_eq_v16i8:
292; CHECK:       @ %bb.0: @ %entry
293; CHECK-NEXT:    vcmp.i8 eq, q0, r0
294; CHECK-NEXT:    vpsel q0, q1, q2
295; CHECK-NEXT:    bx lr
296entry:
297  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
298  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
299  %c = icmp eq <16 x i8> %src, %sp
300  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
301  ret <16 x i8> %s
302}
303
304define arm_aapcs_vfpcc <16 x i8> @vcmp_ne_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
305; CHECK-LABEL: vcmp_ne_v16i8:
306; CHECK:       @ %bb.0: @ %entry
307; CHECK-NEXT:    vcmp.i8 ne, q0, r0
308; CHECK-NEXT:    vpsel q0, q1, q2
309; CHECK-NEXT:    bx lr
310entry:
311  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
312  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
313  %c = icmp ne <16 x i8> %src, %sp
314  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
315  ret <16 x i8> %s
316}
317
318define arm_aapcs_vfpcc <16 x i8> @vcmp_sgt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
319; CHECK-LABEL: vcmp_sgt_v16i8:
320; CHECK:       @ %bb.0: @ %entry
321; CHECK-NEXT:    vcmp.s8 gt, q0, r0
322; CHECK-NEXT:    vpsel q0, q1, q2
323; CHECK-NEXT:    bx lr
324entry:
325  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
326  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
327  %c = icmp sgt <16 x i8> %src, %sp
328  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
329  ret <16 x i8> %s
330}
331
332define arm_aapcs_vfpcc <16 x i8> @vcmp_sge_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
333; CHECK-LABEL: vcmp_sge_v16i8:
334; CHECK:       @ %bb.0: @ %entry
335; CHECK-NEXT:    vcmp.s8 ge, q0, r0
336; CHECK-NEXT:    vpsel q0, q1, q2
337; CHECK-NEXT:    bx lr
338entry:
339  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
340  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
341  %c = icmp sge <16 x i8> %src, %sp
342  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
343  ret <16 x i8> %s
344}
345
346define arm_aapcs_vfpcc <16 x i8> @vcmp_slt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
347; CHECK-LABEL: vcmp_slt_v16i8:
348; CHECK:       @ %bb.0: @ %entry
349; CHECK-NEXT:    vcmp.s8 lt, q0, r0
350; CHECK-NEXT:    vpsel q0, q1, q2
351; CHECK-NEXT:    bx lr
352entry:
353  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
354  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
355  %c = icmp slt <16 x i8> %src, %sp
356  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
357  ret <16 x i8> %s
358}
359
360define arm_aapcs_vfpcc <16 x i8> @vcmp_sle_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
361; CHECK-LABEL: vcmp_sle_v16i8:
362; CHECK:       @ %bb.0: @ %entry
363; CHECK-NEXT:    vcmp.s8 le, q0, r0
364; CHECK-NEXT:    vpsel q0, q1, q2
365; CHECK-NEXT:    bx lr
366entry:
367  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
368  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
369  %c = icmp sle <16 x i8> %src, %sp
370  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
371  ret <16 x i8> %s
372}
373
374define arm_aapcs_vfpcc <16 x i8> @vcmp_ugt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
375; CHECK-LABEL: vcmp_ugt_v16i8:
376; CHECK:       @ %bb.0: @ %entry
377; CHECK-NEXT:    vcmp.u8 hi, q0, r0
378; CHECK-NEXT:    vpsel q0, q1, q2
379; CHECK-NEXT:    bx lr
380entry:
381  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
382  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
383  %c = icmp ugt <16 x i8> %src, %sp
384  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
385  ret <16 x i8> %s
386}
387
388define arm_aapcs_vfpcc <16 x i8> @vcmp_uge_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
389; CHECK-LABEL: vcmp_uge_v16i8:
390; CHECK:       @ %bb.0: @ %entry
391; CHECK-NEXT:    vcmp.u8 cs, q0, r0
392; CHECK-NEXT:    vpsel q0, q1, q2
393; CHECK-NEXT:    bx lr
394entry:
395  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
396  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
397  %c = icmp uge <16 x i8> %src, %sp
398  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
399  ret <16 x i8> %s
400}
401
402define arm_aapcs_vfpcc <16 x i8> @vcmp_ult_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
403; CHECK-LABEL: vcmp_ult_v16i8:
404; CHECK:       @ %bb.0: @ %entry
405; CHECK-NEXT:    vdup.8 q3, r0
406; CHECK-NEXT:    vcmp.u8 hi, q3, q0
407; CHECK-NEXT:    vpsel q0, q1, q2
408; CHECK-NEXT:    bx lr
409entry:
410  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
411  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
412  %c = icmp ult <16 x i8> %src, %sp
413  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
414  ret <16 x i8> %s
415}
416
417define arm_aapcs_vfpcc <16 x i8> @vcmp_ule_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
418; CHECK-LABEL: vcmp_ule_v16i8:
419; CHECK:       @ %bb.0: @ %entry
420; CHECK-NEXT:    vdup.8 q3, r0
421; CHECK-NEXT:    vcmp.u8 cs, q3, q0
422; CHECK-NEXT:    vpsel q0, q1, q2
423; CHECK-NEXT:    bx lr
424entry:
425  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
426  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
427  %c = icmp ule <16 x i8> %src, %sp
428  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
429  ret <16 x i8> %s
430}
431
432
433define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, i64 %src2, <2 x i64> %a, <2 x i64> %b) {
434; CHECK-LABEL: vcmp_eq_v2i64:
435; CHECK:       @ %bb.0: @ %entry
436; CHECK-NEXT:    vmov r2, r3, d0
437; CHECK-NEXT:    eors r3, r1
438; CHECK-NEXT:    eors r2, r0
439; CHECK-NEXT:    orrs r2, r3
440; CHECK-NEXT:    mov.w r3, #0
441; CHECK-NEXT:    csetm r2, eq
442; CHECK-NEXT:    bfi r3, r2, #0, #8
443; CHECK-NEXT:    vmov r12, r2, d1
444; CHECK-NEXT:    eors r1, r2
445; CHECK-NEXT:    eor.w r0, r0, r12
446; CHECK-NEXT:    orrs r0, r1
447; CHECK-NEXT:    csetm r0, eq
448; CHECK-NEXT:    bfi r3, r0, #8, #8
449; CHECK-NEXT:    vmsr p0, r3
450; CHECK-NEXT:    vpsel q0, q1, q2
451; CHECK-NEXT:    bx lr
452entry:
453  %i = insertelement <2 x i64> undef, i64 %src2, i32 0
454  %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer
455  %c = icmp eq <2 x i64> %src, %sp
456  %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b
457  ret <2 x i64> %s
458}
459
460define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, i64 %src2, <2 x i32> %a, <2 x i32> %b) {
461; CHECK-LABEL: vcmp_eq_v2i32:
462; CHECK:       @ %bb.0: @ %entry
463; CHECK-NEXT:    vmov r2, r3, d0
464; CHECK-NEXT:    eors r3, r1
465; CHECK-NEXT:    eors r2, r0
466; CHECK-NEXT:    orrs r2, r3
467; CHECK-NEXT:    mov.w r3, #0
468; CHECK-NEXT:    csetm r2, eq
469; CHECK-NEXT:    bfi r3, r2, #0, #8
470; CHECK-NEXT:    vmov r12, r2, d1
471; CHECK-NEXT:    eors r1, r2
472; CHECK-NEXT:    eor.w r0, r0, r12
473; CHECK-NEXT:    orrs r0, r1
474; CHECK-NEXT:    csetm r0, eq
475; CHECK-NEXT:    bfi r3, r0, #8, #8
476; CHECK-NEXT:    vmsr p0, r3
477; CHECK-NEXT:    vpsel q0, q1, q2
478; CHECK-NEXT:    bx lr
479entry:
480  %i = insertelement <2 x i64> undef, i64 %src2, i32 0
481  %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer
482  %c = icmp eq <2 x i64> %src, %sp
483  %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b
484  ret <2 x i32> %s
485}
486
487define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
488; CHECK-LABEL: vcmp_multi_v2i32:
489; CHECK:       @ %bb.0:
490; CHECK-NEXT:    vmov r0, r1, d0
491; CHECK-NEXT:    movs r2, #0
492; CHECK-NEXT:    orrs r0, r1
493; CHECK-NEXT:    csetm r1, eq
494; CHECK-NEXT:    movs r0, #0
495; CHECK-NEXT:    bfi r2, r1, #0, #8
496; CHECK-NEXT:    vmov r1, r3, d1
497; CHECK-NEXT:    vmov.i32 q0, #0x0
498; CHECK-NEXT:    orrs r1, r3
499; CHECK-NEXT:    csetm r1, eq
500; CHECK-NEXT:    bfi r2, r1, #8, #8
501; CHECK-NEXT:    vmsr p0, r2
502; CHECK-NEXT:    vmov r2, s4
503; CHECK-NEXT:    vpsel q0, q0, q2
504; CHECK-NEXT:    vmov r1, s0
505; CHECK-NEXT:    cmp r2, #0
506; CHECK-NEXT:    cset r2, ne
507; CHECK-NEXT:    cmp r1, #0
508; CHECK-NEXT:    csel r12, zr, r2, eq
509; CHECK-NEXT:    vmov r2, s8
510; CHECK-NEXT:    asrs r3, r1, #31
511; CHECK-NEXT:    subs r1, r1, r2
512; CHECK-NEXT:    sbcs.w r1, r3, r2, asr #31
513; CHECK-NEXT:    vmov r2, s6
514; CHECK-NEXT:    csel r1, zr, r12, ge
515; CHECK-NEXT:    rsbs r1, r1, #0
516; CHECK-NEXT:    bfi r0, r1, #0, #8
517; CHECK-NEXT:    vmov r1, s2
518; CHECK-NEXT:    cmp r2, #0
519; CHECK-NEXT:    cset r2, ne
520; CHECK-NEXT:    cmp r1, #0
521; CHECK-NEXT:    csel r12, zr, r2, eq
522; CHECK-NEXT:    vmov r2, s10
523; CHECK-NEXT:    asrs r3, r1, #31
524; CHECK-NEXT:    subs r1, r1, r2
525; CHECK-NEXT:    sbcs.w r1, r3, r2, asr #31
526; CHECK-NEXT:    csel r1, zr, r12, ge
527; CHECK-NEXT:    rsbs r1, r1, #0
528; CHECK-NEXT:    bfi r0, r1, #8, #8
529; CHECK-NEXT:    vmsr p0, r0
530; CHECK-NEXT:    vpsel q0, q2, q0
531; CHECK-NEXT:    bx lr
532  %a4 = icmp eq <2 x i64> %a, zeroinitializer
533  %a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c
534  %a6 = icmp ne <2 x i32> %b, zeroinitializer
535  %a7 = icmp slt <2 x i32> %a5, %c
536  %a8 = icmp ne <2 x i32> %a5, zeroinitializer
537  %a9 = and <2 x i1> %a6, %a8
538  %a10 = and <2 x i1> %a7, %a9
539  %a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5
540  ret <2 x i32> %a11
541}
542
543; Reversed
544
545define arm_aapcs_vfpcc <4 x i32> @vcmp_r_eq_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
546; CHECK-LABEL: vcmp_r_eq_v4i32:
547; CHECK:       @ %bb.0: @ %entry
548; CHECK-NEXT:    vcmp.i32 eq, q0, r0
549; CHECK-NEXT:    vpsel q0, q1, q2
550; CHECK-NEXT:    bx lr
551entry:
552  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
553  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
554  %c = icmp eq <4 x i32> %sp, %src
555  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
556  ret <4 x i32> %s
557}
558
559define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ne_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
560; CHECK-LABEL: vcmp_r_ne_v4i32:
561; CHECK:       @ %bb.0: @ %entry
562; CHECK-NEXT:    vcmp.i32 ne, q0, r0
563; CHECK-NEXT:    vpsel q0, q1, q2
564; CHECK-NEXT:    bx lr
565entry:
566  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
567  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
568  %c = icmp ne <4 x i32> %sp, %src
569  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
570  ret <4 x i32> %s
571}
572
573define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sgt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
574; CHECK-LABEL: vcmp_r_sgt_v4i32:
575; CHECK:       @ %bb.0: @ %entry
576; CHECK-NEXT:    vcmp.s32 lt, q0, r0
577; CHECK-NEXT:    vpsel q0, q1, q2
578; CHECK-NEXT:    bx lr
579entry:
580  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
581  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
582  %c = icmp sgt <4 x i32> %sp, %src
583  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
584  ret <4 x i32> %s
585}
586
587define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sge_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
588; CHECK-LABEL: vcmp_r_sge_v4i32:
589; CHECK:       @ %bb.0: @ %entry
590; CHECK-NEXT:    vcmp.s32 le, q0, r0
591; CHECK-NEXT:    vpsel q0, q1, q2
592; CHECK-NEXT:    bx lr
593entry:
594  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
595  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
596  %c = icmp sge <4 x i32> %sp, %src
597  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
598  ret <4 x i32> %s
599}
600
601define arm_aapcs_vfpcc <4 x i32> @vcmp_r_slt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
602; CHECK-LABEL: vcmp_r_slt_v4i32:
603; CHECK:       @ %bb.0: @ %entry
604; CHECK-NEXT:    vcmp.s32 gt, q0, r0
605; CHECK-NEXT:    vpsel q0, q1, q2
606; CHECK-NEXT:    bx lr
607entry:
608  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
609  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
610  %c = icmp slt <4 x i32> %sp, %src
611  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
612  ret <4 x i32> %s
613}
614
615define arm_aapcs_vfpcc <4 x i32> @vcmp_r_sle_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
616; CHECK-LABEL: vcmp_r_sle_v4i32:
617; CHECK:       @ %bb.0: @ %entry
618; CHECK-NEXT:    vcmp.s32 ge, q0, r0
619; CHECK-NEXT:    vpsel q0, q1, q2
620; CHECK-NEXT:    bx lr
621entry:
622  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
623  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
624  %c = icmp sle <4 x i32> %sp, %src
625  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
626  ret <4 x i32> %s
627}
628
629define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ugt_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
630; CHECK-LABEL: vcmp_r_ugt_v4i32:
631; CHECK:       @ %bb.0: @ %entry
632; CHECK-NEXT:    vdup.32 q3, r0
633; CHECK-NEXT:    vcmp.u32 hi, q3, q0
634; CHECK-NEXT:    vpsel q0, q1, q2
635; CHECK-NEXT:    bx lr
636entry:
637  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
638  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
639  %c = icmp ugt <4 x i32> %sp, %src
640  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
641  ret <4 x i32> %s
642}
643
644define arm_aapcs_vfpcc <4 x i32> @vcmp_r_uge_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
645; CHECK-LABEL: vcmp_r_uge_v4i32:
646; CHECK:       @ %bb.0: @ %entry
647; CHECK-NEXT:    vdup.32 q3, r0
648; CHECK-NEXT:    vcmp.u32 cs, q3, q0
649; CHECK-NEXT:    vpsel q0, q1, q2
650; CHECK-NEXT:    bx lr
651entry:
652  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
653  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
654  %c = icmp uge <4 x i32> %sp, %src
655  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
656  ret <4 x i32> %s
657}
658
659define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ult_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
660; CHECK-LABEL: vcmp_r_ult_v4i32:
661; CHECK:       @ %bb.0: @ %entry
662; CHECK-NEXT:    vcmp.u32 hi, q0, r0
663; CHECK-NEXT:    vpsel q0, q1, q2
664; CHECK-NEXT:    bx lr
665entry:
666  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
667  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
668  %c = icmp ult <4 x i32> %sp, %src
669  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
670  ret <4 x i32> %s
671}
672
673define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ule_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
674; CHECK-LABEL: vcmp_r_ule_v4i32:
675; CHECK:       @ %bb.0: @ %entry
676; CHECK-NEXT:    vcmp.u32 cs, q0, r0
677; CHECK-NEXT:    vpsel q0, q1, q2
678; CHECK-NEXT:    bx lr
679entry:
680  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
681  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
682  %c = icmp ule <4 x i32> %sp, %src
683  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
684  ret <4 x i32> %s
685}
686
687
688define arm_aapcs_vfpcc <8 x i16> @vcmp_r_eq_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
689; CHECK-LABEL: vcmp_r_eq_v8i16:
690; CHECK:       @ %bb.0: @ %entry
691; CHECK-NEXT:    vcmp.i16 eq, q0, r0
692; CHECK-NEXT:    vpsel q0, q1, q2
693; CHECK-NEXT:    bx lr
694entry:
695  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
696  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
697  %c = icmp eq <8 x i16> %sp, %src
698  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
699  ret <8 x i16> %s
700}
701
702define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ne_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
703; CHECK-LABEL: vcmp_r_ne_v8i16:
704; CHECK:       @ %bb.0: @ %entry
705; CHECK-NEXT:    vcmp.i16 ne, q0, r0
706; CHECK-NEXT:    vpsel q0, q1, q2
707; CHECK-NEXT:    bx lr
708entry:
709  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
710  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
711  %c = icmp ne <8 x i16> %sp, %src
712  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
713  ret <8 x i16> %s
714}
715
716define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sgt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
717; CHECK-LABEL: vcmp_r_sgt_v8i16:
718; CHECK:       @ %bb.0: @ %entry
719; CHECK-NEXT:    vcmp.s16 lt, q0, r0
720; CHECK-NEXT:    vpsel q0, q1, q2
721; CHECK-NEXT:    bx lr
722entry:
723  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
724  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
725  %c = icmp sgt <8 x i16> %sp, %src
726  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
727  ret <8 x i16> %s
728}
729
730define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sge_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
731; CHECK-LABEL: vcmp_r_sge_v8i16:
732; CHECK:       @ %bb.0: @ %entry
733; CHECK-NEXT:    vcmp.s16 le, q0, r0
734; CHECK-NEXT:    vpsel q0, q1, q2
735; CHECK-NEXT:    bx lr
736entry:
737  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
738  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
739  %c = icmp sge <8 x i16> %sp, %src
740  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
741  ret <8 x i16> %s
742}
743
744define arm_aapcs_vfpcc <8 x i16> @vcmp_r_slt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
745; CHECK-LABEL: vcmp_r_slt_v8i16:
746; CHECK:       @ %bb.0: @ %entry
747; CHECK-NEXT:    vcmp.s16 gt, q0, r0
748; CHECK-NEXT:    vpsel q0, q1, q2
749; CHECK-NEXT:    bx lr
750entry:
751  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
752  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
753  %c = icmp slt <8 x i16> %sp, %src
754  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
755  ret <8 x i16> %s
756}
757
758define arm_aapcs_vfpcc <8 x i16> @vcmp_r_sle_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
759; CHECK-LABEL: vcmp_r_sle_v8i16:
760; CHECK:       @ %bb.0: @ %entry
761; CHECK-NEXT:    vcmp.s16 ge, q0, r0
762; CHECK-NEXT:    vpsel q0, q1, q2
763; CHECK-NEXT:    bx lr
764entry:
765  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
766  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
767  %c = icmp sle <8 x i16> %sp, %src
768  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
769  ret <8 x i16> %s
770}
771
772define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ugt_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
773; CHECK-LABEL: vcmp_r_ugt_v8i16:
774; CHECK:       @ %bb.0: @ %entry
775; CHECK-NEXT:    vdup.16 q3, r0
776; CHECK-NEXT:    vcmp.u16 hi, q3, q0
777; CHECK-NEXT:    vpsel q0, q1, q2
778; CHECK-NEXT:    bx lr
779entry:
780  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
781  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
782  %c = icmp ugt <8 x i16> %sp, %src
783  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
784  ret <8 x i16> %s
785}
786
787define arm_aapcs_vfpcc <8 x i16> @vcmp_r_uge_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
788; CHECK-LABEL: vcmp_r_uge_v8i16:
789; CHECK:       @ %bb.0: @ %entry
790; CHECK-NEXT:    vdup.16 q3, r0
791; CHECK-NEXT:    vcmp.u16 cs, q3, q0
792; CHECK-NEXT:    vpsel q0, q1, q2
793; CHECK-NEXT:    bx lr
794entry:
795  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
796  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
797  %c = icmp uge <8 x i16> %sp, %src
798  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
799  ret <8 x i16> %s
800}
801
802define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ult_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
803; CHECK-LABEL: vcmp_r_ult_v8i16:
804; CHECK:       @ %bb.0: @ %entry
805; CHECK-NEXT:    vcmp.u16 hi, q0, r0
806; CHECK-NEXT:    vpsel q0, q1, q2
807; CHECK-NEXT:    bx lr
808entry:
809  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
810  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
811  %c = icmp ult <8 x i16> %sp, %src
812  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
813  ret <8 x i16> %s
814}
815
816define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ule_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
817; CHECK-LABEL: vcmp_r_ule_v8i16:
818; CHECK:       @ %bb.0: @ %entry
819; CHECK-NEXT:    vcmp.u16 cs, q0, r0
820; CHECK-NEXT:    vpsel q0, q1, q2
821; CHECK-NEXT:    bx lr
822entry:
823  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
824  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
825  %c = icmp ule <8 x i16> %sp, %src
826  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
827  ret <8 x i16> %s
828}
829
830
831define arm_aapcs_vfpcc <16 x i8> @vcmp_r_eq_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
832; CHECK-LABEL: vcmp_r_eq_v16i8:
833; CHECK:       @ %bb.0: @ %entry
834; CHECK-NEXT:    vcmp.i8 eq, q0, r0
835; CHECK-NEXT:    vpsel q0, q1, q2
836; CHECK-NEXT:    bx lr
837entry:
838  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
839  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
840  %c = icmp eq <16 x i8> %sp, %src
841  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
842  ret <16 x i8> %s
843}
844
845define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ne_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
846; CHECK-LABEL: vcmp_r_ne_v16i8:
847; CHECK:       @ %bb.0: @ %entry
848; CHECK-NEXT:    vcmp.i8 ne, q0, r0
849; CHECK-NEXT:    vpsel q0, q1, q2
850; CHECK-NEXT:    bx lr
851entry:
852  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
853  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
854  %c = icmp ne <16 x i8> %sp, %src
855  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
856  ret <16 x i8> %s
857}
858
859define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sgt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
860; CHECK-LABEL: vcmp_r_sgt_v16i8:
861; CHECK:       @ %bb.0: @ %entry
862; CHECK-NEXT:    vcmp.s8 lt, q0, r0
863; CHECK-NEXT:    vpsel q0, q1, q2
864; CHECK-NEXT:    bx lr
865entry:
866  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
867  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
868  %c = icmp sgt <16 x i8> %sp, %src
869  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
870  ret <16 x i8> %s
871}
872
873define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sge_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
874; CHECK-LABEL: vcmp_r_sge_v16i8:
875; CHECK:       @ %bb.0: @ %entry
876; CHECK-NEXT:    vcmp.s8 le, q0, r0
877; CHECK-NEXT:    vpsel q0, q1, q2
878; CHECK-NEXT:    bx lr
879entry:
880  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
881  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
882  %c = icmp sge <16 x i8> %sp, %src
883  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
884  ret <16 x i8> %s
885}
886
887define arm_aapcs_vfpcc <16 x i8> @vcmp_r_slt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
888; CHECK-LABEL: vcmp_r_slt_v16i8:
889; CHECK:       @ %bb.0: @ %entry
890; CHECK-NEXT:    vcmp.s8 gt, q0, r0
891; CHECK-NEXT:    vpsel q0, q1, q2
892; CHECK-NEXT:    bx lr
893entry:
894  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
895  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
896  %c = icmp slt <16 x i8> %sp, %src
897  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
898  ret <16 x i8> %s
899}
900
901define arm_aapcs_vfpcc <16 x i8> @vcmp_r_sle_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
902; CHECK-LABEL: vcmp_r_sle_v16i8:
903; CHECK:       @ %bb.0: @ %entry
904; CHECK-NEXT:    vcmp.s8 ge, q0, r0
905; CHECK-NEXT:    vpsel q0, q1, q2
906; CHECK-NEXT:    bx lr
907entry:
908  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
909  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
910  %c = icmp sle <16 x i8> %sp, %src
911  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
912  ret <16 x i8> %s
913}
914
915define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ugt_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
916; CHECK-LABEL: vcmp_r_ugt_v16i8:
917; CHECK:       @ %bb.0: @ %entry
918; CHECK-NEXT:    vdup.8 q3, r0
919; CHECK-NEXT:    vcmp.u8 hi, q3, q0
920; CHECK-NEXT:    vpsel q0, q1, q2
921; CHECK-NEXT:    bx lr
922entry:
923  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
924  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
925  %c = icmp ugt <16 x i8> %sp, %src
926  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
927  ret <16 x i8> %s
928}
929
930define arm_aapcs_vfpcc <16 x i8> @vcmp_r_uge_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
931; CHECK-LABEL: vcmp_r_uge_v16i8:
932; CHECK:       @ %bb.0: @ %entry
933; CHECK-NEXT:    vdup.8 q3, r0
934; CHECK-NEXT:    vcmp.u8 cs, q3, q0
935; CHECK-NEXT:    vpsel q0, q1, q2
936; CHECK-NEXT:    bx lr
937entry:
938  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
939  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
940  %c = icmp uge <16 x i8> %sp, %src
941  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
942  ret <16 x i8> %s
943}
944
945define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ult_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
946; CHECK-LABEL: vcmp_r_ult_v16i8:
947; CHECK:       @ %bb.0: @ %entry
948; CHECK-NEXT:    vcmp.u8 hi, q0, r0
949; CHECK-NEXT:    vpsel q0, q1, q2
950; CHECK-NEXT:    bx lr
951entry:
952  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
953  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
954  %c = icmp ult <16 x i8> %sp, %src
955  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
956  ret <16 x i8> %s
957}
958
959define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ule_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
960; CHECK-LABEL: vcmp_r_ule_v16i8:
961; CHECK:       @ %bb.0: @ %entry
962; CHECK-NEXT:    vcmp.u8 cs, q0, r0
963; CHECK-NEXT:    vpsel q0, q1, q2
964; CHECK-NEXT:    bx lr
965entry:
966  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
967  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
968  %c = icmp ule <16 x i8> %sp, %src
969  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
970  ret <16 x i8> %s
971}
972
973
974define arm_aapcs_vfpcc <2 x i64> @vcmp_r_eq_v2i64(<2 x i64> %src, i64 %src2, <2 x i64> %a, <2 x i64> %b) {
975; CHECK-LABEL: vcmp_r_eq_v2i64:
976; CHECK:       @ %bb.0: @ %entry
977; CHECK-NEXT:    vmov r2, r3, d0
978; CHECK-NEXT:    eors r3, r1
979; CHECK-NEXT:    eors r2, r0
980; CHECK-NEXT:    orrs r2, r3
981; CHECK-NEXT:    mov.w r3, #0
982; CHECK-NEXT:    csetm r2, eq
983; CHECK-NEXT:    bfi r3, r2, #0, #8
984; CHECK-NEXT:    vmov r12, r2, d1
985; CHECK-NEXT:    eors r1, r2
986; CHECK-NEXT:    eor.w r0, r0, r12
987; CHECK-NEXT:    orrs r0, r1
988; CHECK-NEXT:    csetm r0, eq
989; CHECK-NEXT:    bfi r3, r0, #8, #8
990; CHECK-NEXT:    vmsr p0, r3
991; CHECK-NEXT:    vpsel q0, q1, q2
992; CHECK-NEXT:    bx lr
993entry:
994  %i = insertelement <2 x i64> undef, i64 %src2, i32 0
995  %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer
996  %c = icmp eq <2 x i64> %sp, %src
997  %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b
998  ret <2 x i64> %s
999}
1000
1001define arm_aapcs_vfpcc <2 x i32> @vcmp_r_eq_v2i32(<2 x i64> %src, i64 %src2, <2 x i32> %a, <2 x i32> %b) {
1002; CHECK-LABEL: vcmp_r_eq_v2i32:
1003; CHECK:       @ %bb.0: @ %entry
1004; CHECK-NEXT:    vmov r2, r3, d0
1005; CHECK-NEXT:    eors r3, r1
1006; CHECK-NEXT:    eors r2, r0
1007; CHECK-NEXT:    orrs r2, r3
1008; CHECK-NEXT:    mov.w r3, #0
1009; CHECK-NEXT:    csetm r2, eq
1010; CHECK-NEXT:    bfi r3, r2, #0, #8
1011; CHECK-NEXT:    vmov r12, r2, d1
1012; CHECK-NEXT:    eors r1, r2
1013; CHECK-NEXT:    eor.w r0, r0, r12
1014; CHECK-NEXT:    orrs r0, r1
1015; CHECK-NEXT:    csetm r0, eq
1016; CHECK-NEXT:    bfi r3, r0, #8, #8
1017; CHECK-NEXT:    vmsr p0, r3
1018; CHECK-NEXT:    vpsel q0, q1, q2
1019; CHECK-NEXT:    bx lr
1020entry:
1021  %i = insertelement <2 x i64> undef, i64 %src2, i32 0
1022  %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer
1023  %c = icmp eq <2 x i64> %sp, %src
1024  %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b
1025  ret <2 x i32> %s
1026}
1027
1028define arm_aapcs_vfpcc <2 x i32> @vcmp_r_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
1029; CHECK-LABEL: vcmp_r_multi_v2i32:
1030; CHECK:       @ %bb.0:
1031; CHECK-NEXT:    vmov r0, r1, d0
1032; CHECK-NEXT:    movs r2, #0
1033; CHECK-NEXT:    orrs r0, r1
1034; CHECK-NEXT:    csetm r1, eq
1035; CHECK-NEXT:    movs r0, #0
1036; CHECK-NEXT:    bfi r2, r1, #0, #8
1037; CHECK-NEXT:    vmov r1, r3, d1
1038; CHECK-NEXT:    vmov.i32 q0, #0x0
1039; CHECK-NEXT:    orrs r1, r3
1040; CHECK-NEXT:    csetm r1, eq
1041; CHECK-NEXT:    bfi r2, r1, #8, #8
1042; CHECK-NEXT:    vmsr p0, r2
1043; CHECK-NEXT:    vmov r2, s4
1044; CHECK-NEXT:    vpsel q0, q0, q2
1045; CHECK-NEXT:    vmov r1, s0
1046; CHECK-NEXT:    cmp r2, #0
1047; CHECK-NEXT:    cset r2, ne
1048; CHECK-NEXT:    cmp r1, #0
1049; CHECK-NEXT:    csel r12, zr, r2, eq
1050; CHECK-NEXT:    vmov r2, s8
1051; CHECK-NEXT:    asrs r3, r1, #31
1052; CHECK-NEXT:    subs r1, r1, r2
1053; CHECK-NEXT:    sbcs.w r1, r3, r2, asr #31
1054; CHECK-NEXT:    vmov r2, s6
1055; CHECK-NEXT:    csel r1, zr, r12, ge
1056; CHECK-NEXT:    rsbs r1, r1, #0
1057; CHECK-NEXT:    bfi r0, r1, #0, #8
1058; CHECK-NEXT:    vmov r1, s2
1059; CHECK-NEXT:    cmp r2, #0
1060; CHECK-NEXT:    cset r2, ne
1061; CHECK-NEXT:    cmp r1, #0
1062; CHECK-NEXT:    csel r12, zr, r2, eq
1063; CHECK-NEXT:    vmov r2, s10
1064; CHECK-NEXT:    asrs r3, r1, #31
1065; CHECK-NEXT:    subs r1, r1, r2
1066; CHECK-NEXT:    sbcs.w r1, r3, r2, asr #31
1067; CHECK-NEXT:    csel r1, zr, r12, ge
1068; CHECK-NEXT:    rsbs r1, r1, #0
1069; CHECK-NEXT:    bfi r0, r1, #8, #8
1070; CHECK-NEXT:    vmsr p0, r0
1071; CHECK-NEXT:    vpsel q0, q2, q0
1072; CHECK-NEXT:    bx lr
1073  %a4 = icmp eq <2 x i64> %a, zeroinitializer
1074  %a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c
1075  %a6 = icmp ne <2 x i32> %b, zeroinitializer
1076  %a7 = icmp slt <2 x i32> %a5, %c
1077  %a8 = icmp ne <2 x i32> %a5, zeroinitializer
1078  %a9 = and <2 x i1> %a6, %a8
1079  %a10 = and <2 x i1> %a7, %a9
1080  %a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5
1081  ret <2 x i32> %a11
1082}
1083