xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-vcmp.ll (revision 90f24bef47227d58f2ccdcc481ca22eff32248ca) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
3
4define arm_aapcs_vfpcc <4 x i32> @vcmp_eq_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {
5; CHECK-LABEL: vcmp_eq_v4i32:
6; CHECK:       @ %bb.0: @ %entry
7; CHECK-NEXT:    vcmp.i32 eq, q0, q1
8; CHECK-NEXT:    vpsel q0, q2, q3
9; CHECK-NEXT:    bx lr
10entry:
11  %c = icmp eq <4 x i32> %src, %srcb
12  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
13  ret <4 x i32> %s
14}
15
16define arm_aapcs_vfpcc <4 x i32> @vcmp_ne_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {
17; CHECK-LABEL: vcmp_ne_v4i32:
18; CHECK:       @ %bb.0: @ %entry
19; CHECK-NEXT:    vcmp.i32 ne, q0, q1
20; CHECK-NEXT:    vpsel q0, q2, q3
21; CHECK-NEXT:    bx lr
22entry:
23  %c = icmp ne <4 x i32> %src, %srcb
24  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
25  ret <4 x i32> %s
26}
27
28define arm_aapcs_vfpcc <4 x i32> @vcmp_sgt_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {
29; CHECK-LABEL: vcmp_sgt_v4i32:
30; CHECK:       @ %bb.0: @ %entry
31; CHECK-NEXT:    vcmp.s32 gt, q0, q1
32; CHECK-NEXT:    vpsel q0, q2, q3
33; CHECK-NEXT:    bx lr
34entry:
35  %c = icmp sgt <4 x i32> %src, %srcb
36  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
37  ret <4 x i32> %s
38}
39
40define arm_aapcs_vfpcc <4 x i32> @vcmp_sge_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {
41; CHECK-LABEL: vcmp_sge_v4i32:
42; CHECK:       @ %bb.0: @ %entry
43; CHECK-NEXT:    vcmp.s32 ge, q0, q1
44; CHECK-NEXT:    vpsel q0, q2, q3
45; CHECK-NEXT:    bx lr
46entry:
47  %c = icmp sge <4 x i32> %src, %srcb
48  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
49  ret <4 x i32> %s
50}
51
52define arm_aapcs_vfpcc <4 x i32> @vcmp_slt_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {
53; CHECK-LABEL: vcmp_slt_v4i32:
54; CHECK:       @ %bb.0: @ %entry
55; CHECK-NEXT:    vcmp.s32 gt, q1, q0
56; CHECK-NEXT:    vpsel q0, q2, q3
57; CHECK-NEXT:    bx lr
58entry:
59  %c = icmp slt <4 x i32> %src, %srcb
60  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
61  ret <4 x i32> %s
62}
63
64define arm_aapcs_vfpcc <4 x i32> @vcmp_sle_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {
65; CHECK-LABEL: vcmp_sle_v4i32:
66; CHECK:       @ %bb.0: @ %entry
67; CHECK-NEXT:    vcmp.s32 ge, q1, q0
68; CHECK-NEXT:    vpsel q0, q2, q3
69; CHECK-NEXT:    bx lr
70entry:
71  %c = icmp sle <4 x i32> %src, %srcb
72  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
73  ret <4 x i32> %s
74}
75
76define arm_aapcs_vfpcc <4 x i32> @vcmp_ugt_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {
77; CHECK-LABEL: vcmp_ugt_v4i32:
78; CHECK:       @ %bb.0: @ %entry
79; CHECK-NEXT:    vcmp.u32 hi, q0, q1
80; CHECK-NEXT:    vpsel q0, q2, q3
81; CHECK-NEXT:    bx lr
82entry:
83  %c = icmp ugt <4 x i32> %src, %srcb
84  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
85  ret <4 x i32> %s
86}
87
88define arm_aapcs_vfpcc <4 x i32> @vcmp_uge_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {
89; CHECK-LABEL: vcmp_uge_v4i32:
90; CHECK:       @ %bb.0: @ %entry
91; CHECK-NEXT:    vcmp.u32 cs, q0, q1
92; CHECK-NEXT:    vpsel q0, q2, q3
93; CHECK-NEXT:    bx lr
94entry:
95  %c = icmp uge <4 x i32> %src, %srcb
96  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
97  ret <4 x i32> %s
98}
99
100define arm_aapcs_vfpcc <4 x i32> @vcmp_ult_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {
101; CHECK-LABEL: vcmp_ult_v4i32:
102; CHECK:       @ %bb.0: @ %entry
103; CHECK-NEXT:    vcmp.u32 hi, q1, q0
104; CHECK-NEXT:    vpsel q0, q2, q3
105; CHECK-NEXT:    bx lr
106entry:
107  %c = icmp ult <4 x i32> %src, %srcb
108  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
109  ret <4 x i32> %s
110}
111
112define arm_aapcs_vfpcc <4 x i32> @vcmp_ule_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) {
113; CHECK-LABEL: vcmp_ule_v4i32:
114; CHECK:       @ %bb.0: @ %entry
115; CHECK-NEXT:    vcmp.u32 cs, q1, q0
116; CHECK-NEXT:    vpsel q0, q2, q3
117; CHECK-NEXT:    bx lr
118entry:
119  %c = icmp ule <4 x i32> %src, %srcb
120  %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
121  ret <4 x i32> %s
122}
123
124
125define arm_aapcs_vfpcc <8 x i16> @vcmp_eq_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {
126; CHECK-LABEL: vcmp_eq_v8i16:
127; CHECK:       @ %bb.0: @ %entry
128; CHECK-NEXT:    vcmp.i16 eq, q0, q1
129; CHECK-NEXT:    vpsel q0, q2, q3
130; CHECK-NEXT:    bx lr
131entry:
132  %c = icmp eq <8 x i16> %src, %srcb
133  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
134  ret <8 x i16> %s
135}
136
137define arm_aapcs_vfpcc <8 x i16> @vcmp_ne_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {
138; CHECK-LABEL: vcmp_ne_v8i16:
139; CHECK:       @ %bb.0: @ %entry
140; CHECK-NEXT:    vcmp.i16 ne, q0, q1
141; CHECK-NEXT:    vpsel q0, q2, q3
142; CHECK-NEXT:    bx lr
143entry:
144  %c = icmp ne <8 x i16> %src, %srcb
145  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
146  ret <8 x i16> %s
147}
148
149define arm_aapcs_vfpcc <8 x i16> @vcmp_sgt_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {
150; CHECK-LABEL: vcmp_sgt_v8i16:
151; CHECK:       @ %bb.0: @ %entry
152; CHECK-NEXT:    vcmp.s16 gt, q0, q1
153; CHECK-NEXT:    vpsel q0, q2, q3
154; CHECK-NEXT:    bx lr
155entry:
156  %c = icmp sgt <8 x i16> %src, %srcb
157  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
158  ret <8 x i16> %s
159}
160
161define arm_aapcs_vfpcc <8 x i16> @vcmp_sge_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {
162; CHECK-LABEL: vcmp_sge_v8i16:
163; CHECK:       @ %bb.0: @ %entry
164; CHECK-NEXT:    vcmp.s16 ge, q0, q1
165; CHECK-NEXT:    vpsel q0, q2, q3
166; CHECK-NEXT:    bx lr
167entry:
168  %c = icmp sge <8 x i16> %src, %srcb
169  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
170  ret <8 x i16> %s
171}
172
173define arm_aapcs_vfpcc <8 x i16> @vcmp_slt_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {
174; CHECK-LABEL: vcmp_slt_v8i16:
175; CHECK:       @ %bb.0: @ %entry
176; CHECK-NEXT:    vcmp.s16 gt, q1, q0
177; CHECK-NEXT:    vpsel q0, q2, q3
178; CHECK-NEXT:    bx lr
179entry:
180  %c = icmp slt <8 x i16> %src, %srcb
181  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
182  ret <8 x i16> %s
183}
184
185define arm_aapcs_vfpcc <8 x i16> @vcmp_sle_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {
186; CHECK-LABEL: vcmp_sle_v8i16:
187; CHECK:       @ %bb.0: @ %entry
188; CHECK-NEXT:    vcmp.s16 ge, q1, q0
189; CHECK-NEXT:    vpsel q0, q2, q3
190; CHECK-NEXT:    bx lr
191entry:
192  %c = icmp sle <8 x i16> %src, %srcb
193  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
194  ret <8 x i16> %s
195}
196
197define arm_aapcs_vfpcc <8 x i16> @vcmp_ugt_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {
198; CHECK-LABEL: vcmp_ugt_v8i16:
199; CHECK:       @ %bb.0: @ %entry
200; CHECK-NEXT:    vcmp.u16 hi, q0, q1
201; CHECK-NEXT:    vpsel q0, q2, q3
202; CHECK-NEXT:    bx lr
203entry:
204  %c = icmp ugt <8 x i16> %src, %srcb
205  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
206  ret <8 x i16> %s
207}
208
209define arm_aapcs_vfpcc <8 x i16> @vcmp_uge_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {
210; CHECK-LABEL: vcmp_uge_v8i16:
211; CHECK:       @ %bb.0: @ %entry
212; CHECK-NEXT:    vcmp.u16 cs, q0, q1
213; CHECK-NEXT:    vpsel q0, q2, q3
214; CHECK-NEXT:    bx lr
215entry:
216  %c = icmp uge <8 x i16> %src, %srcb
217  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
218  ret <8 x i16> %s
219}
220
221define arm_aapcs_vfpcc <8 x i16> @vcmp_ult_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {
222; CHECK-LABEL: vcmp_ult_v8i16:
223; CHECK:       @ %bb.0: @ %entry
224; CHECK-NEXT:    vcmp.u16 hi, q1, q0
225; CHECK-NEXT:    vpsel q0, q2, q3
226; CHECK-NEXT:    bx lr
227entry:
228  %c = icmp ult <8 x i16> %src, %srcb
229  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
230  ret <8 x i16> %s
231}
232
233define arm_aapcs_vfpcc <8 x i16> @vcmp_ule_v8i16(<8 x i16> %src, <8 x i16> %srcb, <8 x i16> %a, <8 x i16> %b) {
234; CHECK-LABEL: vcmp_ule_v8i16:
235; CHECK:       @ %bb.0: @ %entry
236; CHECK-NEXT:    vcmp.u16 cs, q1, q0
237; CHECK-NEXT:    vpsel q0, q2, q3
238; CHECK-NEXT:    bx lr
239entry:
240  %c = icmp ule <8 x i16> %src, %srcb
241  %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
242  ret <8 x i16> %s
243}
244
245
246define arm_aapcs_vfpcc <16 x i8> @vcmp_eq_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {
247; CHECK-LABEL: vcmp_eq_v16i8:
248; CHECK:       @ %bb.0: @ %entry
249; CHECK-NEXT:    vcmp.i8 eq, q0, q1
250; CHECK-NEXT:    vpsel q0, q2, q3
251; CHECK-NEXT:    bx lr
252entry:
253  %c = icmp eq <16 x i8> %src, %srcb
254  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
255  ret <16 x i8> %s
256}
257
258define arm_aapcs_vfpcc <16 x i8> @vcmp_ne_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {
259; CHECK-LABEL: vcmp_ne_v16i8:
260; CHECK:       @ %bb.0: @ %entry
261; CHECK-NEXT:    vcmp.i8 ne, q0, q1
262; CHECK-NEXT:    vpsel q0, q2, q3
263; CHECK-NEXT:    bx lr
264entry:
265  %c = icmp ne <16 x i8> %src, %srcb
266  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
267  ret <16 x i8> %s
268}
269
270define arm_aapcs_vfpcc <16 x i8> @vcmp_sgt_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {
271; CHECK-LABEL: vcmp_sgt_v16i8:
272; CHECK:       @ %bb.0: @ %entry
273; CHECK-NEXT:    vcmp.s8 gt, q0, q1
274; CHECK-NEXT:    vpsel q0, q2, q3
275; CHECK-NEXT:    bx lr
276entry:
277  %c = icmp sgt <16 x i8> %src, %srcb
278  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
279  ret <16 x i8> %s
280}
281
282define arm_aapcs_vfpcc <16 x i8> @vcmp_sge_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {
283; CHECK-LABEL: vcmp_sge_v16i8:
284; CHECK:       @ %bb.0: @ %entry
285; CHECK-NEXT:    vcmp.s8 ge, q0, q1
286; CHECK-NEXT:    vpsel q0, q2, q3
287; CHECK-NEXT:    bx lr
288entry:
289  %c = icmp sge <16 x i8> %src, %srcb
290  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
291  ret <16 x i8> %s
292}
293
294define arm_aapcs_vfpcc <16 x i8> @vcmp_slt_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {
295; CHECK-LABEL: vcmp_slt_v16i8:
296; CHECK:       @ %bb.0: @ %entry
297; CHECK-NEXT:    vcmp.s8 gt, q1, q0
298; CHECK-NEXT:    vpsel q0, q2, q3
299; CHECK-NEXT:    bx lr
300entry:
301  %c = icmp slt <16 x i8> %src, %srcb
302  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
303  ret <16 x i8> %s
304}
305
306define arm_aapcs_vfpcc <16 x i8> @vcmp_sle_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {
307; CHECK-LABEL: vcmp_sle_v16i8:
308; CHECK:       @ %bb.0: @ %entry
309; CHECK-NEXT:    vcmp.s8 ge, q1, q0
310; CHECK-NEXT:    vpsel q0, q2, q3
311; CHECK-NEXT:    bx lr
312entry:
313  %c = icmp sle <16 x i8> %src, %srcb
314  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
315  ret <16 x i8> %s
316}
317
318define arm_aapcs_vfpcc <16 x i8> @vcmp_ugt_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {
319; CHECK-LABEL: vcmp_ugt_v16i8:
320; CHECK:       @ %bb.0: @ %entry
321; CHECK-NEXT:    vcmp.u8 hi, q0, q1
322; CHECK-NEXT:    vpsel q0, q2, q3
323; CHECK-NEXT:    bx lr
324entry:
325  %c = icmp ugt <16 x i8> %src, %srcb
326  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
327  ret <16 x i8> %s
328}
329
330define arm_aapcs_vfpcc <16 x i8> @vcmp_uge_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {
331; CHECK-LABEL: vcmp_uge_v16i8:
332; CHECK:       @ %bb.0: @ %entry
333; CHECK-NEXT:    vcmp.u8 cs, q0, q1
334; CHECK-NEXT:    vpsel q0, q2, q3
335; CHECK-NEXT:    bx lr
336entry:
337  %c = icmp uge <16 x i8> %src, %srcb
338  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
339  ret <16 x i8> %s
340}
341
342define arm_aapcs_vfpcc <16 x i8> @vcmp_ult_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {
343; CHECK-LABEL: vcmp_ult_v16i8:
344; CHECK:       @ %bb.0: @ %entry
345; CHECK-NEXT:    vcmp.u8 hi, q1, q0
346; CHECK-NEXT:    vpsel q0, q2, q3
347; CHECK-NEXT:    bx lr
348entry:
349  %c = icmp ult <16 x i8> %src, %srcb
350  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
351  ret <16 x i8> %s
352}
353
354define arm_aapcs_vfpcc <16 x i8> @vcmp_ule_v16i8(<16 x i8> %src, <16 x i8> %srcb, <16 x i8> %a, <16 x i8> %b) {
355; CHECK-LABEL: vcmp_ule_v16i8:
356; CHECK:       @ %bb.0: @ %entry
357; CHECK-NEXT:    vcmp.u8 cs, q1, q0
358; CHECK-NEXT:    vpsel q0, q2, q3
359; CHECK-NEXT:    bx lr
360entry:
361  %c = icmp ule <16 x i8> %src, %srcb
362  %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
363  ret <16 x i8> %s
364}
365
366
367define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, <2 x i64> %srcb, <2 x i64> %a, <2 x i64> %b) {
368; CHECK-LABEL: vcmp_eq_v2i64:
369; CHECK:       @ %bb.0: @ %entry
370; CHECK-NEXT:    vmov r0, r1, d2
371; CHECK-NEXT:    vmov r2, r3, d0
372; CHECK-NEXT:    eors r0, r2
373; CHECK-NEXT:    eors r1, r3
374; CHECK-NEXT:    orrs r0, r1
375; CHECK-NEXT:    mov.w r1, #0
376; CHECK-NEXT:    csetm r0, eq
377; CHECK-NEXT:    vmov r12, r2, d3
378; CHECK-NEXT:    bfi r1, r0, #0, #8
379; CHECK-NEXT:    vmov r3, r0, d1
380; CHECK-NEXT:    eors r0, r2
381; CHECK-NEXT:    eor.w r2, r3, r12
382; CHECK-NEXT:    orrs r0, r2
383; CHECK-NEXT:    csetm r0, eq
384; CHECK-NEXT:    bfi r1, r0, #8, #8
385; CHECK-NEXT:    vmsr p0, r1
386; CHECK-NEXT:    vpsel q0, q2, q3
387; CHECK-NEXT:    bx lr
388entry:
389  %c = icmp eq <2 x i64> %src, %srcb
390  %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b
391  ret <2 x i64> %s
392}
393
394define arm_aapcs_vfpcc <2 x i64> @vcmp_slt_v2i64(<2 x i64> %src, <2 x i64> %srcb, <2 x i64> %a, <2 x i64> %b) {
395; CHECK-LABEL: vcmp_slt_v2i64:
396; CHECK:       @ %bb.0: @ %entry
397; CHECK-NEXT:    vmov r0, r1, d2
398; CHECK-NEXT:    vmov r2, r3, d0
399; CHECK-NEXT:    subs r0, r2, r0
400; CHECK-NEXT:    sbcs.w r0, r3, r1
401; CHECK-NEXT:    mov.w r1, #0
402; CHECK-NEXT:    csetm r0, lt
403; CHECK-NEXT:    vmov r3, r2, d1
404; CHECK-NEXT:    bfi r1, r0, #0, #8
405; CHECK-NEXT:    vmov r0, r12, d3
406; CHECK-NEXT:    subs r0, r3, r0
407; CHECK-NEXT:    sbcs.w r0, r2, r12
408; CHECK-NEXT:    csetm r0, lt
409; CHECK-NEXT:    bfi r1, r0, #8, #8
410; CHECK-NEXT:    vmsr p0, r1
411; CHECK-NEXT:    vpsel q0, q2, q3
412; CHECK-NEXT:    bx lr
413entry:
414  %c = icmp slt <2 x i64> %src, %srcb
415  %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b
416  ret <2 x i64> %s
417}
418
419define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, <2 x i64> %srcb, <2 x i32> %a, <2 x i32> %b) {
420; CHECK-LABEL: vcmp_eq_v2i32:
421; CHECK:       @ %bb.0: @ %entry
422; CHECK-NEXT:    vmov r0, r1, d2
423; CHECK-NEXT:    vmov r2, r3, d0
424; CHECK-NEXT:    eors r0, r2
425; CHECK-NEXT:    eors r1, r3
426; CHECK-NEXT:    orrs r0, r1
427; CHECK-NEXT:    mov.w r1, #0
428; CHECK-NEXT:    csetm r0, eq
429; CHECK-NEXT:    vmov r12, r2, d3
430; CHECK-NEXT:    bfi r1, r0, #0, #8
431; CHECK-NEXT:    vmov r3, r0, d1
432; CHECK-NEXT:    eors r0, r2
433; CHECK-NEXT:    eor.w r2, r3, r12
434; CHECK-NEXT:    orrs r0, r2
435; CHECK-NEXT:    csetm r0, eq
436; CHECK-NEXT:    bfi r1, r0, #8, #8
437; CHECK-NEXT:    vmsr p0, r1
438; CHECK-NEXT:    vpsel q0, q2, q3
439; CHECK-NEXT:    bx lr
440entry:
441  %c = icmp eq <2 x i64> %src, %srcb
442  %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b
443  ret <2 x i32> %s
444}
445
446define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
447; CHECK-LABEL: vcmp_multi_v2i32:
448; CHECK:       @ %bb.0:
449; CHECK-NEXT:    vmov r0, r1, d0
450; CHECK-NEXT:    movs r2, #0
451; CHECK-NEXT:    orrs r0, r1
452; CHECK-NEXT:    csetm r1, eq
453; CHECK-NEXT:    movs r0, #0
454; CHECK-NEXT:    bfi r2, r1, #0, #8
455; CHECK-NEXT:    vmov r1, r3, d1
456; CHECK-NEXT:    vmov.i32 q0, #0x0
457; CHECK-NEXT:    orrs r1, r3
458; CHECK-NEXT:    csetm r1, eq
459; CHECK-NEXT:    bfi r2, r1, #8, #8
460; CHECK-NEXT:    vmsr p0, r2
461; CHECK-NEXT:    vmov r2, s4
462; CHECK-NEXT:    vpsel q0, q0, q2
463; CHECK-NEXT:    vmov r1, s0
464; CHECK-NEXT:    cmp r2, #0
465; CHECK-NEXT:    cset r2, ne
466; CHECK-NEXT:    cmp r1, #0
467; CHECK-NEXT:    csel r12, zr, r2, eq
468; CHECK-NEXT:    vmov r2, s8
469; CHECK-NEXT:    asrs r3, r1, #31
470; CHECK-NEXT:    subs r1, r1, r2
471; CHECK-NEXT:    sbcs.w r1, r3, r2, asr #31
472; CHECK-NEXT:    vmov r2, s6
473; CHECK-NEXT:    csel r1, zr, r12, ge
474; CHECK-NEXT:    rsbs r1, r1, #0
475; CHECK-NEXT:    bfi r0, r1, #0, #8
476; CHECK-NEXT:    vmov r1, s2
477; CHECK-NEXT:    cmp r2, #0
478; CHECK-NEXT:    cset r2, ne
479; CHECK-NEXT:    cmp r1, #0
480; CHECK-NEXT:    csel r12, zr, r2, eq
481; CHECK-NEXT:    vmov r2, s10
482; CHECK-NEXT:    asrs r3, r1, #31
483; CHECK-NEXT:    subs r1, r1, r2
484; CHECK-NEXT:    sbcs.w r1, r3, r2, asr #31
485; CHECK-NEXT:    csel r1, zr, r12, ge
486; CHECK-NEXT:    rsbs r1, r1, #0
487; CHECK-NEXT:    bfi r0, r1, #8, #8
488; CHECK-NEXT:    vmsr p0, r0
489; CHECK-NEXT:    vpsel q0, q2, q0
490; CHECK-NEXT:    bx lr
491  %a4 = icmp eq <2 x i64> %a, zeroinitializer
492  %a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c
493  %a6 = icmp ne <2 x i32> %b, zeroinitializer
494  %a7 = icmp slt <2 x i32> %a5, %c
495  %a8 = icmp ne <2 x i32> %a5, zeroinitializer
496  %a9 = and <2 x i1> %a6, %a8
497  %a10 = and <2 x i1> %a7, %a9
498  %a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5
499  ret <2 x i32> %a11
500}
501