1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve -simplify-mir --verify-machineinstrs -run-pass=finalize-isel %s -o - | FileCheck %s 3# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve -simplify-mir -passes=finalize-isel %s -o - | FileCheck %s 4--- | 5 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 6 target triple = "arm-arm-none-eabi" 7 8 ; Function Attrs: argmemonly nofree nosync nounwind willreturn 9 declare void @llvm.memcpy.p0.p0.i32(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i32, i1 immarg) 10 ; Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly 11 declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg) 12 13 define void @test1(ptr noalias %X, ptr noalias readonly %Y, i32 %n) { 14 entry: 15 call void @llvm.memcpy.p0.p0.i32(ptr align 4 %X, ptr align 4 %Y, i32 %n, i1 false) 16 ret void 17 } 18 19 define void @test2(ptr noalias %X, ptr noalias readonly %Y, i32 %n) { 20 entry: 21 %cmp6 = icmp sgt i32 %n, 0 22 br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup 23 24 for.body.preheader: ; preds = %entry 25 call void @llvm.memcpy.p0.p0.i32(ptr align 4 %X, ptr align 4 %Y, i32 %n, i1 false) 26 br label %for.cond.cleanup 27 28 for.cond.cleanup: ; preds = %for.body.preheader, %entry 29 ret void 30 } 31 32 define void @test3(ptr nocapture %X, i8 zeroext %c, i32 %n) { 33 entry: 34 tail call void @llvm.memset.p0.i32(ptr align 4 %X, i8 %c, i32 %n, i1 false) 35 ret void 36 } 37 38 39 define void @test4(ptr nocapture %X, i8 zeroext %c, i32 %n) { 40 entry: 41 %cmp4 = icmp sgt i32 %n, 0 42 br i1 %cmp4, label %for.body.preheader, label %for.cond.cleanup 43 44 for.body.preheader: ; preds = %entry 45 call void @llvm.memset.p0.i32(ptr align 1 %X, i8 %c, i32 %n, i1 false) 46 br label %for.cond.cleanup 47 48 for.cond.cleanup: ; preds = %for.body.preheader, %entry 49 ret void 50 } 51 52... 53--- 54name: test1 55tracksRegLiveness: true 56body: | 57 bb.0.entry: 58 liveins: $r0, $r1, $r2 59 60 ; CHECK-LABEL: name: test1 61 ; CHECK: liveins: $r0, $r1, $r2 62 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2 63 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 64 ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0 65 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg 66 ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg 67 ; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]] 68 ; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.2, implicit-def $cpsr 69 ; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg 70 ; CHECK: .1: 71 ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.0, %7, %bb.1 72 ; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.0, %9, %bb.1 73 ; CHECK: [[PHI2:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.0, %11, %bb.1 74 ; CHECK: [[PHI3:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.0, %13, %bb.1 75 ; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI3]], 0, $noreg, $noreg 76 ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI3]], 16, 14 /* CC::al */, $noreg, $noreg 77 ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[PHI]], 16, 1, [[MVE_VCTP8_]], $noreg 78 ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[MVE_VLDRBU8_post1]], [[PHI1]], 16, 1, [[MVE_VCTP8_]], $noreg 79 ; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI2]], 1 80 ; CHECK: t2LoopEnd [[t2LoopDec]], %bb.1, implicit-def $cpsr 81 ; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg 82 ; CHECK: .2.entry: 83 ; CHECK: tBX_RET 14 /* CC::al */, $noreg 84 %2:rgpr = COPY $r2 85 %1:rgpr = COPY $r1 86 %0:rgpr = COPY $r0 87 MVE_MEMCPYLOOPINST %0, %1, %2, implicit-def $cpsr 88 tBX_RET 14 /* CC::al */, $noreg 89 90... 91--- 92name: test2 93tracksRegLiveness: true 94body: | 95 ; CHECK-LABEL: name: test2 96 ; CHECK: bb.0.entry: 97 ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000) 98 ; CHECK: liveins: $r0, $r1, $r2 99 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2 100 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 101 ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0 102 ; CHECK: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 103 ; CHECK: t2Bcc %bb.2, 11 /* CC::lt */, $cpsr 104 ; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg 105 ; CHECK: bb.1.for.body.preheader: 106 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg 107 ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg 108 ; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]] 109 ; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.4, implicit-def $cpsr 110 ; CHECK: t2B %bb.3, 14 /* CC::al */, $noreg 111 ; CHECK: bb.3: 112 ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.1, %7, %bb.3 113 ; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.1, %9, %bb.3 114 ; CHECK: [[PHI2:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.1, %11, %bb.3 115 ; CHECK: [[PHI3:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.1, %13, %bb.3 116 ; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI3]], 0, $noreg, $noreg 117 ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI3]], 16, 14 /* CC::al */, $noreg, $noreg 118 ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[PHI]], 16, 1, [[MVE_VCTP8_]], $noreg 119 ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[MVE_VLDRBU8_post1]], [[PHI1]], 16, 1, [[MVE_VCTP8_]], $noreg 120 ; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI2]], 1 121 ; CHECK: t2LoopEnd [[t2LoopDec]], %bb.3, implicit-def $cpsr 122 ; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg 123 ; CHECK: bb.4.for.body.preheader: 124 ; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg 125 ; CHECK: bb.2.for.cond.cleanup: 126 ; CHECK: tBX_RET 14 /* CC::al */, $noreg 127 bb.0.entry: 128 successors: %bb.1(0x50000000), %bb.2(0x30000000) 129 liveins: $r0, $r1, $r2 130 131 %2:rgpr = COPY $r2 132 %1:rgpr = COPY $r1 133 %0:rgpr = COPY $r0 134 t2CMPri %2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 135 t2Bcc %bb.2, 11 /* CC::lt */, $cpsr 136 t2B %bb.1, 14 /* CC::al */, $noreg 137 138 bb.1.for.body.preheader: 139 successors: %bb.2(0x80000000) 140 141 MVE_MEMCPYLOOPINST %0, %1, %2, implicit-def $cpsr 142 143 bb.2.for.cond.cleanup: 144 tBX_RET 14 /* CC::al */, $noreg 145 146... 147--- 148name: test3 149tracksRegLiveness: true 150body: | 151 bb.0.entry: 152 liveins: $r0, $r1, $r2 153 154 ; CHECK-LABEL: name: test3 155 ; CHECK: liveins: $r0, $r1, $r2 156 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2 157 ; CHECK: [[COPY1:%[0-9]+]]:mqpr = COPY $r1 158 ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0 159 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg 160 ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg 161 ; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]] 162 ; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.2, implicit-def $cpsr 163 ; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg 164 ; CHECK: .1: 165 ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.0, %7, %bb.1 166 ; CHECK: [[PHI1:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.0, %9, %bb.1 167 ; CHECK: [[PHI2:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.0, %11, %bb.1 168 ; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI2]], 0, $noreg, $noreg 169 ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 16, 14 /* CC::al */, $noreg, $noreg 170 ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY1]], [[PHI]], 16, 1, [[MVE_VCTP8_]], $noreg 171 ; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI1]], 1 172 ; CHECK: t2LoopEnd [[t2LoopDec]], %bb.1, implicit-def $cpsr 173 ; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg 174 ; CHECK: .2.entry: 175 ; CHECK: tBX_RET 14 /* CC::al */, $noreg 176 %2:rgpr = COPY $r2 177 %1:mqpr = COPY $r1 178 %0:rgpr = COPY $r0 179 MVE_MEMSETLOOPINST %0, %1, %2, implicit-def $cpsr 180 tBX_RET 14 /* CC::al */, $noreg 181 182... 183--- 184name: test4 185alignment: 2 186tracksRegLiveness: true 187body: | 188 ; CHECK-LABEL: name: test4 189 ; CHECK: bb.0.entry: 190 ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000) 191 ; CHECK: liveins: $r0, $r1, $r2 192 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2 193 ; CHECK: [[COPY1:%[0-9]+]]:mqpr = COPY $r1 194 ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0 195 ; CHECK: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 196 ; CHECK: t2Bcc %bb.2, 11 /* CC::lt */, $cpsr 197 ; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg 198 ; CHECK: bb.1.for.body.preheader: 199 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg 200 ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg 201 ; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]] 202 ; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.4, implicit-def $cpsr 203 ; CHECK: t2B %bb.3, 14 /* CC::al */, $noreg 204 ; CHECK: bb.3: 205 ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.1, %7, %bb.3 206 ; CHECK: [[PHI1:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.1, %9, %bb.3 207 ; CHECK: [[PHI2:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.1, %11, %bb.3 208 ; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI2]], 0, $noreg, $noreg 209 ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 16, 14 /* CC::al */, $noreg, $noreg 210 ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY1]], [[PHI]], 16, 1, [[MVE_VCTP8_]], $noreg 211 ; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI1]], 1 212 ; CHECK: t2LoopEnd [[t2LoopDec]], %bb.3, implicit-def $cpsr 213 ; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg 214 ; CHECK: bb.4.for.body.preheader: 215 ; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg 216 ; CHECK: bb.2.for.cond.cleanup: 217 ; CHECK: tBX_RET 14 /* CC::al */, $noreg 218 bb.0.entry: 219 successors: %bb.1(0x50000000), %bb.2(0x30000000) 220 liveins: $r0, $r1, $r2 221 222 %2:rgpr = COPY $r2 223 %1:mqpr = COPY $r1 224 %0:rgpr = COPY $r0 225 t2CMPri %2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 226 t2Bcc %bb.2, 11 /* CC::lt */, $cpsr 227 t2B %bb.1, 14 /* CC::al */, $noreg 228 229 bb.1.for.body.preheader: 230 MVE_MEMSETLOOPINST %0, %1, %2, implicit-def $cpsr 231 232 bb.2.for.cond.cleanup: 233 tBX_RET 14 /* CC::al */, $noreg 234 235... 236