1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat=false -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK 3 4define arm_aapcs_vfpcc <4 x i32> @test_v4i32(i32 %x, <4 x i32> %s0, <4 x i32> %s1) { 5; CHECK-LABEL: test_v4i32: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: cmp r0, #0 8; CHECK-NEXT: it eq 9; CHECK-NEXT: bxeq lr 10; CHECK-NEXT: .LBB0_1: @ %select.false 11; CHECK-NEXT: vmov q0, q1 12; CHECK-NEXT: bx lr 13entry: 14 %c = icmp eq i32 %x, 0 15 %s = select i1 %c, <4 x i32> %s0, <4 x i32> %s1 16 ret <4 x i32> %s 17} 18 19define arm_aapcs_vfpcc <8 x i16> @test_v8i16(i32 %x, <8 x i16> %s0, <8 x i16> %s1) { 20; CHECK-LABEL: test_v8i16: 21; CHECK: @ %bb.0: @ %entry 22; CHECK-NEXT: cmp r0, #0 23; CHECK-NEXT: it eq 24; CHECK-NEXT: bxeq lr 25; CHECK-NEXT: .LBB1_1: @ %select.false 26; CHECK-NEXT: vmov q0, q1 27; CHECK-NEXT: bx lr 28entry: 29 %c = icmp eq i32 %x, 0 30 %s = select i1 %c, <8 x i16> %s0, <8 x i16> %s1 31 ret <8 x i16> %s 32} 33 34define arm_aapcs_vfpcc <16 x i8> @test_v16i8(i32 %x, <16 x i8> %s0, <16 x i8> %s1) { 35; CHECK-LABEL: test_v16i8: 36; CHECK: @ %bb.0: @ %entry 37; CHECK-NEXT: cmp r0, #0 38; CHECK-NEXT: it eq 39; CHECK-NEXT: bxeq lr 40; CHECK-NEXT: .LBB2_1: @ %select.false 41; CHECK-NEXT: vmov q0, q1 42; CHECK-NEXT: bx lr 43entry: 44 %c = icmp eq i32 %x, 0 45 %s = select i1 %c, <16 x i8> %s0, <16 x i8> %s1 46 ret <16 x i8> %s 47} 48 49define arm_aapcs_vfpcc <2 x i64> @test_v2i64(i32 %x, <2 x i64> %s0, <2 x i64> %s1) { 50; CHECK-LABEL: test_v2i64: 51; CHECK: @ %bb.0: @ %entry 52; CHECK-NEXT: cmp r0, #0 53; CHECK-NEXT: it eq 54; CHECK-NEXT: bxeq lr 55; CHECK-NEXT: .LBB3_1: @ %select.false 56; CHECK-NEXT: vmov q0, q1 57; CHECK-NEXT: bx lr 58entry: 59 %c = icmp eq i32 %x, 0 60 %s = select i1 %c, <2 x i64> %s0, <2 x i64> %s1 61 ret <2 x i64> %s 62} 63 64define arm_aapcs_vfpcc <4 x float> @test_v4float(i32 %x, <4 x float> %s0, <4 x float> %s1) { 65; CHECK-LABEL: test_v4float: 66; CHECK: @ %bb.0: @ %entry 67; CHECK-NEXT: cmp r0, #0 68; CHECK-NEXT: it eq 69; CHECK-NEXT: bxeq lr 70; CHECK-NEXT: .LBB4_1: @ %select.false 71; CHECK-NEXT: vmov q0, q1 72; CHECK-NEXT: bx lr 73entry: 74 %c = icmp eq i32 %x, 0 75 %s = select i1 %c, <4 x float> %s0, <4 x float> %s1 76 ret <4 x float> %s 77} 78 79define arm_aapcs_vfpcc <8 x half> @test_v8half(i32 %x, <8 x half> %s0, <8 x half> %s1) { 80; CHECK-LABEL: test_v8half: 81; CHECK: @ %bb.0: @ %entry 82; CHECK-NEXT: cmp r0, #0 83; CHECK-NEXT: it eq 84; CHECK-NEXT: bxeq lr 85; CHECK-NEXT: .LBB5_1: @ %select.false 86; CHECK-NEXT: vmov q0, q1 87; CHECK-NEXT: bx lr 88entry: 89 %c = icmp eq i32 %x, 0 90 %s = select i1 %c, <8 x half> %s0, <8 x half> %s1 91 ret <8 x half> %s 92} 93 94define arm_aapcs_vfpcc <2 x double> @test_v2double(i32 %x, <2 x double> %s0, <2 x double> %s1) { 95; CHECK-LABEL: test_v2double: 96; CHECK: @ %bb.0: @ %entry 97; CHECK-NEXT: cmp r0, #0 98; CHECK-NEXT: it eq 99; CHECK-NEXT: bxeq lr 100; CHECK-NEXT: .LBB6_1: @ %select.false 101; CHECK-NEXT: vmov q0, q1 102; CHECK-NEXT: bx lr 103entry: 104 %c = icmp eq i32 %x, 0 105 %s = select i1 %c, <2 x double> %s0, <2 x double> %s1 106 ret <2 x double> %s 107} 108 109define arm_aapcs_vfpcc <4 x i32> @minsize_v4i32(i32 %x, <4 x i32> %s0, <4 x i32> %s1) minsize { 110; CHECK-LABEL: minsize_v4i32: 111; CHECK: @ %bb.0: @ %entry 112; CHECK-NEXT: cbz r0, .LBB7_2 113; CHECK-NEXT: @ %bb.1: @ %select.false 114; CHECK-NEXT: vmov q0, q1 115; CHECK-NEXT: .LBB7_2: @ %select.end 116; CHECK-NEXT: bx lr 117entry: 118 %c = icmp eq i32 %x, 0 119 %s = select i1 %c, <4 x i32> %s0, <4 x i32> %s1 120 ret <4 x i32> %s 121} 122 123define arm_aapcs_vfpcc <8 x i16> @minsize_v8i16(i32 %x, <8 x i16> %s0, <8 x i16> %s1) minsize { 124; CHECK-LABEL: minsize_v8i16: 125; CHECK: @ %bb.0: @ %entry 126; CHECK-NEXT: cbz r0, .LBB8_2 127; CHECK-NEXT: @ %bb.1: @ %select.false 128; CHECK-NEXT: vmov q0, q1 129; CHECK-NEXT: .LBB8_2: @ %select.end 130; CHECK-NEXT: bx lr 131entry: 132 %c = icmp eq i32 %x, 0 133 %s = select i1 %c, <8 x i16> %s0, <8 x i16> %s1 134 ret <8 x i16> %s 135} 136 137define arm_aapcs_vfpcc <16 x i8> @minsize_v16i8(i32 %x, <16 x i8> %s0, <16 x i8> %s1) minsize { 138; CHECK-LABEL: minsize_v16i8: 139; CHECK: @ %bb.0: @ %entry 140; CHECK-NEXT: cbz r0, .LBB9_2 141; CHECK-NEXT: @ %bb.1: @ %select.false 142; CHECK-NEXT: vmov q0, q1 143; CHECK-NEXT: .LBB9_2: @ %select.end 144; CHECK-NEXT: bx lr 145entry: 146 %c = icmp eq i32 %x, 0 147 %s = select i1 %c, <16 x i8> %s0, <16 x i8> %s1 148 ret <16 x i8> %s 149} 150 151define arm_aapcs_vfpcc <2 x i64> @minsize_v2i64(i32 %x, <2 x i64> %s0, <2 x i64> %s1) minsize { 152; CHECK-LABEL: minsize_v2i64: 153; CHECK: @ %bb.0: @ %entry 154; CHECK-NEXT: cbz r0, .LBB10_2 155; CHECK-NEXT: @ %bb.1: @ %select.false 156; CHECK-NEXT: vmov q0, q1 157; CHECK-NEXT: .LBB10_2: @ %select.end 158; CHECK-NEXT: bx lr 159entry: 160 %c = icmp eq i32 %x, 0 161 %s = select i1 %c, <2 x i64> %s0, <2 x i64> %s1 162 ret <2 x i64> %s 163} 164 165define arm_aapcs_vfpcc <4 x float> @minsize_v4float(i32 %x, <4 x float> %s0, <4 x float> %s1) minsize { 166; CHECK-LABEL: minsize_v4float: 167; CHECK: @ %bb.0: @ %entry 168; CHECK-NEXT: cbz r0, .LBB11_2 169; CHECK-NEXT: @ %bb.1: @ %select.false 170; CHECK-NEXT: vmov q0, q1 171; CHECK-NEXT: .LBB11_2: @ %select.end 172; CHECK-NEXT: bx lr 173entry: 174 %c = icmp eq i32 %x, 0 175 %s = select i1 %c, <4 x float> %s0, <4 x float> %s1 176 ret <4 x float> %s 177} 178 179define arm_aapcs_vfpcc <8 x half> @minsize_v8half(i32 %x, <8 x half> %s0, <8 x half> %s1) minsize { 180; CHECK-LABEL: minsize_v8half: 181; CHECK: @ %bb.0: @ %entry 182; CHECK-NEXT: cbz r0, .LBB12_2 183; CHECK-NEXT: @ %bb.1: @ %select.false 184; CHECK-NEXT: vmov q0, q1 185; CHECK-NEXT: .LBB12_2: @ %select.end 186; CHECK-NEXT: bx lr 187entry: 188 %c = icmp eq i32 %x, 0 189 %s = select i1 %c, <8 x half> %s0, <8 x half> %s1 190 ret <8 x half> %s 191} 192 193define arm_aapcs_vfpcc <2 x double> @minsize_v2double(i32 %x, <2 x double> %s0, <2 x double> %s1) minsize { 194; CHECK-LABEL: minsize_v2double: 195; CHECK: @ %bb.0: @ %entry 196; CHECK-NEXT: cbz r0, .LBB13_2 197; CHECK-NEXT: @ %bb.1: @ %select.false 198; CHECK-NEXT: vmov q0, q1 199; CHECK-NEXT: .LBB13_2: @ %select.end 200; CHECK-NEXT: bx lr 201entry: 202 %c = icmp eq i32 %x, 0 203 %s = select i1 %c, <2 x double> %s0, <2 x double> %s1 204 ret <2 x double> %s 205} 206 207define i32 @e() { 208; CHECK-LABEL: e: 209; CHECK: @ %bb.0: @ %entry 210; CHECK-NEXT: adr r0, .LCPI14_0 211; CHECK-NEXT: movs r1, #0 212; CHECK-NEXT: vldrw.u32 q0, [r0] 213; CHECK-NEXT: movs r0, #4 214; CHECK-NEXT: vmov q1, q0 215; CHECK-NEXT: .LBB14_1: @ %vector.body 216; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 217; CHECK-NEXT: adds r1, #4 218; CHECK-NEXT: vadd.i32 q1, q1, r0 219; CHECK-NEXT: cmp r1, #8 220; CHECK-NEXT: csetm r2, eq 221; CHECK-NEXT: subs.w r3, r1, #8 222; CHECK-NEXT: vdup.32 q2, r2 223; CHECK-NEXT: csel r1, r1, r3, ne 224; CHECK-NEXT: vbic q1, q1, q2 225; CHECK-NEXT: vand q2, q2, q0 226; CHECK-NEXT: vorr q1, q2, q1 227; CHECK-NEXT: b .LBB14_1 228; CHECK-NEXT: .p2align 4 229; CHECK-NEXT: @ %bb.2: 230; CHECK-NEXT: .LCPI14_0: 231; CHECK-NEXT: .long 0 @ 0x0 232; CHECK-NEXT: .long 1 @ 0x1 233; CHECK-NEXT: .long 2 @ 0x2 234; CHECK-NEXT: .long 3 @ 0x3 235entry: 236 br label %vector.body 237 238vector.body: ; preds = %pred.store.continue73, %entry 239 %index = phi i32 [ 0, %entry ], [ %spec.select, %pred.store.continue73 ] 240 %vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %entry ], [ %spec.select74, %pred.store.continue73 ] 241 %l3 = icmp ult <4 x i32> %vec.ind, <i32 5, i32 5, i32 5, i32 5> 242 %l4 = extractelement <4 x i1> %l3, i32 0 243 br label %pred.store.continue73 244 245pred.store.continue73: ; preds = %pred.store.if72, %pred.store.continue71 246 %index.next = add i32 %index, 4 247 %vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4> 248 %l60 = icmp eq i32 %index.next, 8 249 %spec.select = select i1 %l60, i32 0, i32 %index.next 250 %spec.select74 = select i1 %l60, <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> %vec.ind.next 251 br label %vector.body 252} 253 254