1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -verify-machineinstrs -o - | FileCheck %s 3 4define void @arm_min_helium_f32(ptr %pSrc, i32 %blockSize, ptr nocapture %pResult, ptr nocapture %pIndex) { 5; CHECK-LABEL: arm_min_helium_f32: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: .save {r4, r5, r7, lr} 8; CHECK-NEXT: push {r4, r5, r7, lr} 9; CHECK-NEXT: movs r4, #0 10; CHECK-NEXT: mov.w r12, #4 11; CHECK-NEXT: vidup.u32 q2, r4, #1 12; CHECK-NEXT: movw r5, #54437 13; CHECK-NEXT: movt r5, #21352 14; CHECK-NEXT: vdup.32 q1, r5 15; CHECK-NEXT: vmov.i32 q0, #0x0 16; CHECK-NEXT: dlstp.32 lr, r1 17; CHECK-NEXT: .LBB0_1: @ %do.body 18; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 19; CHECK-NEXT: vldrw.u32 q3, [r0], #16 20; CHECK-NEXT: vptt.f32 ge, q1, q3 21; CHECK-NEXT: vmovt q0, q2 22; CHECK-NEXT: vmovt q1, q3 23; CHECK-NEXT: vadd.i32 q2, q2, r12 24; CHECK-NEXT: letp lr, .LBB0_1 25; CHECK-NEXT: @ %bb.2: @ %do.end 26; CHECK-NEXT: vldr s8, .LCPI0_0 27; CHECK-NEXT: vdup.32 q3, r1 28; CHECK-NEXT: vmov r0, s8 29; CHECK-NEXT: vminnmv.f32 r0, q1 30; CHECK-NEXT: vcmp.f32 le, q1, r0 31; CHECK-NEXT: vmov s8, r0 32; CHECK-NEXT: vpsel q0, q0, q3 33; CHECK-NEXT: vminv.u32 r1, q0 34; CHECK-NEXT: str r1, [r3] 35; CHECK-NEXT: vstr s8, [r2] 36; CHECK-NEXT: pop {r4, r5, r7, pc} 37; CHECK-NEXT: .p2align 2 38; CHECK-NEXT: @ %bb.3: 39; CHECK-NEXT: .LCPI0_0: 40; CHECK-NEXT: .long 0x5368d4a5 @ float 9.99999995E+11 41entry: 42 %0 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 0, i32 1) 43 %1 = extractvalue { <4 x i32>, i32 } %0, 0 44 br label %do.body 45 46do.body: ; preds = %do.body, %entry 47 %curExtremValVec.0 = phi <4 x float> [ <float 0x426D1A94A0000000, float 0x426D1A94A0000000, float 0x426D1A94A0000000, float 0x426D1A94A0000000>, %entry ], [ %8, %do.body ] 48 %indexVec.0 = phi <4 x i32> [ %1, %entry ], [ %11, %do.body ] 49 %2 = phi <4 x float> [ zeroinitializer, %entry ], [ %10, %do.body ] 50 %blkCnt.0 = phi i32 [ %blockSize, %entry ], [ %sub, %do.body ] 51 %pSrc.addr.0 = phi ptr [ %pSrc, %entry ], [ %add.ptr, %do.body ] 52 %3 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0) 53 %4 = bitcast ptr %pSrc.addr.0 to ptr 54 %5 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr %4, i32 4, <4 x i1> %3, <4 x float> zeroinitializer) 55 %6 = fcmp fast ole <4 x float> %5, %curExtremValVec.0 56 %7 = and <4 x i1> %6, %3 57 %8 = select fast <4 x i1> %7, <4 x float> %5, <4 x float> %curExtremValVec.0 58 %9 = bitcast <4 x i32> %indexVec.0 to <4 x float> 59 %10 = select fast <4 x i1> %7, <4 x float> %9, <4 x float> %2 60 %11 = add <4 x i32> %indexVec.0, <i32 4, i32 4, i32 4, i32 4> 61 %add.ptr = getelementptr inbounds float, ptr %pSrc.addr.0, i32 4 62 %sub = add nsw i32 %blkCnt.0, -4 63 %cmp = icmp sgt i32 %blkCnt.0, 4 64 br i1 %cmp, label %do.body, label %do.end 65 66do.end: ; preds = %do.body 67 %12 = bitcast <4 x float> %10 to <4 x i32> 68 %13 = tail call fast float @llvm.arm.mve.minnmv.f32.v4f32(float 0x426D1A94A0000000, <4 x float> %8) 69 %.splatinsert = insertelement <4 x float> undef, float %13, i32 0 70 %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer 71 %14 = fcmp fast ole <4 x float> %8, %.splat 72 %.splatinsert1 = insertelement <4 x i32> undef, i32 %blockSize, i32 0 73 %.splat2 = shufflevector <4 x i32> %.splatinsert1, <4 x i32> undef, <4 x i32> zeroinitializer 74 %15 = select <4 x i1> %14, <4 x i32> %12, <4 x i32> %.splat2 75 %16 = tail call i32 @llvm.arm.mve.minv.v4i32(i32 %blockSize, <4 x i32> %15, i32 1) 76 store i32 %16, ptr %pIndex, align 4 77 store float %13, ptr %pResult, align 4 78 ret void 79} 80 81declare { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32, i32) #1 82declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1 83declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>) #2 84declare float @llvm.arm.mve.minnmv.f32.v4f32(float, <4 x float>) #1 85declare i32 @llvm.arm.mve.minv.v4i32(i32, <4 x i32>, i32) #1 86