1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s 3 4define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) { 5; CHECK-LABEL: cmpeqz_v4i1: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vcmp.i32 eq, q0, zr 8; CHECK-NEXT: vpsel q0, q1, q0 9; CHECK-NEXT: bx lr 10entry: 11 %c1 = icmp eq <4 x i32> %a, zeroinitializer 12 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 13 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 14 ret <4 x i32> %s 15} 16 17define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b) { 18; CHECK-LABEL: cmpnez_v4i1: 19; CHECK: @ %bb.0: @ %entry 20; CHECK-NEXT: vcmp.i32 eq, q0, zr 21; CHECK-NEXT: vpsel q0, q1, q0 22; CHECK-NEXT: bx lr 23entry: 24 %c1 = icmp eq <4 x i32> %a, zeroinitializer 25 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 26 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 27 ret <4 x i32> %s 28} 29 30define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b) { 31; CHECK-LABEL: cmpsltz_v4i1: 32; CHECK: @ %bb.0: @ %entry 33; CHECK-NEXT: vcmp.i32 eq, q0, zr 34; CHECK-NEXT: vpsel q0, q1, q0 35; CHECK-NEXT: bx lr 36entry: 37 %c1 = icmp eq <4 x i32> %a, zeroinitializer 38 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 39 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 40 ret <4 x i32> %s 41} 42 43define arm_aapcs_vfpcc <4 x i32> @cmpsgtz_v4i1(<4 x i32> %a, <4 x i32> %b) { 44; CHECK-LABEL: cmpsgtz_v4i1: 45; CHECK: @ %bb.0: @ %entry 46; CHECK-NEXT: vcmp.i32 eq, q0, zr 47; CHECK-NEXT: vpsel q0, q1, q0 48; CHECK-NEXT: bx lr 49entry: 50 %c1 = icmp eq <4 x i32> %a, zeroinitializer 51 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 52 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 53 ret <4 x i32> %s 54} 55 56define arm_aapcs_vfpcc <4 x i32> @cmpslez_v4i1(<4 x i32> %a, <4 x i32> %b) { 57; CHECK-LABEL: cmpslez_v4i1: 58; CHECK: @ %bb.0: @ %entry 59; CHECK-NEXT: vcmp.i32 eq, q0, zr 60; CHECK-NEXT: vpsel q0, q1, q0 61; CHECK-NEXT: bx lr 62entry: 63 %c1 = icmp eq <4 x i32> %a, zeroinitializer 64 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 65 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 66 ret <4 x i32> %s 67} 68 69define arm_aapcs_vfpcc <4 x i32> @cmpsgez_v4i1(<4 x i32> %a, <4 x i32> %b) { 70; CHECK-LABEL: cmpsgez_v4i1: 71; CHECK: @ %bb.0: @ %entry 72; CHECK-NEXT: vcmp.i32 eq, q0, zr 73; CHECK-NEXT: vpsel q0, q1, q0 74; CHECK-NEXT: bx lr 75entry: 76 %c1 = icmp eq <4 x i32> %a, zeroinitializer 77 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 78 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 79 ret <4 x i32> %s 80} 81 82define arm_aapcs_vfpcc <4 x i32> @cmpultz_v4i1(<4 x i32> %a, <4 x i32> %b) { 83; CHECK-LABEL: cmpultz_v4i1: 84; CHECK: @ %bb.0: @ %entry 85; CHECK-NEXT: vcmp.i32 eq, q0, zr 86; CHECK-NEXT: vpsel q0, q1, q0 87; CHECK-NEXT: bx lr 88entry: 89 %c1 = icmp eq <4 x i32> %a, zeroinitializer 90 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 91 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 92 ret <4 x i32> %s 93} 94 95define arm_aapcs_vfpcc <4 x i32> @cmpugtz_v4i1(<4 x i32> %a, <4 x i32> %b) { 96; CHECK-LABEL: cmpugtz_v4i1: 97; CHECK: @ %bb.0: @ %entry 98; CHECK-NEXT: vcmp.i32 eq, q0, zr 99; CHECK-NEXT: vpsel q0, q1, q0 100; CHECK-NEXT: bx lr 101entry: 102 %c1 = icmp eq <4 x i32> %a, zeroinitializer 103 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 104 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 105 ret <4 x i32> %s 106} 107 108define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) { 109; CHECK-LABEL: cmpulez_v4i1: 110; CHECK: @ %bb.0: @ %entry 111; CHECK-NEXT: vcmp.i32 eq, q0, zr 112; CHECK-NEXT: vpsel q0, q1, q0 113; CHECK-NEXT: bx lr 114entry: 115 %c1 = icmp eq <4 x i32> %a, zeroinitializer 116 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 117 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 118 ret <4 x i32> %s 119} 120 121define arm_aapcs_vfpcc <4 x i32> @cmpugez_v4i1(<4 x i32> %a, <4 x i32> %b) { 122; CHECK-LABEL: cmpugez_v4i1: 123; CHECK: @ %bb.0: @ %entry 124; CHECK-NEXT: vcmp.i32 eq, q0, zr 125; CHECK-NEXT: vpsel q0, q1, q0 126; CHECK-NEXT: bx lr 127entry: 128 %c1 = icmp eq <4 x i32> %a, zeroinitializer 129 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 130 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 131 ret <4 x i32> %s 132} 133 134 135 136define arm_aapcs_vfpcc <4 x i32> @cmpeq_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 137; CHECK-LABEL: cmpeq_v4i1: 138; CHECK: @ %bb.0: @ %entry 139; CHECK-NEXT: vcmp.i32 eq, q0, zr 140; CHECK-NEXT: vpsel q0, q1, q0 141; CHECK-NEXT: bx lr 142entry: 143 %c1 = icmp eq <4 x i32> %a, zeroinitializer 144 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 145 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 146 ret <4 x i32> %s 147} 148 149define arm_aapcs_vfpcc <4 x i32> @cmpne_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 150; CHECK-LABEL: cmpne_v4i1: 151; CHECK: @ %bb.0: @ %entry 152; CHECK-NEXT: vcmp.i32 eq, q0, zr 153; CHECK-NEXT: vpsel q0, q1, q0 154; CHECK-NEXT: bx lr 155entry: 156 %c1 = icmp eq <4 x i32> %a, zeroinitializer 157 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 158 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 159 ret <4 x i32> %s 160} 161 162define arm_aapcs_vfpcc <4 x i32> @cmpslt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 163; CHECK-LABEL: cmpslt_v4i1: 164; CHECK: @ %bb.0: @ %entry 165; CHECK-NEXT: vcmp.i32 eq, q0, zr 166; CHECK-NEXT: vpsel q0, q1, q0 167; CHECK-NEXT: bx lr 168entry: 169 %c1 = icmp eq <4 x i32> %a, zeroinitializer 170 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 171 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 172 ret <4 x i32> %s 173} 174 175define arm_aapcs_vfpcc <4 x i32> @cmpsgt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 176; CHECK-LABEL: cmpsgt_v4i1: 177; CHECK: @ %bb.0: @ %entry 178; CHECK-NEXT: vcmp.i32 eq, q0, zr 179; CHECK-NEXT: vpsel q0, q1, q0 180; CHECK-NEXT: bx lr 181entry: 182 %c1 = icmp eq <4 x i32> %a, zeroinitializer 183 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 184 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 185 ret <4 x i32> %s 186} 187 188define arm_aapcs_vfpcc <4 x i32> @cmpsle_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 189; CHECK-LABEL: cmpsle_v4i1: 190; CHECK: @ %bb.0: @ %entry 191; CHECK-NEXT: vcmp.i32 eq, q0, zr 192; CHECK-NEXT: vpsel q0, q1, q0 193; CHECK-NEXT: bx lr 194entry: 195 %c1 = icmp eq <4 x i32> %a, zeroinitializer 196 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 197 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 198 ret <4 x i32> %s 199} 200 201define arm_aapcs_vfpcc <4 x i32> @cmpsge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 202; CHECK-LABEL: cmpsge_v4i1: 203; CHECK: @ %bb.0: @ %entry 204; CHECK-NEXT: vcmp.i32 eq, q0, zr 205; CHECK-NEXT: vpsel q0, q1, q0 206; CHECK-NEXT: bx lr 207entry: 208 %c1 = icmp eq <4 x i32> %a, zeroinitializer 209 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 210 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 211 ret <4 x i32> %s 212} 213 214define arm_aapcs_vfpcc <4 x i32> @cmpult_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 215; CHECK-LABEL: cmpult_v4i1: 216; CHECK: @ %bb.0: @ %entry 217; CHECK-NEXT: vcmp.i32 eq, q0, zr 218; CHECK-NEXT: vpsel q0, q1, q0 219; CHECK-NEXT: bx lr 220entry: 221 %c1 = icmp eq <4 x i32> %a, zeroinitializer 222 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 223 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 224 ret <4 x i32> %s 225} 226 227define arm_aapcs_vfpcc <4 x i32> @cmpugt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 228; CHECK-LABEL: cmpugt_v4i1: 229; CHECK: @ %bb.0: @ %entry 230; CHECK-NEXT: vcmp.i32 eq, q0, zr 231; CHECK-NEXT: vpsel q0, q1, q0 232; CHECK-NEXT: bx lr 233entry: 234 %c1 = icmp eq <4 x i32> %a, zeroinitializer 235 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 236 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 237 ret <4 x i32> %s 238} 239 240define arm_aapcs_vfpcc <4 x i32> @cmpule_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 241; CHECK-LABEL: cmpule_v4i1: 242; CHECK: @ %bb.0: @ %entry 243; CHECK-NEXT: vcmp.i32 eq, q0, zr 244; CHECK-NEXT: vpsel q0, q1, q0 245; CHECK-NEXT: bx lr 246entry: 247 %c1 = icmp eq <4 x i32> %a, zeroinitializer 248 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 249 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 250 ret <4 x i32> %s 251} 252 253define arm_aapcs_vfpcc <4 x i32> @cmpuge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 254; CHECK-LABEL: cmpuge_v4i1: 255; CHECK: @ %bb.0: @ %entry 256; CHECK-NEXT: vcmp.i32 eq, q0, zr 257; CHECK-NEXT: vpsel q0, q1, q0 258; CHECK-NEXT: bx lr 259entry: 260 %c1 = icmp eq <4 x i32> %a, zeroinitializer 261 %o = xor <4 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1> 262 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 263 ret <4 x i32> %s 264} 265 266 267 268 269define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) { 270; CHECK-LABEL: cmpeqz_v8i1: 271; CHECK: @ %bb.0: @ %entry 272; CHECK-NEXT: vcmp.i16 eq, q0, zr 273; CHECK-NEXT: vpsel q0, q1, q0 274; CHECK-NEXT: bx lr 275entry: 276 %c1 = icmp eq <8 x i16> %a, zeroinitializer 277 %o = xor <8 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1> 278 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b 279 ret <8 x i16> %s 280} 281 282define arm_aapcs_vfpcc <8 x i16> @cmpeq_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { 283; CHECK-LABEL: cmpeq_v8i1: 284; CHECK: @ %bb.0: @ %entry 285; CHECK-NEXT: vcmp.i16 eq, q0, zr 286; CHECK-NEXT: vpsel q0, q1, q0 287; CHECK-NEXT: bx lr 288entry: 289 %c1 = icmp eq <8 x i16> %a, zeroinitializer 290 %o = xor <8 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1> 291 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b 292 ret <8 x i16> %s 293} 294 295 296define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) { 297; CHECK-LABEL: cmpeqz_v16i1: 298; CHECK: @ %bb.0: @ %entry 299; CHECK-NEXT: vcmp.i8 eq, q0, zr 300; CHECK-NEXT: vpsel q0, q1, q0 301; CHECK-NEXT: bx lr 302entry: 303 %c1 = icmp eq <16 x i8> %a, zeroinitializer 304 %o = xor <16 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1> 305 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b 306 ret <16 x i8> %s 307} 308 309define arm_aapcs_vfpcc <16 x i8> @cmpeq_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 310; CHECK-LABEL: cmpeq_v16i1: 311; CHECK: @ %bb.0: @ %entry 312; CHECK-NEXT: vcmp.i8 eq, q0, zr 313; CHECK-NEXT: vpsel q0, q1, q0 314; CHECK-NEXT: bx lr 315entry: 316 %c1 = icmp eq <16 x i8> %a, zeroinitializer 317 %o = xor <16 x i1> %c1, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1> 318 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b 319 ret <16 x i8> %s 320} 321 322 323define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) { 324; CHECK-LABEL: cmpeqz_v2i1: 325; CHECK: @ %bb.0: @ %entry 326; CHECK-NEXT: vmov r0, r1, d0 327; CHECK-NEXT: orrs r0, r1 328; CHECK-NEXT: mov.w r1, #0 329; CHECK-NEXT: csetm r0, eq 330; CHECK-NEXT: bfi r1, r0, #0, #8 331; CHECK-NEXT: vmov r0, r2, d1 332; CHECK-NEXT: orrs r0, r2 333; CHECK-NEXT: csetm r0, eq 334; CHECK-NEXT: bfi r1, r0, #8, #8 335; CHECK-NEXT: vmsr p0, r1 336; CHECK-NEXT: vpsel q0, q1, q0 337; CHECK-NEXT: bx lr 338entry: 339 %c1 = icmp eq <2 x i64> %a, zeroinitializer 340 %o = xor <2 x i1> %c1, <i1 -1, i1 -1> 341 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b 342 ret <2 x i64> %s 343} 344 345define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) { 346; CHECK-LABEL: cmpeq_v2i1: 347; CHECK: @ %bb.0: @ %entry 348; CHECK-NEXT: vmov r0, r1, d0 349; CHECK-NEXT: orrs r0, r1 350; CHECK-NEXT: mov.w r1, #0 351; CHECK-NEXT: csetm r0, eq 352; CHECK-NEXT: bfi r1, r0, #0, #8 353; CHECK-NEXT: vmov r0, r2, d1 354; CHECK-NEXT: orrs r0, r2 355; CHECK-NEXT: csetm r0, eq 356; CHECK-NEXT: bfi r1, r0, #8, #8 357; CHECK-NEXT: vmsr p0, r1 358; CHECK-NEXT: vpsel q0, q1, q0 359; CHECK-NEXT: bx lr 360entry: 361 %c1 = icmp eq <2 x i64> %a, zeroinitializer 362 %o = xor <2 x i1> %c1, <i1 -1, i1 -1> 363 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b 364 ret <2 x i64> %s 365} 366 367define arm_aapcs_vfpcc <4 x i32> @vpnot_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 368; CHECK-LABEL: vpnot_v4i1: 369; CHECK: @ %bb.0: @ %entry 370; CHECK-NEXT: vpte.s32 lt, q0, zr 371; CHECK-NEXT: vcmpt.s32 gt, q1, zr 372; CHECK-NEXT: vcmpe.i32 eq, q2, zr 373; CHECK-NEXT: vpsel q0, q0, q1 374; CHECK-NEXT: bx lr 375entry: 376 %c1 = icmp slt <4 x i32> %a, zeroinitializer 377 %c2 = icmp sgt <4 x i32> %b, zeroinitializer 378 %c3 = icmp eq <4 x i32> %c, zeroinitializer 379 %o1 = and <4 x i1> %c1, %c2 380 %o2 = xor <4 x i1> %o1, <i1 -1, i1 -1, i1 -1, i1 -1> 381 %o = and <4 x i1> %c3, %o2 382 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 383 ret <4 x i32> %s 384} 385 386declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) 387declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) 388 389define arm_aapcs_vfpcc <4 x i32> @vpttet_v4i1(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) { 390; CHECK-LABEL: vpttet_v4i1: 391; CHECK: @ %bb.0: @ %entry 392; CHECK-NEXT: vpttet.s32 ge, q0, q2 393; CHECK-NEXT: vmovt q0, q2 394; CHECK-NEXT: vmovt q0, q2 395; CHECK-NEXT: vmove q0, q2 396; CHECK-NEXT: vmovt q0, q2 397; CHECK-NEXT: bx lr 398entry: 399 %0 = icmp sge <4 x i32> %x, %z 400 %1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %0, <4 x i32> %x) 401 %2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %0, <4 x i32> %1) 402 %3 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true> 403 %4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %3, <4 x i32> %2) 404 %5 = xor <4 x i1> %3, <i1 true, i1 true, i1 true, i1 true> 405 %6 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %5, <4 x i32> %4) 406 ret <4 x i32> %6 407} 408 409define arm_aapcs_vfpcc <4 x i32> @vpttee_v4i1(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) { 410; CHECK-LABEL: vpttee_v4i1: 411; CHECK: @ %bb.0: @ %entry 412; CHECK-NEXT: vmov q3, q2 413; CHECK-NEXT: vpttee.s32 ge, q0, q2 414; CHECK-NEXT: vmaxt.s32 q3, q0, q1 415; CHECK-NEXT: vcmpt.s32 gt, q0, zr 416; CHECK-NEXT: vmove q3, q2 417; CHECK-NEXT: vmove q3, q2 418; CHECK-NEXT: vmov q0, q3 419; CHECK-NEXT: bx lr 420entry: 421 %0 = icmp sge <4 x i32> %x, %z 422 %1 = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %x, <4 x i32> %y, i32 0, <4 x i1> %0, <4 x i32> %z) 423 %2 = icmp sgt <4 x i32> %x, zeroinitializer 424 %3 = and <4 x i1> %0, %2 425 %4 = xor <4 x i1> %3, <i1 true, i1 true, i1 true, i1 true> 426 %5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %4, <4 x i32> %1) 427 %6 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %4, <4 x i32> %5) 428 ret <4 x i32> %6 429} 430 431define arm_aapcs_vfpcc <4 x i32> @vpttee2_v4i1(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) { 432; CHECK-LABEL: vpttee2_v4i1: 433; CHECK: @ %bb.0: @ %entry 434; CHECK-NEXT: vmov q3, q2 435; CHECK-NEXT: vpttee.s32 ge, q0, q2 436; CHECK-NEXT: vmaxt.s32 q3, q0, q1 437; CHECK-NEXT: vcmpt.s32 gt, q0, zr 438; CHECK-NEXT: vcmpe.s32 gt, q1, zr 439; CHECK-NEXT: vmove q3, q2 440; CHECK-NEXT: vmov q0, q3 441; CHECK-NEXT: bx lr 442entry: 443 %0 = icmp sge <4 x i32> %x, %z 444 %1 = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %x, <4 x i32> %y, i32 0, <4 x i1> %0, <4 x i32> %z) 445 %2 = icmp sgt <4 x i32> %x, zeroinitializer 446 %3 = and <4 x i1> %0, %2 447 %4 = xor <4 x i1> %3, <i1 true, i1 true, i1 true, i1 true> 448 %5 = icmp sgt <4 x i32> %y, zeroinitializer 449 %6 = and <4 x i1> %5, %4 450 %7 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %6, <4 x i32> %1) 451 ret <4 x i32> %7 452} 453 454define arm_aapcs_vfpcc <4 x i32> @vpttte_v4i1(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) { 455; CHECK-LABEL: vpttte_v4i1: 456; CHECK: @ %bb.0: @ %entry 457; CHECK-NEXT: vmov q3, q2 458; CHECK-NEXT: vpttte.s32 ge, q0, q2 459; CHECK-NEXT: vmaxt.s32 q3, q0, q1 460; CHECK-NEXT: vcmpt.s32 gt, q0, zr 461; CHECK-NEXT: vmovt q3, q2 462; CHECK-NEXT: vmove q3, q2 463; CHECK-NEXT: vmov q0, q3 464; CHECK-NEXT: bx lr 465entry: 466 %0 = icmp sge <4 x i32> %x, %z 467 %1 = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %x, <4 x i32> %y, i32 0, <4 x i1> %0, <4 x i32> %z) 468 %2 = icmp sgt <4 x i32> %x, zeroinitializer 469 %3 = and <4 x i1> %0, %2 470 %4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %3, <4 x i32> %1) 471 %5 = xor <4 x i1> %3, <i1 true, i1 true, i1 true, i1 true> 472 %6 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %z, <4 x i32> %z, <4 x i1> %5, <4 x i32> %4) 473 ret <4 x i32> %6 474} 475