1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - -verify-machineinstrs | FileCheck %s 3 4--- | 5 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 6 target triple = "thumbv8.1m.main-none-unknown-eabi" 7 8 define arm_aapcs_vfpcc void @reg(<8 x i16> %acc0, <8 x i16> %acc1, ptr nocapture %px, i16 signext %p0) #0 { 9 entry: 10 %0 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 13107) 11 %1 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %0) 12 %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 52428) 13 %3 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %2) 14 %4 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %0) 15 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %2) 16 store i32 %1, ptr %px, align 4 17 %arrayidx1 = getelementptr inbounds i32, ptr %px, i32 1 18 store i32 %3, ptr %arrayidx1, align 4 19 %arrayidx2 = getelementptr inbounds i32, ptr %px, i32 2 20 store i32 %4, ptr %arrayidx2, align 4 21 %arrayidx3 = getelementptr inbounds i32, ptr %px, i32 3 22 store i32 %5, ptr %arrayidx3, align 4 23 ret void 24 } 25 26 declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1 27 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 28 declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>) #1 29 30 attributes #0 = { "target-features"="+mve" } 31 32... 33--- 34name: reg 35alignment: 2 36tracksRegLiveness: true 37registers: 38 - { id: 0, class: mqpr, preferred-register: '' } 39 - { id: 1, class: mqpr, preferred-register: '' } 40 - { id: 2, class: gpr, preferred-register: '' } 41 - { id: 3, class: gpr, preferred-register: '' } 42 - { id: 4, class: rgpr, preferred-register: '' } 43 - { id: 5, class: vccr, preferred-register: '' } 44 - { id: 6, class: tgpreven, preferred-register: '' } 45 - { id: 7, class: rgpr, preferred-register: '' } 46 - { id: 8, class: vccr, preferred-register: '' } 47 - { id: 9, class: tgpreven, preferred-register: '' } 48 - { id: 10, class: tgpreven, preferred-register: '' } 49 - { id: 11, class: tgpreven, preferred-register: '' } 50liveins: 51 - { reg: '$q0', virtual-reg: '%0' } 52 - { reg: '$q1', virtual-reg: '%1' } 53 - { reg: '$r0', virtual-reg: '%2' } 54body: | 55 bb.0.entry: 56 liveins: $q0, $q1, $r0 57 58 ; CHECK-LABEL: name: reg 59 ; CHECK: liveins: $q0, $q1, $r0 60 ; CHECK-NEXT: {{ $}} 61 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0 62 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:mqpr = COPY $q1 63 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:mqpr = COPY $q0 64 ; CHECK-NEXT: [[t2MOVi16_:%[0-9]+]]:rgpr = t2MOVi16 52428, 14 /* CC::al */, $noreg 65 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vccr = COPY [[t2MOVi16_]] 66 ; CHECK-NEXT: [[MVE_VADDVs16no_acc:%[0-9]+]]:tgpreven = MVE_VADDVs16no_acc [[COPY2]], 1, [[COPY3]], $noreg 67 ; CHECK-NEXT: [[t2MOVi16_1:%[0-9]+]]:rgpr = t2MOVi16 13107, 14 /* CC::al */, $noreg 68 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vccr = COPY [[t2MOVi16_1]] 69 ; CHECK-NEXT: [[MVE_VADDVs16no_acc1:%[0-9]+]]:tgpreven = MVE_VADDVs16no_acc [[COPY2]], 1, [[COPY4]], $noreg 70 ; CHECK-NEXT: [[MVE_VADDVs16no_acc2:%[0-9]+]]:tgpreven = MVE_VADDVs16no_acc [[COPY1]], 1, [[COPY4]], $noreg 71 ; CHECK-NEXT: [[MVE_VADDVs16no_acc3:%[0-9]+]]:tgpreven = MVE_VADDVs16no_acc [[COPY1]], 1, [[COPY3]], $noreg 72 ; CHECK-NEXT: t2STRi12 killed [[MVE_VADDVs16no_acc1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.px) 73 ; CHECK-NEXT: t2STRi12 killed [[MVE_VADDVs16no_acc]], [[COPY]], 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx1) 74 ; CHECK-NEXT: t2STRi12 killed [[MVE_VADDVs16no_acc2]], [[COPY]], 8, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx2) 75 ; CHECK-NEXT: t2STRi12 killed [[MVE_VADDVs16no_acc3]], [[COPY]], 12, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx3) 76 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg 77 %2:gpr = COPY $r0 78 %1:mqpr = COPY $q1 79 %0:mqpr = COPY $q0 80 %4:rgpr = t2MOVi16 52428, 14 /* CC::al */, $noreg 81 %5:vccr = COPY %4 82 %6:tgpreven = MVE_VADDVs16no_acc %0, 1, %5, $noreg 83 t2STRi12 killed %6, %2, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx1) 84 %7:rgpr = t2MOVi16 13107, 14 /* CC::al */, $noreg 85 %8:vccr = COPY %7 86 %9:tgpreven = MVE_VADDVs16no_acc %0, 1, %8, $noreg 87 t2STRi12 killed %9, %2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.px) 88 %10:tgpreven = MVE_VADDVs16no_acc %1, 1, %8, $noreg 89 t2STRi12 killed %10, %2, 8, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx2) 90 %11:tgpreven = MVE_VADDVs16no_acc %1, 1, %5, $noreg 91 t2STRi12 killed %11, %2, 12, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx3) 92 tBX_RET 14 /* CC::al */, $noreg 93 94... 95