xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-pred-const.ll (revision 255ad7342436ff4901d39579f694857f83386dad) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
3
4define arm_aapcs_vfpcc i32 @build_v2i_v2i1_1() {
5; CHECK-LABEL: build_v2i_v2i1_1:
6; CHECK:       @ %bb.0:
7; CHECK-NEXT:    movw r0, #65535
8; CHECK-NEXT:    bx lr
9  %r = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> <i1 1, i1 1>)
10  ret i32 %r
11}
12define arm_aapcs_vfpcc i32 @build_v2i_v2i1_0() {
13; CHECK-LABEL: build_v2i_v2i1_0:
14; CHECK:       @ %bb.0:
15; CHECK-NEXT:    movs r0, #0
16; CHECK-NEXT:    bx lr
17  %r = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> <i1 0, i1 0>)
18  ret i32 %r
19}
20define arm_aapcs_vfpcc i32 @build_v2i_v2i1_5() {
21; CHECK-LABEL: build_v2i_v2i1_5:
22; CHECK:       @ %bb.0:
23; CHECK-NEXT:    mov.w r0, #65280
24; CHECK-NEXT:    bx lr
25  %r = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> <i1 0, i1 1>)
26  ret i32 %r
27}
28
29define arm_aapcs_vfpcc i32 @build_v2i_v4i1_1() {
30; CHECK-LABEL: build_v2i_v4i1_1:
31; CHECK:       @ %bb.0:
32; CHECK-NEXT:    movw r0, #65535
33; CHECK-NEXT:    bx lr
34  %r = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 1, i1 1, i1 1, i1 1>)
35  ret i32 %r
36}
37define arm_aapcs_vfpcc i32 @build_v2i_v4i1_0() {
38; CHECK-LABEL: build_v2i_v4i1_0:
39; CHECK:       @ %bb.0:
40; CHECK-NEXT:    movs r0, #0
41; CHECK-NEXT:    bx lr
42  %r = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 0, i1 0, i1 0>)
43  ret i32 %r
44}
45define arm_aapcs_vfpcc i32 @build_v2i_v4i1_5() {
46; CHECK-LABEL: build_v2i_v4i1_5:
47; CHECK:       @ %bb.0:
48; CHECK-NEXT:    movw r0, #61680
49; CHECK-NEXT:    bx lr
50  %r = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 1, i1 0, i1 1>)
51  ret i32 %r
52}
53
54define arm_aapcs_vfpcc i32 @build_v2i_v8i1_1() {
55; CHECK-LABEL: build_v2i_v8i1_1:
56; CHECK:       @ %bb.0:
57; CHECK-NEXT:    movw r0, #65535
58; CHECK-NEXT:    bx lr
59  %r = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>)
60  ret i32 %r
61}
62define arm_aapcs_vfpcc i32 @build_v2i_v8i1_0() {
63; CHECK-LABEL: build_v2i_v8i1_0:
64; CHECK:       @ %bb.0:
65; CHECK-NEXT:    movs r0, #0
66; CHECK-NEXT:    bx lr
67  %r = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>)
68  ret i32 %r
69}
70define arm_aapcs_vfpcc i32 @build_v2i_v8i1_5() {
71; CHECK-LABEL: build_v2i_v8i1_5:
72; CHECK:       @ %bb.0:
73; CHECK-NEXT:    movw r0, #52428
74; CHECK-NEXT:    bx lr
75  %r = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
76  ret i32 %r
77}
78
79define arm_aapcs_vfpcc i32 @build_v2i_v16i1_1() {
80; CHECK-LABEL: build_v2i_v16i1_1:
81; CHECK:       @ %bb.0:
82; CHECK-NEXT:    movw r0, #65535
83; CHECK-NEXT:    bx lr
84  %r = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>)
85  ret i32 %r
86}
87define arm_aapcs_vfpcc i32 @build_v2i_v16i1_0() {
88; CHECK-LABEL: build_v2i_v16i1_0:
89; CHECK:       @ %bb.0:
90; CHECK-NEXT:    movs r0, #0
91; CHECK-NEXT:    bx lr
92  %r = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>)
93  ret i32 %r
94}
95define arm_aapcs_vfpcc i32 @build_v2i_v16i1_5() {
96; CHECK-LABEL: build_v2i_v16i1_5:
97; CHECK:       @ %bb.0:
98; CHECK-NEXT:    movw r0, #43690
99; CHECK-NEXT:    bx lr
100  %r = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
101  ret i32 %r
102}
103
104
105
106define arm_aapcs_vfpcc <2 x i64> @build_i2v_v2i1_1() {
107; CHECK-LABEL: build_i2v_v2i1_1:
108; CHECK:       @ %bb.0:
109; CHECK-NEXT:    movw r0, #65535
110; CHECK-NEXT:    vmov.i32 q0, #0x0
111; CHECK-NEXT:    vmsr p0, r0
112; CHECK-NEXT:    vmov.i8 q1, #0xff
113; CHECK-NEXT:    vpsel q0, q1, q0
114; CHECK-NEXT:    bx lr
115  %c = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 65535)
116  %r = select <2 x i1> %c, <2 x i64> <i64 18446744073709551615, i64 18446744073709551615>, <2 x i64> <i64 0, i64 0>
117  ret <2 x i64> %r
118}
119define arm_aapcs_vfpcc <2 x i64> @build_i2v_v2i1_0() {
120; CHECK-LABEL: build_i2v_v2i1_0:
121; CHECK:       @ %bb.0:
122; CHECK-NEXT:    movs r0, #0
123; CHECK-NEXT:    vmov.i32 q0, #0x0
124; CHECK-NEXT:    vmsr p0, r0
125; CHECK-NEXT:    vmov.i8 q1, #0xff
126; CHECK-NEXT:    vpsel q0, q1, q0
127; CHECK-NEXT:    bx lr
128  %c = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 0)
129  %r = select <2 x i1> %c, <2 x i64> <i64 18446744073709551615, i64 18446744073709551615>, <2 x i64> <i64 0, i64 0>
130  ret <2 x i64> %r
131}
132define arm_aapcs_vfpcc <2 x i64> @build_i2v_v2i1_5() {
133; CHECK-LABEL: build_i2v_v2i1_5:
134; CHECK:       @ %bb.0:
135; CHECK-NEXT:    movw r0, #61680
136; CHECK-NEXT:    vmov.i32 q0, #0x0
137; CHECK-NEXT:    vmsr p0, r0
138; CHECK-NEXT:    vmov.i8 q1, #0xff
139; CHECK-NEXT:    vpsel q0, q1, q0
140; CHECK-NEXT:    bx lr
141  %c = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 61680)
142  %r = select <2 x i1> %c, <2 x i64> <i64 18446744073709551615, i64 18446744073709551615>, <2 x i64> <i64 0, i64 0>
143  ret <2 x i64> %r
144}
145
146define arm_aapcs_vfpcc <4 x i32> @build_i2v_v4i1_1() {
147; CHECK-LABEL: build_i2v_v4i1_1:
148; CHECK:       @ %bb.0:
149; CHECK-NEXT:    movw r0, #65535
150; CHECK-NEXT:    vmov.i32 q0, #0x0
151; CHECK-NEXT:    vmsr p0, r0
152; CHECK-NEXT:    vmov.i8 q1, #0xff
153; CHECK-NEXT:    vpsel q0, q1, q0
154; CHECK-NEXT:    bx lr
155  %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 65535)
156  %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
157  ret <4 x i32> %r
158}
159define arm_aapcs_vfpcc <4 x i32> @build_i2v_v4i1_0() {
160; CHECK-LABEL: build_i2v_v4i1_0:
161; CHECK:       @ %bb.0:
162; CHECK-NEXT:    movs r0, #0
163; CHECK-NEXT:    vmov.i32 q0, #0x0
164; CHECK-NEXT:    vmsr p0, r0
165; CHECK-NEXT:    vmov.i8 q1, #0xff
166; CHECK-NEXT:    vpsel q0, q1, q0
167; CHECK-NEXT:    bx lr
168  %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 0)
169  %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
170  ret <4 x i32> %r
171}
172define arm_aapcs_vfpcc <4 x i32> @build_i2v_v4i1_5() {
173; CHECK-LABEL: build_i2v_v4i1_5:
174; CHECK:       @ %bb.0:
175; CHECK-NEXT:    movw r0, #61680
176; CHECK-NEXT:    vmov.i32 q0, #0x0
177; CHECK-NEXT:    vmsr p0, r0
178; CHECK-NEXT:    vmov.i8 q1, #0xff
179; CHECK-NEXT:    vpsel q0, q1, q0
180; CHECK-NEXT:    bx lr
181  %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 61680)
182  %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
183  ret <4 x i32> %r
184}
185
186define arm_aapcs_vfpcc <8 x i16> @build_i2v_v8i1_1() {
187; CHECK-LABEL: build_i2v_v8i1_1:
188; CHECK:       @ %bb.0:
189; CHECK-NEXT:    movw r0, #65535
190; CHECK-NEXT:    vmov.i32 q0, #0x0
191; CHECK-NEXT:    vmsr p0, r0
192; CHECK-NEXT:    vmov.i8 q1, #0xff
193; CHECK-NEXT:    vpsel q0, q1, q0
194; CHECK-NEXT:    bx lr
195  %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 65535)
196  %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
197  ret <8 x i16> %r
198}
199define arm_aapcs_vfpcc <8 x i16> @build_i2v_v8i1_0() {
200; CHECK-LABEL: build_i2v_v8i1_0:
201; CHECK:       @ %bb.0:
202; CHECK-NEXT:    movs r0, #0
203; CHECK-NEXT:    vmov.i32 q0, #0x0
204; CHECK-NEXT:    vmsr p0, r0
205; CHECK-NEXT:    vmov.i8 q1, #0xff
206; CHECK-NEXT:    vpsel q0, q1, q0
207; CHECK-NEXT:    bx lr
208  %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 0)
209  %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
210  ret <8 x i16> %r
211}
212define arm_aapcs_vfpcc <8 x i16> @build_i2v_v8i1_5() {
213; CHECK-LABEL: build_i2v_v8i1_5:
214; CHECK:       @ %bb.0:
215; CHECK-NEXT:    movw r0, #52428
216; CHECK-NEXT:    vmov.i32 q0, #0x0
217; CHECK-NEXT:    vmsr p0, r0
218; CHECK-NEXT:    vmov.i8 q1, #0xff
219; CHECK-NEXT:    vpsel q0, q1, q0
220; CHECK-NEXT:    bx lr
221  %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 52428)
222  %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
223  ret <8 x i16> %r
224}
225
226define arm_aapcs_vfpcc <16 x i8> @build_i2v_v16i1_1() {
227; CHECK-LABEL: build_i2v_v16i1_1:
228; CHECK:       @ %bb.0:
229; CHECK-NEXT:    movw r0, #65535
230; CHECK-NEXT:    vmov.i32 q0, #0x0
231; CHECK-NEXT:    vmsr p0, r0
232; CHECK-NEXT:    vmov.i8 q1, #0xff
233; CHECK-NEXT:    vpsel q0, q1, q0
234; CHECK-NEXT:    bx lr
235  %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 65535)
236  %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
237  ret <16 x i8> %r
238}
239define arm_aapcs_vfpcc <16 x i8> @build_i2v_v16i1_0() {
240; CHECK-LABEL: build_i2v_v16i1_0:
241; CHECK:       @ %bb.0:
242; CHECK-NEXT:    movs r0, #0
243; CHECK-NEXT:    vmov.i32 q0, #0x0
244; CHECK-NEXT:    vmsr p0, r0
245; CHECK-NEXT:    vmov.i8 q1, #0xff
246; CHECK-NEXT:    vpsel q0, q1, q0
247; CHECK-NEXT:    bx lr
248  %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 0)
249  %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
250  ret <16 x i8> %r
251}
252define arm_aapcs_vfpcc <16 x i8> @build_i2v_v16i1_5() {
253; CHECK-LABEL: build_i2v_v16i1_5:
254; CHECK:       @ %bb.0:
255; CHECK-NEXT:    movw r0, #43690
256; CHECK-NEXT:    vmov.i32 q0, #0x0
257; CHECK-NEXT:    vmsr p0, r0
258; CHECK-NEXT:    vmov.i8 q1, #0xff
259; CHECK-NEXT:    vpsel q0, q1, q0
260; CHECK-NEXT:    bx lr
261  %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 43690)
262  %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
263  ret <16 x i8> %r
264}
265
266
267define arm_aapcs_vfpcc i32 @build_i2v2i_v2i1_5() {
268; CHECK-LABEL: build_i2v2i_v2i1_5:
269; CHECK:       @ %bb.0:
270; CHECK-NEXT:    movw r0, #61680
271; CHECK-NEXT:    bx lr
272  %c = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 61680)
273  %r = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %c)
274  ret i32 %r
275}
276define arm_aapcs_vfpcc i32 @build_i2v2i_v4i1_5() {
277; CHECK-LABEL: build_i2v2i_v4i1_5:
278; CHECK:       @ %bb.0:
279; CHECK-NEXT:    movw r0, #61680
280; CHECK-NEXT:    bx lr
281  %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 61680)
282  %r = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %c)
283  ret i32 %r
284}
285define arm_aapcs_vfpcc i32 @build_i2v2i_v8i1_5() {
286; CHECK-LABEL: build_i2v2i_v8i1_5:
287; CHECK:       @ %bb.0:
288; CHECK-NEXT:    movw r0, #52428
289; CHECK-NEXT:    bx lr
290  %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 52428)
291  %r = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %c)
292  ret i32 %r
293}
294define arm_aapcs_vfpcc i32 @build_i2v2i_v16i1_5() {
295; CHECK-LABEL: build_i2v2i_v16i1_5:
296; CHECK:       @ %bb.0:
297; CHECK-NEXT:    movw r0, #43690
298; CHECK-NEXT:    bx lr
299  %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 43690)
300  %r = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %c)
301  ret i32 %r
302}
303
304
305define arm_aapcs_vfpcc <2 x i64> @build_v2i2v_v4i1_v2i1_5() {
306; CHECK-LABEL: build_v2i2v_v4i1_v2i1_5:
307; CHECK:       @ %bb.0:
308; CHECK-NEXT:    movw r0, #61680
309; CHECK-NEXT:    vmov.i32 q0, #0x0
310; CHECK-NEXT:    vmsr p0, r0
311; CHECK-NEXT:    vmov.i8 q1, #0xff
312; CHECK-NEXT:    vpsel q0, q1, q0
313; CHECK-NEXT:    bx lr
314  %b = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 1, i1 0, i1 1>)
315  %c = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %b)
316  %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> zeroinitializer
317  ret <2 x i64> %r
318}
319define arm_aapcs_vfpcc <2 x i64> @build_v2i2v_v8i1_v2i1_5() {
320; CHECK-LABEL: build_v2i2v_v8i1_v2i1_5:
321; CHECK:       @ %bb.0:
322; CHECK-NEXT:    movw r0, #52428
323; CHECK-NEXT:    vmov.i32 q0, #0x0
324; CHECK-NEXT:    vmsr p0, r0
325; CHECK-NEXT:    vmov.i8 q1, #0xff
326; CHECK-NEXT:    vpsel q0, q1, q0
327; CHECK-NEXT:    bx lr
328  %b = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
329  %c = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %b)
330  %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> zeroinitializer
331  ret <2 x i64> %r
332}
333define arm_aapcs_vfpcc <2 x i64> @build_v2i2v_v16i1_v2i1_5() {
334; CHECK-LABEL: build_v2i2v_v16i1_v2i1_5:
335; CHECK:       @ %bb.0:
336; CHECK-NEXT:    movw r0, #43690
337; CHECK-NEXT:    vmov.i32 q0, #0x0
338; CHECK-NEXT:    vmsr p0, r0
339; CHECK-NEXT:    vmov.i8 q1, #0xff
340; CHECK-NEXT:    vpsel q0, q1, q0
341; CHECK-NEXT:    bx lr
342  %b = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
343  %c = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %b)
344  %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> zeroinitializer
345  ret <2 x i64> %r
346}
347
348define arm_aapcs_vfpcc <4 x i32> @build_v2i2v_v4i1_v4i1_5() {
349; CHECK-LABEL: build_v2i2v_v4i1_v4i1_5:
350; CHECK:       @ %bb.0:
351; CHECK-NEXT:    movw r0, #61680
352; CHECK-NEXT:    vmov.i32 q0, #0x0
353; CHECK-NEXT:    vmsr p0, r0
354; CHECK-NEXT:    vmov.i8 q1, #0xff
355; CHECK-NEXT:    vpsel q0, q1, q0
356; CHECK-NEXT:    bx lr
357  %b = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 1, i1 0, i1 1>)
358  %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %b)
359  %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
360  ret <4 x i32> %r
361}
362define arm_aapcs_vfpcc <4 x i32> @build_v2i2v_v8i1_v4i1_5() {
363; CHECK-LABEL: build_v2i2v_v8i1_v4i1_5:
364; CHECK:       @ %bb.0:
365; CHECK-NEXT:    movw r0, #52428
366; CHECK-NEXT:    vmov.i32 q0, #0x0
367; CHECK-NEXT:    vmsr p0, r0
368; CHECK-NEXT:    vmov.i8 q1, #0xff
369; CHECK-NEXT:    vpsel q0, q1, q0
370; CHECK-NEXT:    bx lr
371  %b = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
372  %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %b)
373  %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
374  ret <4 x i32> %r
375}
376define arm_aapcs_vfpcc <4 x i32> @build_v2i2v_v16i1_v4i1_5() {
377; CHECK-LABEL: build_v2i2v_v16i1_v4i1_5:
378; CHECK:       @ %bb.0:
379; CHECK-NEXT:    movw r0, #43690
380; CHECK-NEXT:    vmov.i32 q0, #0x0
381; CHECK-NEXT:    vmsr p0, r0
382; CHECK-NEXT:    vmov.i8 q1, #0xff
383; CHECK-NEXT:    vpsel q0, q1, q0
384; CHECK-NEXT:    bx lr
385  %b = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
386  %c = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %b)
387  %r = select <4 x i1> %c, <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
388  ret <4 x i32> %r
389}
390
391define arm_aapcs_vfpcc <8 x i16> @build_v2i2v_v4i1_v8i1_5() {
392; CHECK-LABEL: build_v2i2v_v4i1_v8i1_5:
393; CHECK:       @ %bb.0:
394; CHECK-NEXT:    movw r0, #61680
395; CHECK-NEXT:    vmov.i32 q0, #0x0
396; CHECK-NEXT:    vmsr p0, r0
397; CHECK-NEXT:    vmov.i8 q1, #0xff
398; CHECK-NEXT:    vpsel q0, q1, q0
399; CHECK-NEXT:    bx lr
400  %b = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 1, i1 0, i1 1>)
401  %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %b)
402  %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
403  ret <8 x i16> %r
404}
405define arm_aapcs_vfpcc <8 x i16> @build_v2i2v_v8i1_v8i1_5() {
406; CHECK-LABEL: build_v2i2v_v8i1_v8i1_5:
407; CHECK:       @ %bb.0:
408; CHECK-NEXT:    movw r0, #52428
409; CHECK-NEXT:    vmov.i32 q0, #0x0
410; CHECK-NEXT:    vmsr p0, r0
411; CHECK-NEXT:    vmov.i8 q1, #0xff
412; CHECK-NEXT:    vpsel q0, q1, q0
413; CHECK-NEXT:    bx lr
414  %b = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
415  %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %b)
416  %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
417  ret <8 x i16> %r
418}
419define arm_aapcs_vfpcc <8 x i16> @build_v2i2v_v16i1_v8i1_5() {
420; CHECK-LABEL: build_v2i2v_v16i1_v8i1_5:
421; CHECK:       @ %bb.0:
422; CHECK-NEXT:    movw r0, #43690
423; CHECK-NEXT:    vmov.i32 q0, #0x0
424; CHECK-NEXT:    vmsr p0, r0
425; CHECK-NEXT:    vmov.i8 q1, #0xff
426; CHECK-NEXT:    vpsel q0, q1, q0
427; CHECK-NEXT:    bx lr
428  %b = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
429  %c = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %b)
430  %r = select <8 x i1> %c, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
431  ret <8 x i16> %r
432}
433
434define arm_aapcs_vfpcc <16 x i8> @build_v2i2v_v4i1_v16i1_5() {
435; CHECK-LABEL: build_v2i2v_v4i1_v16i1_5:
436; CHECK:       @ %bb.0:
437; CHECK-NEXT:    movw r0, #61680
438; CHECK-NEXT:    vmov.i32 q0, #0x0
439; CHECK-NEXT:    vmsr p0, r0
440; CHECK-NEXT:    vmov.i8 q1, #0xff
441; CHECK-NEXT:    vpsel q0, q1, q0
442; CHECK-NEXT:    bx lr
443  %b = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> <i1 0, i1 1, i1 0, i1 1>)
444  %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %b)
445  %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
446  ret <16 x i8> %r
447}
448define arm_aapcs_vfpcc <16 x i8> @build_v2i2v_v8i1_v16i1_5() {
449; CHECK-LABEL: build_v2i2v_v8i1_v16i1_5:
450; CHECK:       @ %bb.0:
451; CHECK-NEXT:    movw r0, #52428
452; CHECK-NEXT:    vmov.i32 q0, #0x0
453; CHECK-NEXT:    vmsr p0, r0
454; CHECK-NEXT:    vmov.i8 q1, #0xff
455; CHECK-NEXT:    vpsel q0, q1, q0
456; CHECK-NEXT:    bx lr
457  %b = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
458  %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %b)
459  %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
460  ret <16 x i8> %r
461}
462define arm_aapcs_vfpcc <16 x i8> @build_v2i2v_v16i1_v16i1_5() {
463; CHECK-LABEL: build_v2i2v_v16i1_v16i1_5:
464; CHECK:       @ %bb.0:
465; CHECK-NEXT:    movw r0, #43690
466; CHECK-NEXT:    vmov.i32 q0, #0x0
467; CHECK-NEXT:    vmsr p0, r0
468; CHECK-NEXT:    vmov.i8 q1, #0xff
469; CHECK-NEXT:    vpsel q0, q1, q0
470; CHECK-NEXT:    bx lr
471  %b = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>)
472  %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %b)
473  %r = select <16 x i1> %c, <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
474  ret <16 x i8> %r
475}
476
477declare i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1>)
478declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>)
479declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>)
480declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>)
481
482declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32)
483declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
484declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
485declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
486