1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s 3 4define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) { 5; CHECK-LABEL: cmpeqz_v4i1: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vorr q2, q0, q1 8; CHECK-NEXT: vcmp.i32 eq, q2, zr 9; CHECK-NEXT: vpsel q0, q0, q1 10; CHECK-NEXT: bx lr 11entry: 12 %c1 = icmp eq <4 x i32> %a, zeroinitializer 13 %c2 = icmp eq <4 x i32> %b, zeroinitializer 14 %o = and <4 x i1> %c1, %c2 15 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 16 ret <4 x i32> %s 17} 18 19define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b) { 20; CHECK-LABEL: cmpnez_v4i1: 21; CHECK: @ %bb.0: @ %entry 22; CHECK-NEXT: vpt.i32 eq, q0, zr 23; CHECK-NEXT: vcmpt.i32 ne, q1, zr 24; CHECK-NEXT: vpsel q0, q0, q1 25; CHECK-NEXT: bx lr 26entry: 27 %c1 = icmp eq <4 x i32> %a, zeroinitializer 28 %c2 = icmp ne <4 x i32> %b, zeroinitializer 29 %o = and <4 x i1> %c1, %c2 30 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 31 ret <4 x i32> %s 32} 33 34define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b) { 35; CHECK-LABEL: cmpsltz_v4i1: 36; CHECK: @ %bb.0: @ %entry 37; CHECK-NEXT: vpt.i32 eq, q0, zr 38; CHECK-NEXT: vcmpt.s32 lt, q1, zr 39; CHECK-NEXT: vpsel q0, q0, q1 40; CHECK-NEXT: bx lr 41entry: 42 %c1 = icmp eq <4 x i32> %a, zeroinitializer 43 %c2 = icmp slt <4 x i32> %b, zeroinitializer 44 %o = and <4 x i1> %c1, %c2 45 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 46 ret <4 x i32> %s 47} 48 49define arm_aapcs_vfpcc <4 x i32> @cmpsgtz_v4i1(<4 x i32> %a, <4 x i32> %b) { 50; CHECK-LABEL: cmpsgtz_v4i1: 51; CHECK: @ %bb.0: @ %entry 52; CHECK-NEXT: vpt.i32 eq, q0, zr 53; CHECK-NEXT: vcmpt.s32 gt, q1, zr 54; CHECK-NEXT: vpsel q0, q0, q1 55; CHECK-NEXT: bx lr 56entry: 57 %c1 = icmp eq <4 x i32> %a, zeroinitializer 58 %c2 = icmp sgt <4 x i32> %b, zeroinitializer 59 %o = and <4 x i1> %c1, %c2 60 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 61 ret <4 x i32> %s 62} 63 64define arm_aapcs_vfpcc <4 x i32> @cmpslez_v4i1(<4 x i32> %a, <4 x i32> %b) { 65; CHECK-LABEL: cmpslez_v4i1: 66; CHECK: @ %bb.0: @ %entry 67; CHECK-NEXT: vpt.i32 eq, q0, zr 68; CHECK-NEXT: vcmpt.s32 le, q1, zr 69; CHECK-NEXT: vpsel q0, q0, q1 70; CHECK-NEXT: bx lr 71entry: 72 %c1 = icmp eq <4 x i32> %a, zeroinitializer 73 %c2 = icmp sle <4 x i32> %b, zeroinitializer 74 %o = and <4 x i1> %c1, %c2 75 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 76 ret <4 x i32> %s 77} 78 79define arm_aapcs_vfpcc <4 x i32> @cmpsgez_v4i1(<4 x i32> %a, <4 x i32> %b) { 80; CHECK-LABEL: cmpsgez_v4i1: 81; CHECK: @ %bb.0: @ %entry 82; CHECK-NEXT: vpt.i32 eq, q0, zr 83; CHECK-NEXT: vcmpt.s32 ge, q1, zr 84; CHECK-NEXT: vpsel q0, q0, q1 85; CHECK-NEXT: bx lr 86entry: 87 %c1 = icmp eq <4 x i32> %a, zeroinitializer 88 %c2 = icmp sge <4 x i32> %b, zeroinitializer 89 %o = and <4 x i1> %c1, %c2 90 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 91 ret <4 x i32> %s 92} 93 94define arm_aapcs_vfpcc <4 x i32> @cmpultz_v4i1(<4 x i32> %a, <4 x i32> %b) { 95; CHECK-LABEL: cmpultz_v4i1: 96; CHECK: @ %bb.0: @ %entry 97; CHECK-NEXT: vmov q0, q1 98; CHECK-NEXT: bx lr 99entry: 100 %c1 = icmp eq <4 x i32> %a, zeroinitializer 101 %c2 = icmp ult <4 x i32> %b, zeroinitializer 102 %o = and <4 x i1> %c1, %c2 103 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 104 ret <4 x i32> %s 105} 106 107define arm_aapcs_vfpcc <4 x i32> @cmpugtz_v4i1(<4 x i32> %a, <4 x i32> %b) { 108; CHECK-LABEL: cmpugtz_v4i1: 109; CHECK: @ %bb.0: @ %entry 110; CHECK-NEXT: vpt.i32 eq, q0, zr 111; CHECK-NEXT: vcmpt.i32 ne, q1, zr 112; CHECK-NEXT: vpsel q0, q0, q1 113; CHECK-NEXT: bx lr 114entry: 115 %c1 = icmp eq <4 x i32> %a, zeroinitializer 116 %c2 = icmp ugt <4 x i32> %b, zeroinitializer 117 %o = and <4 x i1> %c1, %c2 118 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 119 ret <4 x i32> %s 120} 121 122define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) { 123; CHECK-LABEL: cmpulez_v4i1: 124; CHECK: @ %bb.0: @ %entry 125; CHECK-NEXT: vmov.i32 q2, #0x0 126; CHECK-NEXT: vpt.i32 eq, q0, zr 127; CHECK-NEXT: vcmpt.u32 cs, q2, q1 128; CHECK-NEXT: vpsel q0, q0, q1 129; CHECK-NEXT: bx lr 130entry: 131 %c1 = icmp eq <4 x i32> %a, zeroinitializer 132 %c2 = icmp ule <4 x i32> %b, zeroinitializer 133 %o = and <4 x i1> %c1, %c2 134 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 135 ret <4 x i32> %s 136} 137 138define arm_aapcs_vfpcc <4 x i32> @cmpugez_v4i1(<4 x i32> %a, <4 x i32> %b) { 139; CHECK-LABEL: cmpugez_v4i1: 140; CHECK: @ %bb.0: @ %entry 141; CHECK-NEXT: vcmp.i32 eq, q0, zr 142; CHECK-NEXT: vpsel q0, q0, q1 143; CHECK-NEXT: bx lr 144entry: 145 %c1 = icmp eq <4 x i32> %a, zeroinitializer 146 %c2 = icmp uge <4 x i32> %b, zeroinitializer 147 %o = and <4 x i1> %c1, %c2 148 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 149 ret <4 x i32> %s 150} 151 152 153 154define arm_aapcs_vfpcc <4 x i32> @cmpeq_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 155; CHECK-LABEL: cmpeq_v4i1: 156; CHECK: @ %bb.0: @ %entry 157; CHECK-NEXT: vpt.i32 eq, q0, zr 158; CHECK-NEXT: vcmpt.i32 eq, q1, q2 159; CHECK-NEXT: vpsel q0, q0, q1 160; CHECK-NEXT: bx lr 161entry: 162 %c1 = icmp eq <4 x i32> %a, zeroinitializer 163 %c2 = icmp eq <4 x i32> %b, %c 164 %o = and <4 x i1> %c1, %c2 165 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 166 ret <4 x i32> %s 167} 168 169define arm_aapcs_vfpcc <4 x i32> @cmpne_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 170; CHECK-LABEL: cmpne_v4i1: 171; CHECK: @ %bb.0: @ %entry 172; CHECK-NEXT: vpt.i32 eq, q0, zr 173; CHECK-NEXT: vcmpt.i32 ne, q1, q2 174; CHECK-NEXT: vpsel q0, q0, q1 175; CHECK-NEXT: bx lr 176entry: 177 %c1 = icmp eq <4 x i32> %a, zeroinitializer 178 %c2 = icmp ne <4 x i32> %b, %c 179 %o = and <4 x i1> %c1, %c2 180 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 181 ret <4 x i32> %s 182} 183 184define arm_aapcs_vfpcc <4 x i32> @cmpslt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 185; CHECK-LABEL: cmpslt_v4i1: 186; CHECK: @ %bb.0: @ %entry 187; CHECK-NEXT: vpt.i32 eq, q0, zr 188; CHECK-NEXT: vcmpt.s32 gt, q2, q1 189; CHECK-NEXT: vpsel q0, q0, q1 190; CHECK-NEXT: bx lr 191entry: 192 %c1 = icmp eq <4 x i32> %a, zeroinitializer 193 %c2 = icmp slt <4 x i32> %b, %c 194 %o = and <4 x i1> %c1, %c2 195 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 196 ret <4 x i32> %s 197} 198 199define arm_aapcs_vfpcc <4 x i32> @cmpsgt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 200; CHECK-LABEL: cmpsgt_v4i1: 201; CHECK: @ %bb.0: @ %entry 202; CHECK-NEXT: vpt.i32 eq, q0, zr 203; CHECK-NEXT: vcmpt.s32 gt, q1, q2 204; CHECK-NEXT: vpsel q0, q0, q1 205; CHECK-NEXT: bx lr 206entry: 207 %c1 = icmp eq <4 x i32> %a, zeroinitializer 208 %c2 = icmp sgt <4 x i32> %b, %c 209 %o = and <4 x i1> %c1, %c2 210 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 211 ret <4 x i32> %s 212} 213 214define arm_aapcs_vfpcc <4 x i32> @cmpsle_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 215; CHECK-LABEL: cmpsle_v4i1: 216; CHECK: @ %bb.0: @ %entry 217; CHECK-NEXT: vpt.i32 eq, q0, zr 218; CHECK-NEXT: vcmpt.s32 ge, q2, q1 219; CHECK-NEXT: vpsel q0, q0, q1 220; CHECK-NEXT: bx lr 221entry: 222 %c1 = icmp eq <4 x i32> %a, zeroinitializer 223 %c2 = icmp sle <4 x i32> %b, %c 224 %o = and <4 x i1> %c1, %c2 225 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 226 ret <4 x i32> %s 227} 228 229define arm_aapcs_vfpcc <4 x i32> @cmpsge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 230; CHECK-LABEL: cmpsge_v4i1: 231; CHECK: @ %bb.0: @ %entry 232; CHECK-NEXT: vpt.i32 eq, q0, zr 233; CHECK-NEXT: vcmpt.s32 ge, q1, q2 234; CHECK-NEXT: vpsel q0, q0, q1 235; CHECK-NEXT: bx lr 236entry: 237 %c1 = icmp eq <4 x i32> %a, zeroinitializer 238 %c2 = icmp sge <4 x i32> %b, %c 239 %o = and <4 x i1> %c1, %c2 240 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 241 ret <4 x i32> %s 242} 243 244define arm_aapcs_vfpcc <4 x i32> @cmpult_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 245; CHECK-LABEL: cmpult_v4i1: 246; CHECK: @ %bb.0: @ %entry 247; CHECK-NEXT: vpt.i32 eq, q0, zr 248; CHECK-NEXT: vcmpt.u32 hi, q2, q1 249; CHECK-NEXT: vpsel q0, q0, q1 250; CHECK-NEXT: bx lr 251entry: 252 %c1 = icmp eq <4 x i32> %a, zeroinitializer 253 %c2 = icmp ult <4 x i32> %b, %c 254 %o = and <4 x i1> %c1, %c2 255 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 256 ret <4 x i32> %s 257} 258 259define arm_aapcs_vfpcc <4 x i32> @cmpugt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 260; CHECK-LABEL: cmpugt_v4i1: 261; CHECK: @ %bb.0: @ %entry 262; CHECK-NEXT: vpt.i32 eq, q0, zr 263; CHECK-NEXT: vcmpt.u32 hi, q1, q2 264; CHECK-NEXT: vpsel q0, q0, q1 265; CHECK-NEXT: bx lr 266entry: 267 %c1 = icmp eq <4 x i32> %a, zeroinitializer 268 %c2 = icmp ugt <4 x i32> %b, %c 269 %o = and <4 x i1> %c1, %c2 270 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 271 ret <4 x i32> %s 272} 273 274define arm_aapcs_vfpcc <4 x i32> @cmpule_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 275; CHECK-LABEL: cmpule_v4i1: 276; CHECK: @ %bb.0: @ %entry 277; CHECK-NEXT: vpt.i32 eq, q0, zr 278; CHECK-NEXT: vcmpt.u32 cs, q2, q1 279; CHECK-NEXT: vpsel q0, q0, q1 280; CHECK-NEXT: bx lr 281entry: 282 %c1 = icmp eq <4 x i32> %a, zeroinitializer 283 %c2 = icmp ule <4 x i32> %b, %c 284 %o = and <4 x i1> %c1, %c2 285 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 286 ret <4 x i32> %s 287} 288 289define arm_aapcs_vfpcc <4 x i32> @cmpuge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 290; CHECK-LABEL: cmpuge_v4i1: 291; CHECK: @ %bb.0: @ %entry 292; CHECK-NEXT: vpt.i32 eq, q0, zr 293; CHECK-NEXT: vcmpt.u32 cs, q1, q2 294; CHECK-NEXT: vpsel q0, q0, q1 295; CHECK-NEXT: bx lr 296entry: 297 %c1 = icmp eq <4 x i32> %a, zeroinitializer 298 %c2 = icmp uge <4 x i32> %b, %c 299 %o = and <4 x i1> %c1, %c2 300 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 301 ret <4 x i32> %s 302} 303 304 305define arm_aapcs_vfpcc <4 x i32> @cmpeqr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) { 306; CHECK-LABEL: cmpeqr_v4i1: 307; CHECK: @ %bb.0: @ %entry 308; CHECK-NEXT: vpt.i32 eq, q0, zr 309; CHECK-NEXT: vcmpt.i32 eq, q1, r0 310; CHECK-NEXT: vpsel q0, q0, q1 311; CHECK-NEXT: bx lr 312entry: 313 %c1 = icmp eq <4 x i32> %a, zeroinitializer 314 %i = insertelement <4 x i32> undef, i32 %c, i32 0 315 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 316 %c2 = icmp eq <4 x i32> %b, %sp 317 %o = and <4 x i1> %c1, %c2 318 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 319 ret <4 x i32> %s 320} 321 322define arm_aapcs_vfpcc <4 x i32> @cmpner_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) { 323; CHECK-LABEL: cmpner_v4i1: 324; CHECK: @ %bb.0: @ %entry 325; CHECK-NEXT: vpt.i32 eq, q0, zr 326; CHECK-NEXT: vcmpt.i32 ne, q1, r0 327; CHECK-NEXT: vpsel q0, q0, q1 328; CHECK-NEXT: bx lr 329entry: 330 %c1 = icmp eq <4 x i32> %a, zeroinitializer 331 %i = insertelement <4 x i32> undef, i32 %c, i32 0 332 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 333 %c2 = icmp ne <4 x i32> %b, %sp 334 %o = and <4 x i1> %c1, %c2 335 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 336 ret <4 x i32> %s 337} 338 339define arm_aapcs_vfpcc <4 x i32> @cmpsltr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) { 340; CHECK-LABEL: cmpsltr_v4i1: 341; CHECK: @ %bb.0: @ %entry 342; CHECK-NEXT: vpt.i32 eq, q0, zr 343; CHECK-NEXT: vcmpt.s32 lt, q1, r0 344; CHECK-NEXT: vpsel q0, q0, q1 345; CHECK-NEXT: bx lr 346entry: 347 %c1 = icmp eq <4 x i32> %a, zeroinitializer 348 %i = insertelement <4 x i32> undef, i32 %c, i32 0 349 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 350 %c2 = icmp slt <4 x i32> %b, %sp 351 %o = and <4 x i1> %c1, %c2 352 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 353 ret <4 x i32> %s 354} 355 356define arm_aapcs_vfpcc <4 x i32> @cmpsgtr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) { 357; CHECK-LABEL: cmpsgtr_v4i1: 358; CHECK: @ %bb.0: @ %entry 359; CHECK-NEXT: vpt.i32 eq, q0, zr 360; CHECK-NEXT: vcmpt.s32 gt, q1, r0 361; CHECK-NEXT: vpsel q0, q0, q1 362; CHECK-NEXT: bx lr 363entry: 364 %c1 = icmp eq <4 x i32> %a, zeroinitializer 365 %i = insertelement <4 x i32> undef, i32 %c, i32 0 366 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 367 %c2 = icmp sgt <4 x i32> %b, %sp 368 %o = and <4 x i1> %c1, %c2 369 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 370 ret <4 x i32> %s 371} 372 373define arm_aapcs_vfpcc <4 x i32> @cmpsler_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) { 374; CHECK-LABEL: cmpsler_v4i1: 375; CHECK: @ %bb.0: @ %entry 376; CHECK-NEXT: vpt.i32 eq, q0, zr 377; CHECK-NEXT: vcmpt.s32 le, q1, r0 378; CHECK-NEXT: vpsel q0, q0, q1 379; CHECK-NEXT: bx lr 380entry: 381 %c1 = icmp eq <4 x i32> %a, zeroinitializer 382 %i = insertelement <4 x i32> undef, i32 %c, i32 0 383 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 384 %c2 = icmp sle <4 x i32> %b, %sp 385 %o = and <4 x i1> %c1, %c2 386 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 387 ret <4 x i32> %s 388} 389 390define arm_aapcs_vfpcc <4 x i32> @cmpsger_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) { 391; CHECK-LABEL: cmpsger_v4i1: 392; CHECK: @ %bb.0: @ %entry 393; CHECK-NEXT: vpt.i32 eq, q0, zr 394; CHECK-NEXT: vcmpt.s32 ge, q1, r0 395; CHECK-NEXT: vpsel q0, q0, q1 396; CHECK-NEXT: bx lr 397entry: 398 %c1 = icmp eq <4 x i32> %a, zeroinitializer 399 %i = insertelement <4 x i32> undef, i32 %c, i32 0 400 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 401 %c2 = icmp sge <4 x i32> %b, %sp 402 %o = and <4 x i1> %c1, %c2 403 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 404 ret <4 x i32> %s 405} 406 407define arm_aapcs_vfpcc <4 x i32> @cmpultr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) { 408; CHECK-LABEL: cmpultr_v4i1: 409; CHECK: @ %bb.0: @ %entry 410; CHECK-NEXT: vdup.32 q2, r0 411; CHECK-NEXT: vpt.i32 eq, q0, zr 412; CHECK-NEXT: vcmpt.u32 hi, q2, q1 413; CHECK-NEXT: vpsel q0, q0, q1 414; CHECK-NEXT: bx lr 415entry: 416 %c1 = icmp eq <4 x i32> %a, zeroinitializer 417 %i = insertelement <4 x i32> undef, i32 %c, i32 0 418 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 419 %c2 = icmp ult <4 x i32> %b, %sp 420 %o = and <4 x i1> %c1, %c2 421 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 422 ret <4 x i32> %s 423} 424 425define arm_aapcs_vfpcc <4 x i32> @cmpugtr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) { 426; CHECK-LABEL: cmpugtr_v4i1: 427; CHECK: @ %bb.0: @ %entry 428; CHECK-NEXT: vpt.i32 eq, q0, zr 429; CHECK-NEXT: vcmpt.u32 hi, q1, r0 430; CHECK-NEXT: vpsel q0, q0, q1 431; CHECK-NEXT: bx lr 432entry: 433 %c1 = icmp eq <4 x i32> %a, zeroinitializer 434 %i = insertelement <4 x i32> undef, i32 %c, i32 0 435 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 436 %c2 = icmp ugt <4 x i32> %b, %sp 437 %o = and <4 x i1> %c1, %c2 438 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 439 ret <4 x i32> %s 440} 441 442define arm_aapcs_vfpcc <4 x i32> @cmpuler_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) { 443; CHECK-LABEL: cmpuler_v4i1: 444; CHECK: @ %bb.0: @ %entry 445; CHECK-NEXT: vdup.32 q2, r0 446; CHECK-NEXT: vpt.i32 eq, q0, zr 447; CHECK-NEXT: vcmpt.u32 cs, q2, q1 448; CHECK-NEXT: vpsel q0, q0, q1 449; CHECK-NEXT: bx lr 450entry: 451 %c1 = icmp eq <4 x i32> %a, zeroinitializer 452 %i = insertelement <4 x i32> undef, i32 %c, i32 0 453 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 454 %c2 = icmp ule <4 x i32> %b, %sp 455 %o = and <4 x i1> %c1, %c2 456 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 457 ret <4 x i32> %s 458} 459 460define arm_aapcs_vfpcc <4 x i32> @cmpuger_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) { 461; CHECK-LABEL: cmpuger_v4i1: 462; CHECK: @ %bb.0: @ %entry 463; CHECK-NEXT: vpt.i32 eq, q0, zr 464; CHECK-NEXT: vcmpt.u32 cs, q1, r0 465; CHECK-NEXT: vpsel q0, q0, q1 466; CHECK-NEXT: bx lr 467entry: 468 %c1 = icmp eq <4 x i32> %a, zeroinitializer 469 %i = insertelement <4 x i32> undef, i32 %c, i32 0 470 %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer 471 %c2 = icmp uge <4 x i32> %b, %sp 472 %o = and <4 x i1> %c1, %c2 473 %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b 474 ret <4 x i32> %s 475} 476 477 478 479define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) { 480; CHECK-LABEL: cmpeqz_v8i1: 481; CHECK: @ %bb.0: @ %entry 482; CHECK-NEXT: vorr q2, q0, q1 483; CHECK-NEXT: vcmp.i16 eq, q2, zr 484; CHECK-NEXT: vpsel q0, q0, q1 485; CHECK-NEXT: bx lr 486entry: 487 %c1 = icmp eq <8 x i16> %a, zeroinitializer 488 %c2 = icmp eq <8 x i16> %b, zeroinitializer 489 %o = and <8 x i1> %c1, %c2 490 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b 491 ret <8 x i16> %s 492} 493 494define arm_aapcs_vfpcc <8 x i16> @cmpeq_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { 495; CHECK-LABEL: cmpeq_v8i1: 496; CHECK: @ %bb.0: @ %entry 497; CHECK-NEXT: vpt.i16 eq, q0, zr 498; CHECK-NEXT: vcmpt.i16 eq, q1, q2 499; CHECK-NEXT: vpsel q0, q0, q1 500; CHECK-NEXT: bx lr 501entry: 502 %c1 = icmp eq <8 x i16> %a, zeroinitializer 503 %c2 = icmp eq <8 x i16> %b, %c 504 %o = and <8 x i1> %c1, %c2 505 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b 506 ret <8 x i16> %s 507} 508 509define arm_aapcs_vfpcc <8 x i16> @cmpeqr_v8i1(<8 x i16> %a, <8 x i16> %b, i16 %c) { 510; CHECK-LABEL: cmpeqr_v8i1: 511; CHECK: @ %bb.0: @ %entry 512; CHECK-NEXT: vpt.i16 eq, q0, zr 513; CHECK-NEXT: vcmpt.i16 eq, q1, r0 514; CHECK-NEXT: vpsel q0, q0, q1 515; CHECK-NEXT: bx lr 516entry: 517 %c1 = icmp eq <8 x i16> %a, zeroinitializer 518 %i = insertelement <8 x i16> undef, i16 %c, i32 0 519 %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer 520 %c2 = icmp eq <8 x i16> %b, %sp 521 %o = and <8 x i1> %c1, %c2 522 %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b 523 ret <8 x i16> %s 524} 525 526 527define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) { 528; CHECK-LABEL: cmpeqz_v16i1: 529; CHECK: @ %bb.0: @ %entry 530; CHECK-NEXT: vorr q2, q0, q1 531; CHECK-NEXT: vcmp.i8 eq, q2, zr 532; CHECK-NEXT: vpsel q0, q0, q1 533; CHECK-NEXT: bx lr 534entry: 535 %c1 = icmp eq <16 x i8> %a, zeroinitializer 536 %c2 = icmp eq <16 x i8> %b, zeroinitializer 537 %o = and <16 x i1> %c1, %c2 538 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b 539 ret <16 x i8> %s 540} 541 542define arm_aapcs_vfpcc <16 x i8> @cmpeq_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 543; CHECK-LABEL: cmpeq_v16i1: 544; CHECK: @ %bb.0: @ %entry 545; CHECK-NEXT: vpt.i8 eq, q0, zr 546; CHECK-NEXT: vcmpt.i8 eq, q1, q2 547; CHECK-NEXT: vpsel q0, q0, q1 548; CHECK-NEXT: bx lr 549entry: 550 %c1 = icmp eq <16 x i8> %a, zeroinitializer 551 %c2 = icmp eq <16 x i8> %b, %c 552 %o = and <16 x i1> %c1, %c2 553 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b 554 ret <16 x i8> %s 555} 556 557define arm_aapcs_vfpcc <16 x i8> @cmpeqr_v16i1(<16 x i8> %a, <16 x i8> %b, i8 %c) { 558; CHECK-LABEL: cmpeqr_v16i1: 559; CHECK: @ %bb.0: @ %entry 560; CHECK-NEXT: vpt.i8 eq, q0, zr 561; CHECK-NEXT: vcmpt.i8 eq, q1, r0 562; CHECK-NEXT: vpsel q0, q0, q1 563; CHECK-NEXT: bx lr 564entry: 565 %c1 = icmp eq <16 x i8> %a, zeroinitializer 566 %i = insertelement <16 x i8> undef, i8 %c, i32 0 567 %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer 568 %c2 = icmp eq <16 x i8> %b, %sp 569 %o = and <16 x i1> %c1, %c2 570 %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b 571 ret <16 x i8> %s 572} 573 574 575define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) { 576; CHECK-LABEL: cmpeqz_v2i1: 577; CHECK: @ %bb.0: @ %entry 578; CHECK-NEXT: vorr q2, q0, q1 579; CHECK-NEXT: vmov r0, r1, d4 580; CHECK-NEXT: orrs r0, r1 581; CHECK-NEXT: mov.w r1, #0 582; CHECK-NEXT: csetm r0, eq 583; CHECK-NEXT: bfi r1, r0, #0, #8 584; CHECK-NEXT: vmov r0, r2, d5 585; CHECK-NEXT: orrs r0, r2 586; CHECK-NEXT: csetm r0, eq 587; CHECK-NEXT: bfi r1, r0, #8, #8 588; CHECK-NEXT: vmsr p0, r1 589; CHECK-NEXT: vpsel q0, q0, q1 590; CHECK-NEXT: bx lr 591entry: 592 %c1 = icmp eq <2 x i64> %a, zeroinitializer 593 %c2 = icmp eq <2 x i64> %b, zeroinitializer 594 %o = and <2 x i1> %c1, %c2 595 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b 596 ret <2 x i64> %s 597} 598 599define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) { 600; CHECK-LABEL: cmpeq_v2i1: 601; CHECK: @ %bb.0: @ %entry 602; CHECK-NEXT: vmov r0, r1, d4 603; CHECK-NEXT: vmov r2, r3, d2 604; CHECK-NEXT: eors r1, r3 605; CHECK-NEXT: eors r0, r2 606; CHECK-NEXT: orrs r0, r1 607; CHECK-NEXT: vmov r1, r2, d0 608; CHECK-NEXT: orrs r1, r2 609; CHECK-NEXT: vmov r12, r2, d5 610; CHECK-NEXT: cset r1, eq 611; CHECK-NEXT: cmp r0, #0 612; CHECK-NEXT: csel r0, zr, r1, ne 613; CHECK-NEXT: movs r1, #0 614; CHECK-NEXT: rsbs r0, r0, #0 615; CHECK-NEXT: bfi r1, r0, #0, #8 616; CHECK-NEXT: vmov r3, r0, d3 617; CHECK-NEXT: eors r0, r2 618; CHECK-NEXT: eor.w r2, r3, r12 619; CHECK-NEXT: orrs r0, r2 620; CHECK-NEXT: vmov r2, r3, d1 621; CHECK-NEXT: orrs r2, r3 622; CHECK-NEXT: cset r2, eq 623; CHECK-NEXT: cmp r0, #0 624; CHECK-NEXT: csel r0, zr, r2, ne 625; CHECK-NEXT: rsbs r0, r0, #0 626; CHECK-NEXT: bfi r1, r0, #8, #8 627; CHECK-NEXT: vmsr p0, r1 628; CHECK-NEXT: vpsel q0, q0, q1 629; CHECK-NEXT: bx lr 630entry: 631 %c1 = icmp eq <2 x i64> %a, zeroinitializer 632 %c2 = icmp eq <2 x i64> %b, %c 633 %o = and <2 x i1> %c1, %c2 634 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b 635 ret <2 x i64> %s 636} 637 638define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c) { 639; CHECK-LABEL: cmpeqr_v2i1: 640; CHECK: @ %bb.0: @ %entry 641; CHECK-NEXT: vmov r2, r3, d2 642; CHECK-NEXT: eors r3, r1 643; CHECK-NEXT: eors r2, r0 644; CHECK-NEXT: orr.w r12, r2, r3 645; CHECK-NEXT: vmov r3, r2, d0 646; CHECK-NEXT: orrs r2, r3 647; CHECK-NEXT: mov.w r3, #0 648; CHECK-NEXT: cset r2, eq 649; CHECK-NEXT: cmp.w r12, #0 650; CHECK-NEXT: csel r2, zr, r2, ne 651; CHECK-NEXT: rsbs r2, r2, #0 652; CHECK-NEXT: bfi r3, r2, #0, #8 653; CHECK-NEXT: vmov r12, r2, d3 654; CHECK-NEXT: eors r1, r2 655; CHECK-NEXT: eor.w r0, r0, r12 656; CHECK-NEXT: orrs r0, r1 657; CHECK-NEXT: vmov r1, r2, d1 658; CHECK-NEXT: orrs r1, r2 659; CHECK-NEXT: cset r1, eq 660; CHECK-NEXT: cmp r0, #0 661; CHECK-NEXT: csel r0, zr, r1, ne 662; CHECK-NEXT: rsbs r0, r0, #0 663; CHECK-NEXT: bfi r3, r0, #8, #8 664; CHECK-NEXT: vmsr p0, r3 665; CHECK-NEXT: vpsel q0, q0, q1 666; CHECK-NEXT: bx lr 667entry: 668 %c1 = icmp eq <2 x i64> %a, zeroinitializer 669 %i = insertelement <2 x i64> undef, i64 %c, i32 0 670 %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer 671 %c2 = icmp eq <2 x i64> %b, %sp 672 %o = and <2 x i1> %c1, %c2 673 %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b 674 ret <2 x i64> %s 675} 676