1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s 3 4define arm_aapcs_vfpcc <8 x half> @test_vrndaq_m_f16(<8 x half> %inactive, <8 x half> %a, i16 zeroext %p) { 5; CHECK-LABEL: test_vrndaq_m_f16: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vmsr p0, r0 8; CHECK-NEXT: vpst 9; CHECK-NEXT: vrintat.f16 q0, q1 10; CHECK-NEXT: bx lr 11entry: 12 %0 = zext i16 %p to i32 13 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 14 %2 = tail call <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half> %a, <8 x i1> %1, <8 x half> %inactive) 15 ret <8 x half> %2 16} 17 18define arm_aapcs_vfpcc <4 x float> @test_vrndaq_m_f32(<4 x float> %inactive, <4 x float> %a, i16 zeroext %p) { 19; CHECK-LABEL: test_vrndaq_m_f32: 20; CHECK: @ %bb.0: @ %entry 21; CHECK-NEXT: vmsr p0, r0 22; CHECK-NEXT: vpst 23; CHECK-NEXT: vrintat.f32 q0, q1 24; CHECK-NEXT: bx lr 25entry: 26 %0 = zext i16 %p to i32 27 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 28 %2 = tail call <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1, <4 x float> %inactive) 29 ret <4 x float> %2 30} 31 32define arm_aapcs_vfpcc <8 x half> @test_vrndmq_m_f16(<8 x half> %inactive, <8 x half> %a, i16 zeroext %p) { 33; CHECK-LABEL: test_vrndmq_m_f16: 34; CHECK: @ %bb.0: @ %entry 35; CHECK-NEXT: vmsr p0, r0 36; CHECK-NEXT: vpst 37; CHECK-NEXT: vrintmt.f16 q0, q1 38; CHECK-NEXT: bx lr 39entry: 40 %0 = zext i16 %p to i32 41 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 42 %2 = tail call <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half> %a, <8 x i1> %1, <8 x half> %inactive) 43 ret <8 x half> %2 44} 45 46define arm_aapcs_vfpcc <4 x float> @test_vrndmq_m_f32(<4 x float> %inactive, <4 x float> %a, i16 zeroext %p) { 47; CHECK-LABEL: test_vrndmq_m_f32: 48; CHECK: @ %bb.0: @ %entry 49; CHECK-NEXT: vmsr p0, r0 50; CHECK-NEXT: vpst 51; CHECK-NEXT: vrintmt.f32 q0, q1 52; CHECK-NEXT: bx lr 53entry: 54 %0 = zext i16 %p to i32 55 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 56 %2 = tail call <4 x float> @llvm.arm.mve.vrintm.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1, <4 x float> %inactive) 57 ret <4 x float> %2 58} 59 60define arm_aapcs_vfpcc <8 x half> @test_vrndnq_m_f16(<8 x half> %inactive, <8 x half> %a, i16 zeroext %p) { 61; CHECK-LABEL: test_vrndnq_m_f16: 62; CHECK: @ %bb.0: @ %entry 63; CHECK-NEXT: vmsr p0, r0 64; CHECK-NEXT: vpst 65; CHECK-NEXT: vrintnt.f16 q0, q1 66; CHECK-NEXT: bx lr 67entry: 68 %0 = zext i16 %p to i32 69 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 70 %2 = tail call <8 x half> @llvm.arm.mve.vrintn.predicated.v8f16.v8i1(<8 x half> %a, <8 x i1> %1, <8 x half> %inactive) 71 ret <8 x half> %2 72} 73 74define arm_aapcs_vfpcc <4 x float> @test_vrndnq_m_f32(<4 x float> %inactive, <4 x float> %a, i16 zeroext %p) { 75; CHECK-LABEL: test_vrndnq_m_f32: 76; CHECK: @ %bb.0: @ %entry 77; CHECK-NEXT: vmsr p0, r0 78; CHECK-NEXT: vpst 79; CHECK-NEXT: vrintnt.f32 q0, q1 80; CHECK-NEXT: bx lr 81entry: 82 %0 = zext i16 %p to i32 83 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 84 %2 = tail call <4 x float> @llvm.arm.mve.vrintn.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1, <4 x float> %inactive) 85 ret <4 x float> %2 86} 87 88define arm_aapcs_vfpcc <8 x half> @test_vrndpq_m_f16(<8 x half> %inactive, <8 x half> %a, i16 zeroext %p) { 89; CHECK-LABEL: test_vrndpq_m_f16: 90; CHECK: @ %bb.0: @ %entry 91; CHECK-NEXT: vmsr p0, r0 92; CHECK-NEXT: vpst 93; CHECK-NEXT: vrintpt.f16 q0, q1 94; CHECK-NEXT: bx lr 95entry: 96 %0 = zext i16 %p to i32 97 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 98 %2 = tail call <8 x half> @llvm.arm.mve.vrintp.predicated.v8f16.v8i1(<8 x half> %a, <8 x i1> %1, <8 x half> %inactive) 99 ret <8 x half> %2 100} 101 102define arm_aapcs_vfpcc <4 x float> @test_vrndpq_m_f32(<4 x float> %inactive, <4 x float> %a, i16 zeroext %p) { 103; CHECK-LABEL: test_vrndpq_m_f32: 104; CHECK: @ %bb.0: @ %entry 105; CHECK-NEXT: vmsr p0, r0 106; CHECK-NEXT: vpst 107; CHECK-NEXT: vrintpt.f32 q0, q1 108; CHECK-NEXT: bx lr 109entry: 110 %0 = zext i16 %p to i32 111 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 112 %2 = tail call <4 x float> @llvm.arm.mve.vrintp.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1, <4 x float> %inactive) 113 ret <4 x float> %2 114} 115 116define arm_aapcs_vfpcc <8 x half> @test_vrndq_m_f16(<8 x half> %inactive, <8 x half> %a, i16 zeroext %p) { 117; CHECK-LABEL: test_vrndq_m_f16: 118; CHECK: @ %bb.0: @ %entry 119; CHECK-NEXT: vmsr p0, r0 120; CHECK-NEXT: vpst 121; CHECK-NEXT: vrintzt.f16 q0, q1 122; CHECK-NEXT: bx lr 123entry: 124 %0 = zext i16 %p to i32 125 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 126 %2 = tail call <8 x half> @llvm.arm.mve.vrintz.predicated.v8f16.v8i1(<8 x half> %a, <8 x i1> %1, <8 x half> %inactive) 127 ret <8 x half> %2 128} 129 130define arm_aapcs_vfpcc <4 x float> @test_vrndq_m_f32(<4 x float> %inactive, <4 x float> %a, i16 zeroext %p) { 131; CHECK-LABEL: test_vrndq_m_f32: 132; CHECK: @ %bb.0: @ %entry 133; CHECK-NEXT: vmsr p0, r0 134; CHECK-NEXT: vpst 135; CHECK-NEXT: vrintzt.f32 q0, q1 136; CHECK-NEXT: bx lr 137entry: 138 %0 = zext i16 %p to i32 139 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 140 %2 = tail call <4 x float> @llvm.arm.mve.vrintz.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1, <4 x float> %inactive) 141 ret <4 x float> %2 142} 143 144define arm_aapcs_vfpcc <8 x half> @test_vrndxq_m_f16(<8 x half> %inactive, <8 x half> %a, i16 zeroext %p) { 145; CHECK-LABEL: test_vrndxq_m_f16: 146; CHECK: @ %bb.0: @ %entry 147; CHECK-NEXT: vmsr p0, r0 148; CHECK-NEXT: vpst 149; CHECK-NEXT: vrintxt.f16 q0, q1 150; CHECK-NEXT: bx lr 151entry: 152 %0 = zext i16 %p to i32 153 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 154 %2 = tail call <8 x half> @llvm.arm.mve.vrintx.predicated.v8f16.v8i1(<8 x half> %a, <8 x i1> %1, <8 x half> %inactive) 155 ret <8 x half> %2 156} 157 158define arm_aapcs_vfpcc <4 x float> @test_vrndxq_m_f32(<4 x float> %inactive, <4 x float> %a, i16 zeroext %p) { 159; CHECK-LABEL: test_vrndxq_m_f32: 160; CHECK: @ %bb.0: @ %entry 161; CHECK-NEXT: vmsr p0, r0 162; CHECK-NEXT: vpst 163; CHECK-NEXT: vrintxt.f32 q0, q1 164; CHECK-NEXT: bx lr 165entry: 166 %0 = zext i16 %p to i32 167 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 168 %2 = tail call <4 x float> @llvm.arm.mve.vrintx.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1, <4 x float> %inactive) 169 ret <4 x float> %2 170} 171 172declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) 173declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) 174declare <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) 175declare <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>) 176declare <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) 177declare <4 x float> @llvm.arm.mve.vrintm.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>) 178declare <8 x half> @llvm.arm.mve.vrintn.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) 179declare <4 x float> @llvm.arm.mve.vrintn.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>) 180declare <8 x half> @llvm.arm.mve.vrintp.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) 181declare <4 x float> @llvm.arm.mve.vrintp.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>) 182declare <8 x half> @llvm.arm.mve.vrintz.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) 183declare <4 x float> @llvm.arm.mve.vrintz.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>) 184declare <8 x half> @llvm.arm.mve.vrintx.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) 185declare <4 x float> @llvm.arm.mve.vrintx.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>) 186