xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulltq.ll (revision ab0c5cea0b1a9a1227fea840184dd7b5983c22a5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
3
4define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
5; CHECK-LABEL: test_vmulltq_int_u8:
6; CHECK:       @ %bb.0: @ %entry
7; CHECK-NEXT:    vmullt.u8 q0, q0, q1
8; CHECK-NEXT:    bx lr
9entry:
10  %0 = tail call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1, i32 1)
11  ret <8 x i16> %0
12}
13
14declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1
15
16define arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {
17; CHECK-LABEL: test_vmulltq_int_s16:
18; CHECK:       @ %bb.0: @ %entry
19; CHECK-NEXT:    vmullt.s16 q0, q0, q1
20; CHECK-NEXT:    bx lr
21entry:
22  %0 = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0, i32 1)
23  ret <4 x i32> %0
24}
25
26declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1
27
28define arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {
29; CHECK-LABEL: test_vmulltq_int_u32:
30; CHECK:       @ %bb.0: @ %entry
31; CHECK-NEXT:    vmullt.u32 q2, q0, q1
32; CHECK-NEXT:    vmov q0, q2
33; CHECK-NEXT:    bx lr
34entry:
35  %0 = tail call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1, i32 1)
36  ret <2 x i64> %0
37}
38
39declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1
40
41define arm_aapcs_vfpcc <4 x i32> @test_vmulltq_poly_p16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {
42; CHECK-LABEL: test_vmulltq_poly_p16:
43; CHECK:       @ %bb.0: @ %entry
44; CHECK-NEXT:    vmullt.p16 q0, q0, q1
45; CHECK-NEXT:    bx lr
46entry:
47  %0 = tail call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 1)
48  ret <4 x i32> %0
49}
50
51declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
52
53define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_m_s8(<8 x i16> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
54; CHECK-LABEL: test_vmulltq_int_m_s8:
55; CHECK:       @ %bb.0: @ %entry
56; CHECK-NEXT:    vmsr p0, r0
57; CHECK-NEXT:    vpst
58; CHECK-NEXT:    vmulltt.s8 q0, q1, q2
59; CHECK-NEXT:    bx lr
60entry:
61  %0 = zext i16 %p to i32
62  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
63  %2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, <8 x i1> %1, <8 x i16> %inactive)
64  ret <8 x i16> %2
65}
66
67declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
68
69declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
70
71define arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_m_u16(<4 x i32> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
72; CHECK-LABEL: test_vmulltq_int_m_u16:
73; CHECK:       @ %bb.0: @ %entry
74; CHECK-NEXT:    vmsr p0, r0
75; CHECK-NEXT:    vpst
76; CHECK-NEXT:    vmulltt.u16 q0, q1, q2
77; CHECK-NEXT:    bx lr
78entry:
79  %0 = zext i16 %p to i32
80  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
81  %2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 1, i32 1, <4 x i1> %1, <4 x i32> %inactive)
82  ret <4 x i32> %2
83}
84
85declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
86
87declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
88
89define arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_m_s32(<2 x i64> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
90; CHECK-LABEL: test_vmulltq_int_m_s32:
91; CHECK:       @ %bb.0: @ %entry
92; CHECK-NEXT:    vmsr p0, r0
93; CHECK-NEXT:    vpst
94; CHECK-NEXT:    vmulltt.s32 q0, q1, q2
95; CHECK-NEXT:    bx lr
96entry:
97  %0 = zext i16 %p to i32
98  %1 = tail call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)
99  %2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 1, <2 x i1> %1, <2 x i64> %inactive)
100  ret <2 x i64> %2
101}
102
103declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32)
104declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1
105
106define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_m_p8(<8 x i16> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
107; CHECK-LABEL: test_vmulltq_poly_m_p8:
108; CHECK:       @ %bb.0: @ %entry
109; CHECK-NEXT:    vmsr p0, r0
110; CHECK-NEXT:    vpst
111; CHECK-NEXT:    vmulltt.p8 q0, q1, q2
112; CHECK-NEXT:    bx lr
113entry:
114  %0 = zext i16 %p to i32
115  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
116  %2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 1, <8 x i1> %1, <8 x i16> %inactive)
117  ret <8 x i16> %2
118}
119
120declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1
121
122define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
123; CHECK-LABEL: test_vmulltq_int_x_u8:
124; CHECK:       @ %bb.0: @ %entry
125; CHECK-NEXT:    vmsr p0, r0
126; CHECK-NEXT:    vpst
127; CHECK-NEXT:    vmulltt.u8 q0, q0, q1
128; CHECK-NEXT:    bx lr
129entry:
130  %0 = zext i16 %p to i32
131  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
132  %2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 1, i32 1, <8 x i1> %1, <8 x i16> undef)
133  ret <8 x i16> %2
134}
135
136define arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
137; CHECK-LABEL: test_vmulltq_int_x_s16:
138; CHECK:       @ %bb.0: @ %entry
139; CHECK-NEXT:    vmsr p0, r0
140; CHECK-NEXT:    vpst
141; CHECK-NEXT:    vmulltt.s16 q0, q0, q1
142; CHECK-NEXT:    bx lr
143entry:
144  %0 = zext i16 %p to i32
145  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
146  %2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 1, <4 x i1> %1, <4 x i32> undef)
147  ret <4 x i32> %2
148}
149
150define arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
151; CHECK-LABEL: test_vmulltq_int_x_u32:
152; CHECK:       @ %bb.0: @ %entry
153; CHECK-NEXT:    vmsr p0, r0
154; CHECK-NEXT:    vpst
155; CHECK-NEXT:    vmulltt.u32 q2, q0, q1
156; CHECK-NEXT:    vmov q0, q2
157; CHECK-NEXT:    bx lr
158entry:
159  %0 = zext i16 %p to i32
160  %1 = tail call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %0)
161  %2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %a, <4 x i32> %b, i32 1, i32 1, <2 x i1> %1, <2 x i64> undef)
162  ret <2 x i64> %2
163}
164
165define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_x_p8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
166; CHECK-LABEL: test_vmulltq_poly_x_p8:
167; CHECK:       @ %bb.0: @ %entry
168; CHECK-NEXT:    vmsr p0, r0
169; CHECK-NEXT:    vpst
170; CHECK-NEXT:    vmulltt.p8 q0, q0, q1
171; CHECK-NEXT:    bx lr
172entry:
173  %0 = zext i16 %p to i32
174  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
175  %2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 1, <8 x i1> %1, <8 x i16> undef)
176  ret <8 x i16> %2
177}
178
179