1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVE 3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVEFP 4 5; 6; Float to signed 32-bit -- Vector size variation 7; 8 9declare <1 x i32> @llvm.fptoui.sat.v1f32.v1i32 (<1 x float>) 10declare <2 x i32> @llvm.fptoui.sat.v2f32.v2i32 (<2 x float>) 11declare <3 x i32> @llvm.fptoui.sat.v3f32.v3i32 (<3 x float>) 12declare <4 x i32> @llvm.fptoui.sat.v4f32.v4i32 (<4 x float>) 13declare <5 x i32> @llvm.fptoui.sat.v5f32.v5i32 (<5 x float>) 14declare <6 x i32> @llvm.fptoui.sat.v6f32.v6i32 (<6 x float>) 15declare <7 x i32> @llvm.fptoui.sat.v7f32.v7i32 (<7 x float>) 16declare <8 x i32> @llvm.fptoui.sat.v8f32.v8i32 (<8 x float>) 17 18define arm_aapcs_vfpcc <1 x i32> @test_unsigned_v1f32_v1i32(<1 x float> %f) { 19; CHECK-LABEL: test_unsigned_v1f32_v1i32: 20; CHECK: @ %bb.0: 21; CHECK-NEXT: vcvt.u32.f32 s0, s0 22; CHECK-NEXT: vmov r0, s0 23; CHECK-NEXT: bx lr 24 %x = call <1 x i32> @llvm.fptoui.sat.v1f32.v1i32(<1 x float> %f) 25 ret <1 x i32> %x 26} 27 28define arm_aapcs_vfpcc <2 x i32> @test_unsigned_v2f32_v2i32(<2 x float> %f) { 29; CHECK-LABEL: test_unsigned_v2f32_v2i32: 30; CHECK: @ %bb.0: 31; CHECK-NEXT: .save {r4, r5, r7, lr} 32; CHECK-NEXT: push {r4, r5, r7, lr} 33; CHECK-NEXT: .vsave {d8, d9} 34; CHECK-NEXT: vpush {d8, d9} 35; CHECK-NEXT: vmov q4, q0 36; CHECK-NEXT: vmov r0, s17 37; CHECK-NEXT: bl __aeabi_f2ulz 38; CHECK-NEXT: mov r5, r0 39; CHECK-NEXT: vmov r0, s16 40; CHECK-NEXT: vldr s18, .LCPI1_0 41; CHECK-NEXT: vcmp.f32 s17, #0 42; CHECK-NEXT: mov r4, r1 43; CHECK-NEXT: vmrs APSR_nzcv, fpscr 44; CHECK-NEXT: itt lt 45; CHECK-NEXT: movlt r5, #0 46; CHECK-NEXT: movlt r4, #0 47; CHECK-NEXT: vcmp.f32 s17, s18 48; CHECK-NEXT: vmrs APSR_nzcv, fpscr 49; CHECK-NEXT: itt gt 50; CHECK-NEXT: movgt r4, #0 51; CHECK-NEXT: movgt.w r5, #-1 52; CHECK-NEXT: bl __aeabi_f2ulz 53; CHECK-NEXT: vcmp.f32 s16, #0 54; CHECK-NEXT: vmrs APSR_nzcv, fpscr 55; CHECK-NEXT: itt lt 56; CHECK-NEXT: movlt r1, #0 57; CHECK-NEXT: movlt r0, #0 58; CHECK-NEXT: vcmp.f32 s16, s18 59; CHECK-NEXT: vmrs APSR_nzcv, fpscr 60; CHECK-NEXT: itt gt 61; CHECK-NEXT: movgt.w r0, #-1 62; CHECK-NEXT: movgt r1, #0 63; CHECK-NEXT: vmov q0[2], q0[0], r0, r5 64; CHECK-NEXT: vmov q0[3], q0[1], r1, r4 65; CHECK-NEXT: vpop {d8, d9} 66; CHECK-NEXT: pop {r4, r5, r7, pc} 67; CHECK-NEXT: .p2align 2 68; CHECK-NEXT: @ %bb.1: 69; CHECK-NEXT: .LCPI1_0: 70; CHECK-NEXT: .long 0x4f7fffff @ float 4.29496704E+9 71 %x = call <2 x i32> @llvm.fptoui.sat.v2f32.v2i32(<2 x float> %f) 72 ret <2 x i32> %x 73} 74 75define arm_aapcs_vfpcc <3 x i32> @test_unsigned_v3f32_v3i32(<3 x float> %f) { 76; CHECK-MVE-LABEL: test_unsigned_v3f32_v3i32: 77; CHECK-MVE: @ %bb.0: 78; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2 79; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0 80; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s3 81; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s1 82; CHECK-MVE-NEXT: vmov r0, s2 83; CHECK-MVE-NEXT: vmov r1, s0 84; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0 85; CHECK-MVE-NEXT: vmov r0, s4 86; CHECK-MVE-NEXT: vmov r1, s6 87; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0 88; CHECK-MVE-NEXT: bx lr 89; 90; CHECK-MVEFP-LABEL: test_unsigned_v3f32_v3i32: 91; CHECK-MVEFP: @ %bb.0: 92; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0 93; CHECK-MVEFP-NEXT: bx lr 94 %x = call <3 x i32> @llvm.fptoui.sat.v3f32.v3i32(<3 x float> %f) 95 ret <3 x i32> %x 96} 97 98define arm_aapcs_vfpcc <4 x i32> @test_unsigned_v4f32_v4i32(<4 x float> %f) { 99; CHECK-MVE-LABEL: test_unsigned_v4f32_v4i32: 100; CHECK-MVE: @ %bb.0: 101; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2 102; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0 103; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s3 104; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s1 105; CHECK-MVE-NEXT: vmov r0, s2 106; CHECK-MVE-NEXT: vmov r1, s0 107; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0 108; CHECK-MVE-NEXT: vmov r0, s4 109; CHECK-MVE-NEXT: vmov r1, s6 110; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0 111; CHECK-MVE-NEXT: bx lr 112; 113; CHECK-MVEFP-LABEL: test_unsigned_v4f32_v4i32: 114; CHECK-MVEFP: @ %bb.0: 115; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0 116; CHECK-MVEFP-NEXT: bx lr 117 %x = call <4 x i32> @llvm.fptoui.sat.v4f32.v4i32(<4 x float> %f) 118 ret <4 x i32> %x 119} 120 121define arm_aapcs_vfpcc <5 x i32> @test_unsigned_v5f32_v5i32(<5 x float> %f) { 122; CHECK-MVE-LABEL: test_unsigned_v5f32_v5i32: 123; CHECK-MVE: @ %bb.0: 124; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2 125; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0 126; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s3 127; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s1 128; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4 129; CHECK-MVE-NEXT: vmov r1, s2 130; CHECK-MVE-NEXT: vmov r2, s0 131; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1 132; CHECK-MVE-NEXT: vmov r1, s6 133; CHECK-MVE-NEXT: vmov r2, s8 134; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1 135; CHECK-MVE-NEXT: vstrw.32 q0, [r0] 136; CHECK-MVE-NEXT: vstr s4, [r0, #16] 137; CHECK-MVE-NEXT: bx lr 138; 139; CHECK-MVEFP-LABEL: test_unsigned_v5f32_v5i32: 140; CHECK-MVEFP: @ %bb.0: 141; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1 142; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0 143; CHECK-MVEFP-NEXT: vmov r1, s4 144; CHECK-MVEFP-NEXT: str r1, [r0, #16] 145; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0] 146; CHECK-MVEFP-NEXT: bx lr 147 %x = call <5 x i32> @llvm.fptoui.sat.v5f32.v5i32(<5 x float> %f) 148 ret <5 x i32> %x 149} 150 151define arm_aapcs_vfpcc <6 x i32> @test_unsigned_v6f32_v6i32(<6 x float> %f) { 152; CHECK-MVE-LABEL: test_unsigned_v6f32_v6i32: 153; CHECK-MVE: @ %bb.0: 154; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2 155; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0 156; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s3 157; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s1 158; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s5 159; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4 160; CHECK-MVE-NEXT: vmov r1, s2 161; CHECK-MVE-NEXT: vmov r2, s0 162; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1 163; CHECK-MVE-NEXT: vmov r1, s8 164; CHECK-MVE-NEXT: vmov r2, s10 165; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1 166; CHECK-MVE-NEXT: vstr s6, [r0, #20] 167; CHECK-MVE-NEXT: vstrw.32 q0, [r0] 168; CHECK-MVE-NEXT: vstr s4, [r0, #16] 169; CHECK-MVE-NEXT: bx lr 170; 171; CHECK-MVEFP-LABEL: test_unsigned_v6f32_v6i32: 172; CHECK-MVEFP: @ %bb.0: 173; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1 174; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0 175; CHECK-MVEFP-NEXT: vmov.f32 s6, s5 176; CHECK-MVEFP-NEXT: vmov r2, s4 177; CHECK-MVEFP-NEXT: vmov r1, s6 178; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16] 179; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0] 180; CHECK-MVEFP-NEXT: bx lr 181 %x = call <6 x i32> @llvm.fptoui.sat.v6f32.v6i32(<6 x float> %f) 182 ret <6 x i32> %x 183} 184 185define arm_aapcs_vfpcc <7 x i32> @test_unsigned_v7f32_v7i32(<7 x float> %f) { 186; CHECK-MVE-LABEL: test_unsigned_v7f32_v7i32: 187; CHECK-MVE: @ %bb.0: 188; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2 189; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0 190; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s3 191; CHECK-MVE-NEXT: vcvt.u32.f32 s12, s1 192; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s5 193; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4 194; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s6 195; CHECK-MVE-NEXT: vmov r1, s2 196; CHECK-MVE-NEXT: vmov r2, s0 197; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1 198; CHECK-MVE-NEXT: vmov r1, s10 199; CHECK-MVE-NEXT: vmov r2, s12 200; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1 201; CHECK-MVE-NEXT: vstr s8, [r0, #20] 202; CHECK-MVE-NEXT: vstr s4, [r0, #16] 203; CHECK-MVE-NEXT: vstrw.32 q0, [r0] 204; CHECK-MVE-NEXT: vstr s6, [r0, #24] 205; CHECK-MVE-NEXT: bx lr 206; 207; CHECK-MVEFP-LABEL: test_unsigned_v7f32_v7i32: 208; CHECK-MVEFP: @ %bb.0: 209; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1 210; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0 211; CHECK-MVEFP-NEXT: vmov.f32 s10, s5 212; CHECK-MVEFP-NEXT: vmov r2, s4 213; CHECK-MVEFP-NEXT: vmov r3, s6 214; CHECK-MVEFP-NEXT: vmov r1, s10 215; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16] 216; CHECK-MVEFP-NEXT: str r3, [r0, #24] 217; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0] 218; CHECK-MVEFP-NEXT: bx lr 219 %x = call <7 x i32> @llvm.fptoui.sat.v7f32.v7i32(<7 x float> %f) 220 ret <7 x i32> %x 221} 222 223define arm_aapcs_vfpcc <8 x i32> @test_unsigned_v8f32_v8i32(<8 x float> %f) { 224; CHECK-MVE-LABEL: test_unsigned_v8f32_v8i32: 225; CHECK-MVE: @ %bb.0: 226; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2 227; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0 228; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s3 229; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s1 230; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s6 231; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4 232; CHECK-MVE-NEXT: vcvt.u32.f32 s12, s7 233; CHECK-MVE-NEXT: vcvt.u32.f32 s14, s5 234; CHECK-MVE-NEXT: vmov r0, s2 235; CHECK-MVE-NEXT: vmov r1, s0 236; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0 237; CHECK-MVE-NEXT: vmov r0, s8 238; CHECK-MVE-NEXT: vmov r1, s10 239; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0 240; CHECK-MVE-NEXT: vmov r0, s6 241; CHECK-MVE-NEXT: vmov r1, s4 242; CHECK-MVE-NEXT: vmov q1[2], q1[0], r1, r0 243; CHECK-MVE-NEXT: vmov r0, s12 244; CHECK-MVE-NEXT: vmov r1, s14 245; CHECK-MVE-NEXT: vmov q1[3], q1[1], r1, r0 246; CHECK-MVE-NEXT: bx lr 247; 248; CHECK-MVEFP-LABEL: test_unsigned_v8f32_v8i32: 249; CHECK-MVEFP: @ %bb.0: 250; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0 251; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1 252; CHECK-MVEFP-NEXT: bx lr 253 %x = call <8 x i32> @llvm.fptoui.sat.v8f32.v8i32(<8 x float> %f) 254 ret <8 x i32> %x 255} 256 257; 258; Double to signed 32-bit -- Vector size variation 259; 260 261declare <1 x i32> @llvm.fptoui.sat.v1f64.v1i32 (<1 x double>) 262declare <2 x i32> @llvm.fptoui.sat.v2f64.v2i32 (<2 x double>) 263declare <3 x i32> @llvm.fptoui.sat.v3f64.v3i32 (<3 x double>) 264declare <4 x i32> @llvm.fptoui.sat.v4f64.v4i32 (<4 x double>) 265declare <5 x i32> @llvm.fptoui.sat.v5f64.v5i32 (<5 x double>) 266declare <6 x i32> @llvm.fptoui.sat.v6f64.v6i32 (<6 x double>) 267 268define arm_aapcs_vfpcc <1 x i32> @test_unsigned_v1f64_v1i32(<1 x double> %f) { 269; CHECK-LABEL: test_unsigned_v1f64_v1i32: 270; CHECK: @ %bb.0: 271; CHECK-NEXT: .save {r4, r5, r6, lr} 272; CHECK-NEXT: push {r4, r5, r6, lr} 273; CHECK-NEXT: vldr d1, .LCPI8_0 274; CHECK-NEXT: vmov r4, r5, d0 275; CHECK-NEXT: vmov r2, r3, d1 276; CHECK-NEXT: mov r0, r4 277; CHECK-NEXT: mov r1, r5 278; CHECK-NEXT: bl __aeabi_dcmpge 279; CHECK-NEXT: mov r6, r0 280; CHECK-NEXT: mov r0, r4 281; CHECK-NEXT: mov r1, r5 282; CHECK-NEXT: bl __aeabi_d2uiz 283; CHECK-NEXT: vldr d0, .LCPI8_1 284; CHECK-NEXT: cmp r6, #0 285; CHECK-NEXT: csel r6, r0, r6, ne 286; CHECK-NEXT: mov r0, r4 287; CHECK-NEXT: vmov r2, r3, d0 288; CHECK-NEXT: mov r1, r5 289; CHECK-NEXT: bl __aeabi_dcmpgt 290; CHECK-NEXT: cmp r0, #0 291; CHECK-NEXT: it ne 292; CHECK-NEXT: movne.w r6, #-1 293; CHECK-NEXT: mov r0, r6 294; CHECK-NEXT: pop {r4, r5, r6, pc} 295; CHECK-NEXT: .p2align 3 296; CHECK-NEXT: @ %bb.1: 297; CHECK-NEXT: .LCPI8_0: 298; CHECK-NEXT: .long 0 @ double 0 299; CHECK-NEXT: .long 0 300; CHECK-NEXT: .LCPI8_1: 301; CHECK-NEXT: .long 4292870144 @ double 4294967295 302; CHECK-NEXT: .long 1106247679 303 %x = call <1 x i32> @llvm.fptoui.sat.v1f64.v1i32(<1 x double> %f) 304 ret <1 x i32> %x 305} 306 307define arm_aapcs_vfpcc <2 x i32> @test_unsigned_v2f64_v2i32(<2 x double> %f) { 308; CHECK-LABEL: test_unsigned_v2f64_v2i32: 309; CHECK: @ %bb.0: 310; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 311; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 312; CHECK-NEXT: .pad #4 313; CHECK-NEXT: sub sp, #4 314; CHECK-NEXT: .vsave {d8, d9} 315; CHECK-NEXT: vpush {d8, d9} 316; CHECK-NEXT: .pad #8 317; CHECK-NEXT: sub sp, #8 318; CHECK-NEXT: vmov q4, q0 319; CHECK-NEXT: vldr d0, .LCPI9_0 320; CHECK-NEXT: vmov r6, r7, d9 321; CHECK-NEXT: vmov r11, r3, d0 322; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill 323; CHECK-NEXT: mov r0, r6 324; CHECK-NEXT: mov r1, r7 325; CHECK-NEXT: mov r2, r11 326; CHECK-NEXT: bl __aeabi_dcmpge 327; CHECK-NEXT: mov r8, r0 328; CHECK-NEXT: mov r0, r6 329; CHECK-NEXT: mov r1, r7 330; CHECK-NEXT: bl __aeabi_d2ulz 331; CHECK-NEXT: vldr d0, .LCPI9_1 332; CHECK-NEXT: cmp.w r8, #0 333; CHECK-NEXT: csel r9, r0, r8, ne 334; CHECK-NEXT: csel r8, r1, r8, ne 335; CHECK-NEXT: vmov r10, r3, d0 336; CHECK-NEXT: mov r0, r6 337; CHECK-NEXT: mov r1, r7 338; CHECK-NEXT: vmov r5, r4, d8 339; CHECK-NEXT: str r3, [sp] @ 4-byte Spill 340; CHECK-NEXT: mov r2, r10 341; CHECK-NEXT: bl __aeabi_dcmpgt 342; CHECK-NEXT: cmp r0, #0 343; CHECK-NEXT: itt ne 344; CHECK-NEXT: movne.w r8, #0 345; CHECK-NEXT: movne.w r9, #-1 346; CHECK-NEXT: ldr r3, [sp, #4] @ 4-byte Reload 347; CHECK-NEXT: mov r0, r5 348; CHECK-NEXT: mov r1, r4 349; CHECK-NEXT: mov r2, r11 350; CHECK-NEXT: bl __aeabi_dcmpge 351; CHECK-NEXT: mov r6, r0 352; CHECK-NEXT: mov r0, r5 353; CHECK-NEXT: mov r1, r4 354; CHECK-NEXT: bl __aeabi_d2ulz 355; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload 356; CHECK-NEXT: cmp r6, #0 357; CHECK-NEXT: csel r7, r1, r6, ne 358; CHECK-NEXT: csel r6, r0, r6, ne 359; CHECK-NEXT: mov r0, r5 360; CHECK-NEXT: mov r1, r4 361; CHECK-NEXT: mov r2, r10 362; CHECK-NEXT: bl __aeabi_dcmpgt 363; CHECK-NEXT: cmp r0, #0 364; CHECK-NEXT: itt ne 365; CHECK-NEXT: movne.w r6, #-1 366; CHECK-NEXT: movne r7, #0 367; CHECK-NEXT: vmov q0[2], q0[0], r6, r9 368; CHECK-NEXT: vmov q0[3], q0[1], r7, r8 369; CHECK-NEXT: add sp, #8 370; CHECK-NEXT: vpop {d8, d9} 371; CHECK-NEXT: add sp, #4 372; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 373; CHECK-NEXT: .p2align 3 374; CHECK-NEXT: @ %bb.1: 375; CHECK-NEXT: .LCPI9_0: 376; CHECK-NEXT: .long 0 @ double 0 377; CHECK-NEXT: .long 0 378; CHECK-NEXT: .LCPI9_1: 379; CHECK-NEXT: .long 4292870144 @ double 4294967295 380; CHECK-NEXT: .long 1106247679 381 %x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f) 382 ret <2 x i32> %x 383} 384 385define arm_aapcs_vfpcc <3 x i32> @test_unsigned_v3f64_v3i32(<3 x double> %f) { 386; CHECK-LABEL: test_unsigned_v3f64_v3i32: 387; CHECK: @ %bb.0: 388; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 389; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 390; CHECK-NEXT: .pad #4 391; CHECK-NEXT: sub sp, #4 392; CHECK-NEXT: .vsave {d8, d9} 393; CHECK-NEXT: vpush {d8, d9} 394; CHECK-NEXT: .pad #16 395; CHECK-NEXT: sub sp, #16 396; CHECK-NEXT: vmov.f32 s18, s0 397; CHECK-NEXT: vmov.f32 s19, s1 398; CHECK-NEXT: vldr d0, .LCPI10_0 399; CHECK-NEXT: vmov r8, r9, d1 400; CHECK-NEXT: vmov r5, r4, d0 401; CHECK-NEXT: vmov.f32 s16, s4 402; CHECK-NEXT: vmov.f32 s17, s5 403; CHECK-NEXT: str r5, [sp, #4] @ 4-byte Spill 404; CHECK-NEXT: mov r0, r8 405; CHECK-NEXT: mov r1, r9 406; CHECK-NEXT: mov r2, r5 407; CHECK-NEXT: mov r3, r4 408; CHECK-NEXT: str r4, [sp, #8] @ 4-byte Spill 409; CHECK-NEXT: bl __aeabi_dcmpge 410; CHECK-NEXT: mov r10, r0 411; CHECK-NEXT: mov r0, r8 412; CHECK-NEXT: mov r1, r9 413; CHECK-NEXT: bl __aeabi_d2ulz 414; CHECK-NEXT: vldr d0, .LCPI10_1 415; CHECK-NEXT: vmov r11, r1, d9 416; CHECK-NEXT: cmp.w r10, #0 417; CHECK-NEXT: vmov r7, r6, d8 418; CHECK-NEXT: vmov r2, r3, d0 419; CHECK-NEXT: csel r10, r0, r10, ne 420; CHECK-NEXT: mov r0, r8 421; CHECK-NEXT: str r1, [sp, #12] @ 4-byte Spill 422; CHECK-NEXT: mov r1, r9 423; CHECK-NEXT: mov r9, r2 424; CHECK-NEXT: mov r8, r3 425; CHECK-NEXT: bl __aeabi_dcmpgt 426; CHECK-NEXT: cmp r0, #0 427; CHECK-NEXT: mov r0, r7 428; CHECK-NEXT: mov r1, r6 429; CHECK-NEXT: mov r2, r5 430; CHECK-NEXT: mov r3, r4 431; CHECK-NEXT: it ne 432; CHECK-NEXT: movne.w r10, #-1 433; CHECK-NEXT: bl __aeabi_dcmpge 434; CHECK-NEXT: mov r4, r0 435; CHECK-NEXT: mov r0, r7 436; CHECK-NEXT: mov r1, r6 437; CHECK-NEXT: bl __aeabi_d2ulz 438; CHECK-NEXT: cmp r4, #0 439; CHECK-NEXT: mov r1, r6 440; CHECK-NEXT: csel r5, r0, r4, ne 441; CHECK-NEXT: mov r0, r7 442; CHECK-NEXT: mov r2, r9 443; CHECK-NEXT: mov r3, r8 444; CHECK-NEXT: bl __aeabi_dcmpgt 445; CHECK-NEXT: cmp r0, #0 446; CHECK-NEXT: it ne 447; CHECK-NEXT: movne.w r5, #-1 448; CHECK-NEXT: ldr r6, [sp, #12] @ 4-byte Reload 449; CHECK-NEXT: mov r0, r11 450; CHECK-NEXT: ldrd r2, r3, [sp, #4] @ 8-byte Folded Reload 451; CHECK-NEXT: mov r1, r6 452; CHECK-NEXT: bl __aeabi_dcmpge 453; CHECK-NEXT: mov r4, r0 454; CHECK-NEXT: mov r0, r11 455; CHECK-NEXT: mov r1, r6 456; CHECK-NEXT: bl __aeabi_d2ulz 457; CHECK-NEXT: cmp r4, #0 458; CHECK-NEXT: mov r1, r6 459; CHECK-NEXT: csel r4, r0, r4, ne 460; CHECK-NEXT: mov r0, r11 461; CHECK-NEXT: mov r2, r9 462; CHECK-NEXT: mov r3, r8 463; CHECK-NEXT: bl __aeabi_dcmpgt 464; CHECK-NEXT: vmov.32 q0[1], r10 465; CHECK-NEXT: cmp r0, #0 466; CHECK-NEXT: it ne 467; CHECK-NEXT: movne.w r4, #-1 468; CHECK-NEXT: vmov q0[2], q0[0], r4, r5 469; CHECK-NEXT: add sp, #16 470; CHECK-NEXT: vpop {d8, d9} 471; CHECK-NEXT: add sp, #4 472; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 473; CHECK-NEXT: .p2align 3 474; CHECK-NEXT: @ %bb.1: 475; CHECK-NEXT: .LCPI10_0: 476; CHECK-NEXT: .long 0 @ double 0 477; CHECK-NEXT: .long 0 478; CHECK-NEXT: .LCPI10_1: 479; CHECK-NEXT: .long 4292870144 @ double 4294967295 480; CHECK-NEXT: .long 1106247679 481 %x = call <3 x i32> @llvm.fptoui.sat.v3f64.v3i32(<3 x double> %f) 482 ret <3 x i32> %x 483} 484 485define arm_aapcs_vfpcc <4 x i32> @test_unsigned_v4f64_v4i32(<4 x double> %f) { 486; CHECK-LABEL: test_unsigned_v4f64_v4i32: 487; CHECK: @ %bb.0: 488; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 489; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 490; CHECK-NEXT: .pad #4 491; CHECK-NEXT: sub sp, #4 492; CHECK-NEXT: .vsave {d8, d9, d10, d11} 493; CHECK-NEXT: vpush {d8, d9, d10, d11} 494; CHECK-NEXT: .pad #24 495; CHECK-NEXT: sub sp, #24 496; CHECK-NEXT: vmov q4, q0 497; CHECK-NEXT: vldr d0, .LCPI11_0 498; CHECK-NEXT: vmov q5, q1 499; CHECK-NEXT: vmov r8, r9, d10 500; CHECK-NEXT: vmov r2, r11, d0 501; CHECK-NEXT: str r2, [sp, #20] @ 4-byte Spill 502; CHECK-NEXT: mov r0, r8 503; CHECK-NEXT: mov r1, r9 504; CHECK-NEXT: mov r3, r11 505; CHECK-NEXT: bl __aeabi_dcmpge 506; CHECK-NEXT: mov r10, r0 507; CHECK-NEXT: mov r0, r8 508; CHECK-NEXT: mov r1, r9 509; CHECK-NEXT: bl __aeabi_d2ulz 510; CHECK-NEXT: vldr d0, .LCPI11_1 511; CHECK-NEXT: vmov r5, r1, d11 512; CHECK-NEXT: cmp.w r10, #0 513; CHECK-NEXT: vmov r6, r7, d8 514; CHECK-NEXT: vmov r2, r3, d0 515; CHECK-NEXT: csel r4, r0, r10, ne 516; CHECK-NEXT: mov r0, r8 517; CHECK-NEXT: strd r5, r1, [sp, #4] @ 8-byte Folded Spill 518; CHECK-NEXT: mov r1, r9 519; CHECK-NEXT: str r2, [sp] @ 4-byte Spill 520; CHECK-NEXT: mov r8, r2 521; CHECK-NEXT: mov r9, r3 522; CHECK-NEXT: bl __aeabi_dcmpgt 523; CHECK-NEXT: cmp r0, #0 524; CHECK-NEXT: it ne 525; CHECK-NEXT: movne.w r4, #-1 526; CHECK-NEXT: mov r5, r7 527; CHECK-NEXT: mov r1, r7 528; CHECK-NEXT: ldr r7, [sp, #20] @ 4-byte Reload 529; CHECK-NEXT: mov r0, r6 530; CHECK-NEXT: mov r3, r11 531; CHECK-NEXT: str r4, [sp, #16] @ 4-byte Spill 532; CHECK-NEXT: mov r10, r11 533; CHECK-NEXT: mov r2, r7 534; CHECK-NEXT: bl __aeabi_dcmpge 535; CHECK-NEXT: mov r4, r0 536; CHECK-NEXT: mov r0, r6 537; CHECK-NEXT: mov r1, r5 538; CHECK-NEXT: bl __aeabi_d2ulz 539; CHECK-NEXT: cmp r4, #0 540; CHECK-NEXT: mov r2, r8 541; CHECK-NEXT: csel r4, r0, r4, ne 542; CHECK-NEXT: mov r0, r6 543; CHECK-NEXT: mov r1, r5 544; CHECK-NEXT: mov r3, r9 545; CHECK-NEXT: mov r8, r9 546; CHECK-NEXT: bl __aeabi_dcmpgt 547; CHECK-NEXT: cmp r0, #0 548; CHECK-NEXT: it ne 549; CHECK-NEXT: movne.w r4, #-1 550; CHECK-NEXT: ldr.w r11, [sp, #4] @ 4-byte Reload 551; CHECK-NEXT: mov r2, r7 552; CHECK-NEXT: ldr.w r9, [sp, #8] @ 4-byte Reload 553; CHECK-NEXT: mov r3, r10 554; CHECK-NEXT: str r4, [sp, #12] @ 4-byte Spill 555; CHECK-NEXT: mov r0, r11 556; CHECK-NEXT: mov r1, r9 557; CHECK-NEXT: bl __aeabi_dcmpge 558; CHECK-NEXT: mov r4, r0 559; CHECK-NEXT: mov r0, r11 560; CHECK-NEXT: mov r1, r9 561; CHECK-NEXT: bl __aeabi_d2ulz 562; CHECK-NEXT: mov r1, r9 563; CHECK-NEXT: ldr.w r9, [sp] @ 4-byte Reload 564; CHECK-NEXT: cmp r4, #0 565; CHECK-NEXT: mov r3, r8 566; CHECK-NEXT: csel r5, r0, r4, ne 567; CHECK-NEXT: mov r0, r11 568; CHECK-NEXT: mov r2, r9 569; CHECK-NEXT: vmov r7, r6, d9 570; CHECK-NEXT: bl __aeabi_dcmpgt 571; CHECK-NEXT: cmp r0, #0 572; CHECK-NEXT: it ne 573; CHECK-NEXT: movne.w r5, #-1 574; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload 575; CHECK-NEXT: mov r0, r7 576; CHECK-NEXT: mov r1, r6 577; CHECK-NEXT: mov r3, r10 578; CHECK-NEXT: bl __aeabi_dcmpge 579; CHECK-NEXT: mov r4, r0 580; CHECK-NEXT: mov r0, r7 581; CHECK-NEXT: mov r1, r6 582; CHECK-NEXT: bl __aeabi_d2ulz 583; CHECK-NEXT: cmp r4, #0 584; CHECK-NEXT: mov r1, r6 585; CHECK-NEXT: csel r4, r0, r4, ne 586; CHECK-NEXT: mov r0, r7 587; CHECK-NEXT: mov r2, r9 588; CHECK-NEXT: mov r3, r8 589; CHECK-NEXT: bl __aeabi_dcmpgt 590; CHECK-NEXT: cmp r0, #0 591; CHECK-NEXT: it ne 592; CHECK-NEXT: movne.w r4, #-1 593; CHECK-NEXT: ldrd r1, r0, [sp, #12] @ 8-byte Folded Reload 594; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 595; CHECK-NEXT: vmov q0[3], q0[1], r4, r5 596; CHECK-NEXT: add sp, #24 597; CHECK-NEXT: vpop {d8, d9, d10, d11} 598; CHECK-NEXT: add sp, #4 599; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 600; CHECK-NEXT: .p2align 3 601; CHECK-NEXT: @ %bb.1: 602; CHECK-NEXT: .LCPI11_0: 603; CHECK-NEXT: .long 0 @ double 0 604; CHECK-NEXT: .long 0 605; CHECK-NEXT: .LCPI11_1: 606; CHECK-NEXT: .long 4292870144 @ double 4294967295 607; CHECK-NEXT: .long 1106247679 608 %x = call <4 x i32> @llvm.fptoui.sat.v4f64.v4i32(<4 x double> %f) 609 ret <4 x i32> %x 610} 611 612define arm_aapcs_vfpcc <5 x i32> @test_unsigned_v5f64_v5i32(<5 x double> %f) { 613; CHECK-LABEL: test_unsigned_v5f64_v5i32: 614; CHECK: @ %bb.0: 615; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 616; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 617; CHECK-NEXT: .pad #4 618; CHECK-NEXT: sub sp, #4 619; CHECK-NEXT: .vsave {d8, d9, d10, d11} 620; CHECK-NEXT: vpush {d8, d9, d10, d11} 621; CHECK-NEXT: .pad #32 622; CHECK-NEXT: sub sp, #32 623; CHECK-NEXT: vmov.f32 s16, s0 624; CHECK-NEXT: mov r7, r0 625; CHECK-NEXT: vmov.f32 s17, s1 626; CHECK-NEXT: vldr d0, .LCPI12_0 627; CHECK-NEXT: vmov r6, r11, d4 628; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill 629; CHECK-NEXT: vmov r2, r3, d0 630; CHECK-NEXT: vmov.f32 s18, s6 631; CHECK-NEXT: vmov.f32 s20, s4 632; CHECK-NEXT: vmov.f32 s22, s2 633; CHECK-NEXT: vmov.f32 s19, s7 634; CHECK-NEXT: vmov.f32 s21, s5 635; CHECK-NEXT: vmov.f32 s23, s3 636; CHECK-NEXT: str r2, [sp, #28] @ 4-byte Spill 637; CHECK-NEXT: mov r0, r6 638; CHECK-NEXT: mov r1, r11 639; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill 640; CHECK-NEXT: bl __aeabi_dcmpge 641; CHECK-NEXT: mov r4, r0 642; CHECK-NEXT: mov r0, r6 643; CHECK-NEXT: mov r1, r11 644; CHECK-NEXT: bl __aeabi_d2ulz 645; CHECK-NEXT: vmov r8, r1, d11 646; CHECK-NEXT: vldr d0, .LCPI12_1 647; CHECK-NEXT: cmp r4, #0 648; CHECK-NEXT: vmov r10, r9, d9 649; CHECK-NEXT: vmov r2, r3, d0 650; CHECK-NEXT: csel r4, r0, r4, ne 651; CHECK-NEXT: mov r0, r6 652; CHECK-NEXT: str r1, [sp, #8] @ 4-byte Spill 653; CHECK-NEXT: vmov r5, r1, d10 654; CHECK-NEXT: strd r5, r1, [sp, #12] @ 8-byte Folded Spill 655; CHECK-NEXT: mov r1, r11 656; CHECK-NEXT: mov r11, r2 657; CHECK-NEXT: mov r5, r3 658; CHECK-NEXT: bl __aeabi_dcmpgt 659; CHECK-NEXT: cmp r0, #0 660; CHECK-NEXT: it ne 661; CHECK-NEXT: movne.w r4, #-1 662; CHECK-NEXT: str r4, [r7, #16] 663; CHECK-NEXT: mov r0, r10 664; CHECK-NEXT: ldr r7, [sp, #28] @ 4-byte Reload 665; CHECK-NEXT: mov r1, r9 666; CHECK-NEXT: ldr r6, [sp, #4] @ 4-byte Reload 667; CHECK-NEXT: mov r2, r7 668; CHECK-NEXT: mov r3, r6 669; CHECK-NEXT: bl __aeabi_dcmpge 670; CHECK-NEXT: mov r4, r0 671; CHECK-NEXT: mov r0, r10 672; CHECK-NEXT: mov r1, r9 673; CHECK-NEXT: bl __aeabi_d2ulz 674; CHECK-NEXT: cmp r4, #0 675; CHECK-NEXT: mov r1, r9 676; CHECK-NEXT: csel r4, r0, r4, ne 677; CHECK-NEXT: mov r0, r10 678; CHECK-NEXT: mov r2, r11 679; CHECK-NEXT: mov r3, r5 680; CHECK-NEXT: mov r10, r11 681; CHECK-NEXT: mov r11, r5 682; CHECK-NEXT: bl __aeabi_dcmpgt 683; CHECK-NEXT: cmp r0, #0 684; CHECK-NEXT: it ne 685; CHECK-NEXT: movne.w r4, #-1 686; CHECK-NEXT: ldr r5, [sp, #8] @ 4-byte Reload 687; CHECK-NEXT: mov r0, r8 688; CHECK-NEXT: mov r2, r7 689; CHECK-NEXT: mov r3, r6 690; CHECK-NEXT: str r4, [sp, #20] @ 4-byte Spill 691; CHECK-NEXT: mov r1, r5 692; CHECK-NEXT: bl __aeabi_dcmpge 693; CHECK-NEXT: mov r4, r0 694; CHECK-NEXT: mov r0, r8 695; CHECK-NEXT: mov r1, r5 696; CHECK-NEXT: bl __aeabi_d2ulz 697; CHECK-NEXT: cmp r4, #0 698; CHECK-NEXT: mov r1, r5 699; CHECK-NEXT: csel r9, r0, r4, ne 700; CHECK-NEXT: mov r0, r8 701; CHECK-NEXT: mov r2, r10 702; CHECK-NEXT: mov r3, r11 703; CHECK-NEXT: mov r8, r11 704; CHECK-NEXT: bl __aeabi_dcmpgt 705; CHECK-NEXT: cmp r0, #0 706; CHECK-NEXT: it ne 707; CHECK-NEXT: movne.w r9, #-1 708; CHECK-NEXT: ldr.w r11, [sp, #12] @ 4-byte Reload 709; CHECK-NEXT: mov r2, r7 710; CHECK-NEXT: ldr r5, [sp, #16] @ 4-byte Reload 711; CHECK-NEXT: mov r3, r6 712; CHECK-NEXT: mov r0, r11 713; CHECK-NEXT: mov r1, r5 714; CHECK-NEXT: bl __aeabi_dcmpge 715; CHECK-NEXT: mov r4, r0 716; CHECK-NEXT: mov r0, r11 717; CHECK-NEXT: mov r1, r5 718; CHECK-NEXT: bl __aeabi_d2ulz 719; CHECK-NEXT: cmp r4, #0 720; CHECK-NEXT: mov r1, r5 721; CHECK-NEXT: csel r7, r0, r4, ne 722; CHECK-NEXT: mov r0, r11 723; CHECK-NEXT: mov r2, r10 724; CHECK-NEXT: mov r3, r8 725; CHECK-NEXT: bl __aeabi_dcmpgt 726; CHECK-NEXT: vmov r4, r5, d8 727; CHECK-NEXT: cmp r0, #0 728; CHECK-NEXT: it ne 729; CHECK-NEXT: movne.w r7, #-1 730; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload 731; CHECK-NEXT: mov r3, r6 732; CHECK-NEXT: mov r0, r4 733; CHECK-NEXT: mov r1, r5 734; CHECK-NEXT: bl __aeabi_dcmpge 735; CHECK-NEXT: mov r6, r0 736; CHECK-NEXT: mov r0, r4 737; CHECK-NEXT: mov r1, r5 738; CHECK-NEXT: bl __aeabi_d2ulz 739; CHECK-NEXT: cmp r6, #0 740; CHECK-NEXT: mov r1, r5 741; CHECK-NEXT: csel r6, r0, r6, ne 742; CHECK-NEXT: mov r0, r4 743; CHECK-NEXT: mov r2, r10 744; CHECK-NEXT: mov r3, r8 745; CHECK-NEXT: bl __aeabi_dcmpgt 746; CHECK-NEXT: cmp r0, #0 747; CHECK-NEXT: it ne 748; CHECK-NEXT: movne.w r6, #-1 749; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload 750; CHECK-NEXT: vmov q0[2], q0[0], r6, r7 751; CHECK-NEXT: vmov q0[3], q0[1], r9, r0 752; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload 753; CHECK-NEXT: vstrw.32 q0, [r0] 754; CHECK-NEXT: add sp, #32 755; CHECK-NEXT: vpop {d8, d9, d10, d11} 756; CHECK-NEXT: add sp, #4 757; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 758; CHECK-NEXT: .p2align 3 759; CHECK-NEXT: @ %bb.1: 760; CHECK-NEXT: .LCPI12_0: 761; CHECK-NEXT: .long 0 @ double 0 762; CHECK-NEXT: .long 0 763; CHECK-NEXT: .LCPI12_1: 764; CHECK-NEXT: .long 4292870144 @ double 4294967295 765; CHECK-NEXT: .long 1106247679 766 %x = call <5 x i32> @llvm.fptoui.sat.v5f64.v5i32(<5 x double> %f) 767 ret <5 x i32> %x 768} 769 770define arm_aapcs_vfpcc <6 x i32> @test_unsigned_v6f64_v6i32(<6 x double> %f) { 771; CHECK-LABEL: test_unsigned_v6f64_v6i32: 772; CHECK: @ %bb.0: 773; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 774; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 775; CHECK-NEXT: .pad #4 776; CHECK-NEXT: sub sp, #4 777; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12} 778; CHECK-NEXT: vpush {d8, d9, d10, d11, d12} 779; CHECK-NEXT: .pad #40 780; CHECK-NEXT: sub sp, #40 781; CHECK-NEXT: vmov.f32 s16, s0 782; CHECK-NEXT: str r0, [sp, #36] @ 4-byte Spill 783; CHECK-NEXT: vmov.f32 s17, s1 784; CHECK-NEXT: vldr d0, .LCPI13_0 785; CHECK-NEXT: vmov r5, r6, d5 786; CHECK-NEXT: vmov r10, r3, d0 787; CHECK-NEXT: vmov.f32 s20, s8 788; CHECK-NEXT: vmov.f32 s22, s6 789; CHECK-NEXT: vmov.f32 s18, s4 790; CHECK-NEXT: vmov.f32 s24, s2 791; CHECK-NEXT: vmov.f32 s21, s9 792; CHECK-NEXT: vmov.f32 s23, s7 793; CHECK-NEXT: vmov.f32 s19, s5 794; CHECK-NEXT: vmov.f32 s25, s3 795; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill 796; CHECK-NEXT: mov r0, r5 797; CHECK-NEXT: mov r1, r6 798; CHECK-NEXT: mov r2, r10 799; CHECK-NEXT: bl __aeabi_dcmpge 800; CHECK-NEXT: mov r4, r0 801; CHECK-NEXT: mov r0, r5 802; CHECK-NEXT: mov r1, r6 803; CHECK-NEXT: bl __aeabi_d2ulz 804; CHECK-NEXT: vmov r9, r1, d11 805; CHECK-NEXT: vldr d0, .LCPI13_1 806; CHECK-NEXT: cmp r4, #0 807; CHECK-NEXT: vmov r8, r11, d10 808; CHECK-NEXT: vmov r2, r3, d0 809; CHECK-NEXT: csel r4, r0, r4, ne 810; CHECK-NEXT: mov r0, r5 811; CHECK-NEXT: str r1, [sp, #32] @ 4-byte Spill 812; CHECK-NEXT: vmov r7, r1, d12 813; CHECK-NEXT: str r3, [sp, #8] @ 4-byte Spill 814; CHECK-NEXT: mov r5, r2 815; CHECK-NEXT: strd r7, r1, [sp, #24] @ 8-byte Folded Spill 816; CHECK-NEXT: mov r1, r6 817; CHECK-NEXT: bl __aeabi_dcmpgt 818; CHECK-NEXT: cmp r0, #0 819; CHECK-NEXT: it ne 820; CHECK-NEXT: movne.w r4, #-1 821; CHECK-NEXT: ldr r7, [sp, #36] @ 4-byte Reload 822; CHECK-NEXT: mov r0, r8 823; CHECK-NEXT: mov r1, r11 824; CHECK-NEXT: mov r2, r10 825; CHECK-NEXT: str r4, [r7, #20] 826; CHECK-NEXT: ldr r6, [sp, #12] @ 4-byte Reload 827; CHECK-NEXT: mov r3, r6 828; CHECK-NEXT: bl __aeabi_dcmpge 829; CHECK-NEXT: mov r4, r0 830; CHECK-NEXT: mov r0, r8 831; CHECK-NEXT: mov r1, r11 832; CHECK-NEXT: bl __aeabi_d2ulz 833; CHECK-NEXT: vmov r2, r1, d9 834; CHECK-NEXT: cmp r4, #0 835; CHECK-NEXT: csel r4, r0, r4, ne 836; CHECK-NEXT: mov r0, r8 837; CHECK-NEXT: mov r8, r5 838; CHECK-NEXT: strd r2, r1, [sp, #16] @ 8-byte Folded Spill 839; CHECK-NEXT: mov r1, r11 840; CHECK-NEXT: ldr.w r11, [sp, #8] @ 4-byte Reload 841; CHECK-NEXT: mov r2, r5 842; CHECK-NEXT: mov r3, r11 843; CHECK-NEXT: bl __aeabi_dcmpgt 844; CHECK-NEXT: cmp r0, #0 845; CHECK-NEXT: it ne 846; CHECK-NEXT: movne.w r4, #-1 847; CHECK-NEXT: str r4, [r7, #16] 848; CHECK-NEXT: mov r0, r9 849; CHECK-NEXT: ldr r5, [sp, #32] @ 4-byte Reload 850; CHECK-NEXT: mov r2, r10 851; CHECK-NEXT: mov r3, r6 852; CHECK-NEXT: mov r1, r5 853; CHECK-NEXT: bl __aeabi_dcmpge 854; CHECK-NEXT: mov r4, r0 855; CHECK-NEXT: mov r0, r9 856; CHECK-NEXT: mov r1, r5 857; CHECK-NEXT: bl __aeabi_d2ulz 858; CHECK-NEXT: cmp r4, #0 859; CHECK-NEXT: mov r1, r5 860; CHECK-NEXT: csel r4, r0, r4, ne 861; CHECK-NEXT: mov r0, r9 862; CHECK-NEXT: mov r2, r8 863; CHECK-NEXT: mov r3, r11 864; CHECK-NEXT: str.w r8, [sp, #4] @ 4-byte Spill 865; CHECK-NEXT: bl __aeabi_dcmpgt 866; CHECK-NEXT: cmp r0, #0 867; CHECK-NEXT: it ne 868; CHECK-NEXT: movne.w r4, #-1 869; CHECK-NEXT: ldr r5, [sp, #24] @ 4-byte Reload 870; CHECK-NEXT: mov r2, r10 871; CHECK-NEXT: ldr r7, [sp, #28] @ 4-byte Reload 872; CHECK-NEXT: mov r3, r6 873; CHECK-NEXT: str r4, [sp, #32] @ 4-byte Spill 874; CHECK-NEXT: mov r0, r5 875; CHECK-NEXT: mov r1, r7 876; CHECK-NEXT: bl __aeabi_dcmpge 877; CHECK-NEXT: mov r4, r0 878; CHECK-NEXT: mov r0, r5 879; CHECK-NEXT: mov r1, r7 880; CHECK-NEXT: bl __aeabi_d2ulz 881; CHECK-NEXT: cmp r4, #0 882; CHECK-NEXT: mov r1, r7 883; CHECK-NEXT: csel r9, r0, r4, ne 884; CHECK-NEXT: mov r0, r5 885; CHECK-NEXT: mov r2, r8 886; CHECK-NEXT: mov r3, r11 887; CHECK-NEXT: bl __aeabi_dcmpgt 888; CHECK-NEXT: cmp r0, #0 889; CHECK-NEXT: it ne 890; CHECK-NEXT: movne.w r9, #-1 891; CHECK-NEXT: ldr r7, [sp, #16] @ 4-byte Reload 892; CHECK-NEXT: mov r2, r10 893; CHECK-NEXT: ldr r5, [sp, #20] @ 4-byte Reload 894; CHECK-NEXT: mov r3, r6 895; CHECK-NEXT: mov r0, r7 896; CHECK-NEXT: mov r1, r5 897; CHECK-NEXT: bl __aeabi_dcmpge 898; CHECK-NEXT: mov r4, r0 899; CHECK-NEXT: mov r0, r7 900; CHECK-NEXT: mov r1, r5 901; CHECK-NEXT: bl __aeabi_d2ulz 902; CHECK-NEXT: cmp r4, #0 903; CHECK-NEXT: mov r1, r5 904; CHECK-NEXT: csel r8, r0, r4, ne 905; CHECK-NEXT: mov r0, r7 906; CHECK-NEXT: ldr r7, [sp, #4] @ 4-byte Reload 907; CHECK-NEXT: mov r3, r11 908; CHECK-NEXT: mov r2, r7 909; CHECK-NEXT: bl __aeabi_dcmpgt 910; CHECK-NEXT: vmov r4, r5, d8 911; CHECK-NEXT: cmp r0, #0 912; CHECK-NEXT: mov r2, r10 913; CHECK-NEXT: mov r3, r6 914; CHECK-NEXT: it ne 915; CHECK-NEXT: movne.w r8, #-1 916; CHECK-NEXT: mov r0, r4 917; CHECK-NEXT: mov r1, r5 918; CHECK-NEXT: bl __aeabi_dcmpge 919; CHECK-NEXT: mov r6, r0 920; CHECK-NEXT: mov r0, r4 921; CHECK-NEXT: mov r1, r5 922; CHECK-NEXT: bl __aeabi_d2ulz 923; CHECK-NEXT: cmp r6, #0 924; CHECK-NEXT: mov r1, r5 925; CHECK-NEXT: csel r6, r0, r6, ne 926; CHECK-NEXT: mov r0, r4 927; CHECK-NEXT: mov r2, r7 928; CHECK-NEXT: mov r3, r11 929; CHECK-NEXT: bl __aeabi_dcmpgt 930; CHECK-NEXT: cmp r0, #0 931; CHECK-NEXT: it ne 932; CHECK-NEXT: movne.w r6, #-1 933; CHECK-NEXT: ldr r0, [sp, #32] @ 4-byte Reload 934; CHECK-NEXT: vmov q0[2], q0[0], r6, r8 935; CHECK-NEXT: vmov q0[3], q0[1], r9, r0 936; CHECK-NEXT: ldr r0, [sp, #36] @ 4-byte Reload 937; CHECK-NEXT: vstrw.32 q0, [r0] 938; CHECK-NEXT: add sp, #40 939; CHECK-NEXT: vpop {d8, d9, d10, d11, d12} 940; CHECK-NEXT: add sp, #4 941; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 942; CHECK-NEXT: .p2align 3 943; CHECK-NEXT: @ %bb.1: 944; CHECK-NEXT: .LCPI13_0: 945; CHECK-NEXT: .long 0 @ double 0 946; CHECK-NEXT: .long 0 947; CHECK-NEXT: .LCPI13_1: 948; CHECK-NEXT: .long 4292870144 @ double 4294967295 949; CHECK-NEXT: .long 1106247679 950 %x = call <6 x i32> @llvm.fptoui.sat.v6f64.v6i32(<6 x double> %f) 951 ret <6 x i32> %x 952} 953 954; 955; FP16 to signed 32-bit -- Vector size variation 956; 957 958declare <1 x i32> @llvm.fptoui.sat.v1f16.v1i32 (<1 x half>) 959declare <2 x i32> @llvm.fptoui.sat.v2f16.v2i32 (<2 x half>) 960declare <3 x i32> @llvm.fptoui.sat.v3f16.v3i32 (<3 x half>) 961declare <4 x i32> @llvm.fptoui.sat.v4f16.v4i32 (<4 x half>) 962declare <5 x i32> @llvm.fptoui.sat.v5f16.v5i32 (<5 x half>) 963declare <6 x i32> @llvm.fptoui.sat.v6f16.v6i32 (<6 x half>) 964declare <7 x i32> @llvm.fptoui.sat.v7f16.v7i32 (<7 x half>) 965declare <8 x i32> @llvm.fptoui.sat.v8f16.v8i32 (<8 x half>) 966 967define arm_aapcs_vfpcc <1 x i32> @test_unsigned_v1f16_v1i32(<1 x half> %f) { 968; CHECK-LABEL: test_unsigned_v1f16_v1i32: 969; CHECK: @ %bb.0: 970; CHECK-NEXT: vcvt.u32.f16 s0, s0 971; CHECK-NEXT: vmov r0, s0 972; CHECK-NEXT: bx lr 973 %x = call <1 x i32> @llvm.fptoui.sat.v1f16.v1i32(<1 x half> %f) 974 ret <1 x i32> %x 975} 976 977define arm_aapcs_vfpcc <2 x i32> @test_unsigned_v2f16_v2i32(<2 x half> %f) { 978; CHECK-LABEL: test_unsigned_v2f16_v2i32: 979; CHECK: @ %bb.0: 980; CHECK-NEXT: .save {r4, r5, r7, lr} 981; CHECK-NEXT: push {r4, r5, r7, lr} 982; CHECK-NEXT: .vsave {d8, d9, d10} 983; CHECK-NEXT: vpush {d8, d9, d10} 984; CHECK-NEXT: vmov q4, q0 985; CHECK-NEXT: vcvtt.f32.f16 s18, s16 986; CHECK-NEXT: vmov r0, s18 987; CHECK-NEXT: bl __aeabi_f2ulz 988; CHECK-NEXT: vcvtb.f32.f16 s16, s16 989; CHECK-NEXT: mov r5, r0 990; CHECK-NEXT: vmov r0, s16 991; CHECK-NEXT: vldr s20, .LCPI15_0 992; CHECK-NEXT: vcmp.f32 s18, #0 993; CHECK-NEXT: mov r4, r1 994; CHECK-NEXT: vmrs APSR_nzcv, fpscr 995; CHECK-NEXT: itt lt 996; CHECK-NEXT: movlt r5, #0 997; CHECK-NEXT: movlt r4, #0 998; CHECK-NEXT: vcmp.f32 s18, s20 999; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1000; CHECK-NEXT: itt gt 1001; CHECK-NEXT: movgt r4, #0 1002; CHECK-NEXT: movgt.w r5, #-1 1003; CHECK-NEXT: bl __aeabi_f2ulz 1004; CHECK-NEXT: vcmp.f32 s16, #0 1005; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1006; CHECK-NEXT: itt lt 1007; CHECK-NEXT: movlt r1, #0 1008; CHECK-NEXT: movlt r0, #0 1009; CHECK-NEXT: vcmp.f32 s16, s20 1010; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1011; CHECK-NEXT: itt gt 1012; CHECK-NEXT: movgt.w r0, #-1 1013; CHECK-NEXT: movgt r1, #0 1014; CHECK-NEXT: vmov q0[2], q0[0], r0, r5 1015; CHECK-NEXT: vmov q0[3], q0[1], r1, r4 1016; CHECK-NEXT: vpop {d8, d9, d10} 1017; CHECK-NEXT: pop {r4, r5, r7, pc} 1018; CHECK-NEXT: .p2align 2 1019; CHECK-NEXT: @ %bb.1: 1020; CHECK-NEXT: .LCPI15_0: 1021; CHECK-NEXT: .long 0x4f7fffff @ float 4.29496704E+9 1022 %x = call <2 x i32> @llvm.fptoui.sat.v2f16.v2i32(<2 x half> %f) 1023 ret <2 x i32> %x 1024} 1025 1026define arm_aapcs_vfpcc <3 x i32> @test_unsigned_v3f16_v3i32(<3 x half> %f) { 1027; CHECK-LABEL: test_unsigned_v3f16_v3i32: 1028; CHECK: @ %bb.0: 1029; CHECK-NEXT: vcvt.u32.f16 s6, s0 1030; CHECK-NEXT: vcvt.u32.f16 s0, s1 1031; CHECK-NEXT: vcvt.u32.f16 s4, s2 1032; CHECK-NEXT: vmov r0, s0 1033; CHECK-NEXT: vmov.32 q0[1], r0 1034; CHECK-NEXT: vmov r0, s4 1035; CHECK-NEXT: vmov r1, s6 1036; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 1037; CHECK-NEXT: bx lr 1038 %x = call <3 x i32> @llvm.fptoui.sat.v3f16.v3i32(<3 x half> %f) 1039 ret <3 x i32> %x 1040} 1041 1042define arm_aapcs_vfpcc <4 x i32> @test_unsigned_v4f16_v4i32(<4 x half> %f) { 1043; CHECK-LABEL: test_unsigned_v4f16_v4i32: 1044; CHECK: @ %bb.0: 1045; CHECK-NEXT: vmovx.f16 s2, s1 1046; CHECK-NEXT: vcvt.u32.f16 s4, s2 1047; CHECK-NEXT: vmovx.f16 s2, s0 1048; CHECK-NEXT: vcvt.u32.f16 s6, s2 1049; CHECK-NEXT: vcvt.u32.f16 s2, s1 1050; CHECK-NEXT: vcvt.u32.f16 s0, s0 1051; CHECK-NEXT: vmov r0, s2 1052; CHECK-NEXT: vmov r1, s0 1053; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 1054; CHECK-NEXT: vmov r0, s4 1055; CHECK-NEXT: vmov r1, s6 1056; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 1057; CHECK-NEXT: bx lr 1058 %x = call <4 x i32> @llvm.fptoui.sat.v4f16.v4i32(<4 x half> %f) 1059 ret <4 x i32> %x 1060} 1061 1062define arm_aapcs_vfpcc <5 x i32> @test_unsigned_v5f16_v5i32(<5 x half> %f) { 1063; CHECK-LABEL: test_unsigned_v5f16_v5i32: 1064; CHECK: @ %bb.0: 1065; CHECK-NEXT: vmovx.f16 s6, s0 1066; CHECK-NEXT: vmovx.f16 s4, s1 1067; CHECK-NEXT: vcvt.u32.f16 s8, s1 1068; CHECK-NEXT: vcvt.u32.f16 s0, s0 1069; CHECK-NEXT: vcvt.u32.f16 s4, s4 1070; CHECK-NEXT: vcvt.u32.f16 s6, s6 1071; CHECK-NEXT: vmov r1, s8 1072; CHECK-NEXT: vcvt.u32.f16 s2, s2 1073; CHECK-NEXT: vmov r2, s0 1074; CHECK-NEXT: vmov q2[2], q2[0], r2, r1 1075; CHECK-NEXT: vmov r1, s4 1076; CHECK-NEXT: vmov r2, s6 1077; CHECK-NEXT: vmov q2[3], q2[1], r2, r1 1078; CHECK-NEXT: vmov r1, s2 1079; CHECK-NEXT: str r1, [r0, #16] 1080; CHECK-NEXT: vstrw.32 q2, [r0] 1081; CHECK-NEXT: bx lr 1082 %x = call <5 x i32> @llvm.fptoui.sat.v5f16.v5i32(<5 x half> %f) 1083 ret <5 x i32> %x 1084} 1085 1086define arm_aapcs_vfpcc <6 x i32> @test_unsigned_v6f16_v6i32(<6 x half> %f) { 1087; CHECK-LABEL: test_unsigned_v6f16_v6i32: 1088; CHECK: @ %bb.0: 1089; CHECK-NEXT: vmovx.f16 s8, s0 1090; CHECK-NEXT: vmovx.f16 s6, s1 1091; CHECK-NEXT: vcvt.u32.f16 s10, s1 1092; CHECK-NEXT: vcvt.u32.f16 s0, s0 1093; CHECK-NEXT: vcvt.u32.f16 s4, s2 1094; CHECK-NEXT: vmovx.f16 s2, s2 1095; CHECK-NEXT: vcvt.u32.f16 s6, s6 1096; CHECK-NEXT: vcvt.u32.f16 s8, s8 1097; CHECK-NEXT: vmov r1, s10 1098; CHECK-NEXT: vcvt.u32.f16 s2, s2 1099; CHECK-NEXT: vmov r2, s0 1100; CHECK-NEXT: vmov q3[2], q3[0], r2, r1 1101; CHECK-NEXT: vmov r1, s6 1102; CHECK-NEXT: vmov r2, s8 1103; CHECK-NEXT: vmov q3[3], q3[1], r2, r1 1104; CHECK-NEXT: vmov r1, s2 1105; CHECK-NEXT: vmov r2, s4 1106; CHECK-NEXT: strd r2, r1, [r0, #16] 1107; CHECK-NEXT: vstrw.32 q3, [r0] 1108; CHECK-NEXT: bx lr 1109 %x = call <6 x i32> @llvm.fptoui.sat.v6f16.v6i32(<6 x half> %f) 1110 ret <6 x i32> %x 1111} 1112 1113define arm_aapcs_vfpcc <7 x i32> @test_unsigned_v7f16_v7i32(<7 x half> %f) { 1114; CHECK-LABEL: test_unsigned_v7f16_v7i32: 1115; CHECK: @ %bb.0: 1116; CHECK-NEXT: vmovx.f16 s10, s0 1117; CHECK-NEXT: vmovx.f16 s8, s1 1118; CHECK-NEXT: vcvt.u32.f16 s12, s1 1119; CHECK-NEXT: vcvt.u32.f16 s0, s0 1120; CHECK-NEXT: vcvt.u32.f16 s4, s2 1121; CHECK-NEXT: vmovx.f16 s2, s2 1122; CHECK-NEXT: vcvt.u32.f16 s8, s8 1123; CHECK-NEXT: vcvt.u32.f16 s10, s10 1124; CHECK-NEXT: vmov r1, s12 1125; CHECK-NEXT: vcvt.u32.f16 s2, s2 1126; CHECK-NEXT: vmov r2, s0 1127; CHECK-NEXT: vcvt.u32.f16 s6, s3 1128; CHECK-NEXT: vmov q3[2], q3[0], r2, r1 1129; CHECK-NEXT: vmov r1, s8 1130; CHECK-NEXT: vmov r2, s10 1131; CHECK-NEXT: vmov q3[3], q3[1], r2, r1 1132; CHECK-NEXT: vmov r1, s2 1133; CHECK-NEXT: vmov r2, s4 1134; CHECK-NEXT: vmov r3, s6 1135; CHECK-NEXT: strd r2, r1, [r0, #16] 1136; CHECK-NEXT: str r3, [r0, #24] 1137; CHECK-NEXT: vstrw.32 q3, [r0] 1138; CHECK-NEXT: bx lr 1139 %x = call <7 x i32> @llvm.fptoui.sat.v7f16.v7i32(<7 x half> %f) 1140 ret <7 x i32> %x 1141} 1142 1143define arm_aapcs_vfpcc <8 x i32> @test_unsigned_v8f16_v8i32(<8 x half> %f) { 1144; CHECK-LABEL: test_unsigned_v8f16_v8i32: 1145; CHECK: @ %bb.0: 1146; CHECK-NEXT: vmovx.f16 s4, s3 1147; CHECK-NEXT: vmovx.f16 s6, s0 1148; CHECK-NEXT: vcvt.u32.f16 s8, s4 1149; CHECK-NEXT: vmovx.f16 s4, s2 1150; CHECK-NEXT: vcvt.u32.f16 s10, s4 1151; CHECK-NEXT: vmovx.f16 s4, s1 1152; CHECK-NEXT: vcvt.u32.f16 s14, s2 1153; CHECK-NEXT: vcvt.u32.f16 s2, s1 1154; CHECK-NEXT: vcvt.u32.f16 s0, s0 1155; CHECK-NEXT: vcvt.u32.f16 s4, s4 1156; CHECK-NEXT: vcvt.u32.f16 s6, s6 1157; CHECK-NEXT: vmov r0, s2 1158; CHECK-NEXT: vmov r1, s0 1159; CHECK-NEXT: vcvt.u32.f16 s12, s3 1160; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 1161; CHECK-NEXT: vmov r0, s4 1162; CHECK-NEXT: vmov r1, s6 1163; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 1164; CHECK-NEXT: vmov r0, s12 1165; CHECK-NEXT: vmov r1, s14 1166; CHECK-NEXT: vmov q1[2], q1[0], r1, r0 1167; CHECK-NEXT: vmov r0, s8 1168; CHECK-NEXT: vmov r1, s10 1169; CHECK-NEXT: vmov q1[3], q1[1], r1, r0 1170; CHECK-NEXT: bx lr 1171 %x = call <8 x i32> @llvm.fptoui.sat.v8f16.v8i32(<8 x half> %f) 1172 ret <8 x i32> %x 1173} 1174 1175; 1176; 2-Vector float to signed integer -- result size variation 1177; 1178 1179declare <4 x i1> @llvm.fptoui.sat.v4f32.v4i1 (<4 x float>) 1180declare <4 x i8> @llvm.fptoui.sat.v4f32.v4i8 (<4 x float>) 1181declare <4 x i13> @llvm.fptoui.sat.v4f32.v4i13 (<4 x float>) 1182declare <4 x i16> @llvm.fptoui.sat.v4f32.v4i16 (<4 x float>) 1183declare <4 x i19> @llvm.fptoui.sat.v4f32.v4i19 (<4 x float>) 1184declare <4 x i50> @llvm.fptoui.sat.v4f32.v4i50 (<4 x float>) 1185declare <4 x i64> @llvm.fptoui.sat.v4f32.v4i64 (<4 x float>) 1186declare <4 x i100> @llvm.fptoui.sat.v4f32.v4i100(<4 x float>) 1187declare <4 x i128> @llvm.fptoui.sat.v4f32.v4i128(<4 x float>) 1188 1189define arm_aapcs_vfpcc <4 x i1> @test_unsigned_v4f32_v4i1(<4 x float> %f) { 1190; CHECK-LABEL: test_unsigned_v4f32_v4i1: 1191; CHECK: @ %bb.0: 1192; CHECK-NEXT: vldr s4, .LCPI22_0 1193; CHECK-NEXT: vmov.f32 s6, #1.000000e+00 1194; CHECK-NEXT: movs r1, #0 1195; CHECK-NEXT: vmaxnm.f32 s0, s0, s4 1196; CHECK-NEXT: vmaxnm.f32 s8, s3, s4 1197; CHECK-NEXT: vminnm.f32 s0, s0, s6 1198; CHECK-NEXT: vmaxnm.f32 s2, s2, s4 1199; CHECK-NEXT: vcvt.u32.f32 s0, s0 1200; CHECK-NEXT: vmaxnm.f32 s4, s1, s4 1201; CHECK-NEXT: vminnm.f32 s4, s4, s6 1202; CHECK-NEXT: vminnm.f32 s2, s2, s6 1203; CHECK-NEXT: vcvt.u32.f32 s4, s4 1204; CHECK-NEXT: vminnm.f32 s8, s8, s6 1205; CHECK-NEXT: vcvt.u32.f32 s2, s2 1206; CHECK-NEXT: vcvt.u32.f32 s8, s8 1207; CHECK-NEXT: vmov r2, s0 1208; CHECK-NEXT: and r2, r2, #1 1209; CHECK-NEXT: rsbs r2, r2, #0 1210; CHECK-NEXT: bfi r1, r2, #0, #1 1211; CHECK-NEXT: vmov r2, s4 1212; CHECK-NEXT: and r2, r2, #1 1213; CHECK-NEXT: rsbs r2, r2, #0 1214; CHECK-NEXT: bfi r1, r2, #1, #1 1215; CHECK-NEXT: vmov r2, s2 1216; CHECK-NEXT: and r2, r2, #1 1217; CHECK-NEXT: rsbs r2, r2, #0 1218; CHECK-NEXT: bfi r1, r2, #2, #1 1219; CHECK-NEXT: vmov r2, s8 1220; CHECK-NEXT: and r2, r2, #1 1221; CHECK-NEXT: rsbs r2, r2, #0 1222; CHECK-NEXT: bfi r1, r2, #3, #1 1223; CHECK-NEXT: strb r1, [r0] 1224; CHECK-NEXT: bx lr 1225; CHECK-NEXT: .p2align 2 1226; CHECK-NEXT: @ %bb.1: 1227; CHECK-NEXT: .LCPI22_0: 1228; CHECK-NEXT: .long 0x00000000 @ float 0 1229 %x = call <4 x i1> @llvm.fptoui.sat.v4f32.v4i1(<4 x float> %f) 1230 ret <4 x i1> %x 1231} 1232 1233define arm_aapcs_vfpcc <4 x i8> @test_unsigned_v4f32_v4i8(<4 x float> %f) { 1234; CHECK-MVE-LABEL: test_unsigned_v4f32_v4i8: 1235; CHECK-MVE: @ %bb.0: 1236; CHECK-MVE-NEXT: vldr s4, .LCPI23_0 1237; CHECK-MVE-NEXT: vldr s6, .LCPI23_1 1238; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s4 1239; CHECK-MVE-NEXT: vmaxnm.f32 s0, s0, s4 1240; CHECK-MVE-NEXT: vmaxnm.f32 s8, s3, s4 1241; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s6 1242; CHECK-MVE-NEXT: vminnm.f32 s0, s0, s6 1243; CHECK-MVE-NEXT: vmaxnm.f32 s4, s1, s4 1244; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6 1245; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6 1246; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2 1247; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0 1248; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s8 1249; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4 1250; CHECK-MVE-NEXT: vmov r0, s2 1251; CHECK-MVE-NEXT: vmov r1, s0 1252; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0 1253; CHECK-MVE-NEXT: vmov r0, s8 1254; CHECK-MVE-NEXT: vmov r1, s4 1255; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0 1256; CHECK-MVE-NEXT: bx lr 1257; CHECK-MVE-NEXT: .p2align 2 1258; CHECK-MVE-NEXT: @ %bb.1: 1259; CHECK-MVE-NEXT: .LCPI23_0: 1260; CHECK-MVE-NEXT: .long 0x00000000 @ float 0 1261; CHECK-MVE-NEXT: .LCPI23_1: 1262; CHECK-MVE-NEXT: .long 0x437f0000 @ float 255 1263; 1264; CHECK-MVEFP-LABEL: test_unsigned_v4f32_v4i8: 1265; CHECK-MVEFP: @ %bb.0: 1266; CHECK-MVEFP-NEXT: vmov.i32 q1, #0xff 1267; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0 1268; CHECK-MVEFP-NEXT: vmin.u32 q0, q0, q1 1269; CHECK-MVEFP-NEXT: bx lr 1270 %x = call <4 x i8> @llvm.fptoui.sat.v4f32.v4i8(<4 x float> %f) 1271 ret <4 x i8> %x 1272} 1273 1274define arm_aapcs_vfpcc <4 x i13> @test_unsigned_v4f32_v4i13(<4 x float> %f) { 1275; CHECK-MVE-LABEL: test_unsigned_v4f32_v4i13: 1276; CHECK-MVE: @ %bb.0: 1277; CHECK-MVE-NEXT: vldr s4, .LCPI24_0 1278; CHECK-MVE-NEXT: vldr s6, .LCPI24_1 1279; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s4 1280; CHECK-MVE-NEXT: vmaxnm.f32 s0, s0, s4 1281; CHECK-MVE-NEXT: vmaxnm.f32 s8, s3, s4 1282; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s6 1283; CHECK-MVE-NEXT: vminnm.f32 s0, s0, s6 1284; CHECK-MVE-NEXT: vmaxnm.f32 s4, s1, s4 1285; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6 1286; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6 1287; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2 1288; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0 1289; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s8 1290; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4 1291; CHECK-MVE-NEXT: vmov r0, s2 1292; CHECK-MVE-NEXT: vmov r1, s0 1293; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0 1294; CHECK-MVE-NEXT: vmov r0, s8 1295; CHECK-MVE-NEXT: vmov r1, s4 1296; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0 1297; CHECK-MVE-NEXT: bx lr 1298; CHECK-MVE-NEXT: .p2align 2 1299; CHECK-MVE-NEXT: @ %bb.1: 1300; CHECK-MVE-NEXT: .LCPI24_0: 1301; CHECK-MVE-NEXT: .long 0x00000000 @ float 0 1302; CHECK-MVE-NEXT: .LCPI24_1: 1303; CHECK-MVE-NEXT: .long 0x45fff800 @ float 8191 1304; 1305; CHECK-MVEFP-LABEL: test_unsigned_v4f32_v4i13: 1306; CHECK-MVEFP: @ %bb.0: 1307; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x1fff 1308; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0 1309; CHECK-MVEFP-NEXT: vmin.u32 q0, q0, q1 1310; CHECK-MVEFP-NEXT: bx lr 1311 %x = call <4 x i13> @llvm.fptoui.sat.v4f32.v4i13(<4 x float> %f) 1312 ret <4 x i13> %x 1313} 1314 1315define arm_aapcs_vfpcc <4 x i16> @test_unsigned_v4f32_v4i16(<4 x float> %f) { 1316; CHECK-MVE-LABEL: test_unsigned_v4f32_v4i16: 1317; CHECK-MVE: @ %bb.0: 1318; CHECK-MVE-NEXT: vldr s4, .LCPI25_0 1319; CHECK-MVE-NEXT: vldr s6, .LCPI25_1 1320; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s4 1321; CHECK-MVE-NEXT: vmaxnm.f32 s0, s0, s4 1322; CHECK-MVE-NEXT: vmaxnm.f32 s8, s3, s4 1323; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s6 1324; CHECK-MVE-NEXT: vminnm.f32 s0, s0, s6 1325; CHECK-MVE-NEXT: vmaxnm.f32 s4, s1, s4 1326; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6 1327; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6 1328; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2 1329; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0 1330; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s8 1331; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4 1332; CHECK-MVE-NEXT: vmov r0, s2 1333; CHECK-MVE-NEXT: vmov r1, s0 1334; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0 1335; CHECK-MVE-NEXT: vmov r0, s8 1336; CHECK-MVE-NEXT: vmov r1, s4 1337; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0 1338; CHECK-MVE-NEXT: bx lr 1339; CHECK-MVE-NEXT: .p2align 2 1340; CHECK-MVE-NEXT: @ %bb.1: 1341; CHECK-MVE-NEXT: .LCPI25_0: 1342; CHECK-MVE-NEXT: .long 0x00000000 @ float 0 1343; CHECK-MVE-NEXT: .LCPI25_1: 1344; CHECK-MVE-NEXT: .long 0x477fff00 @ float 65535 1345; 1346; CHECK-MVEFP-LABEL: test_unsigned_v4f32_v4i16: 1347; CHECK-MVEFP: @ %bb.0: 1348; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0 1349; CHECK-MVEFP-NEXT: vqmovnb.u32 q0, q0 1350; CHECK-MVEFP-NEXT: vmovlb.u16 q0, q0 1351; CHECK-MVEFP-NEXT: bx lr 1352 %x = call <4 x i16> @llvm.fptoui.sat.v4f32.v4i16(<4 x float> %f) 1353 ret <4 x i16> %x 1354} 1355 1356define arm_aapcs_vfpcc <4 x i19> @test_unsigned_v4f32_v4i19(<4 x float> %f) { 1357; CHECK-MVE-LABEL: test_unsigned_v4f32_v4i19: 1358; CHECK-MVE: @ %bb.0: 1359; CHECK-MVE-NEXT: vldr s4, .LCPI26_0 1360; CHECK-MVE-NEXT: vldr s6, .LCPI26_1 1361; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s4 1362; CHECK-MVE-NEXT: vmaxnm.f32 s0, s0, s4 1363; CHECK-MVE-NEXT: vmaxnm.f32 s8, s3, s4 1364; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s6 1365; CHECK-MVE-NEXT: vminnm.f32 s0, s0, s6 1366; CHECK-MVE-NEXT: vmaxnm.f32 s4, s1, s4 1367; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6 1368; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6 1369; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2 1370; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0 1371; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s8 1372; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4 1373; CHECK-MVE-NEXT: vmov r0, s2 1374; CHECK-MVE-NEXT: vmov r1, s0 1375; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0 1376; CHECK-MVE-NEXT: vmov r0, s8 1377; CHECK-MVE-NEXT: vmov r1, s4 1378; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0 1379; CHECK-MVE-NEXT: bx lr 1380; CHECK-MVE-NEXT: .p2align 2 1381; CHECK-MVE-NEXT: @ %bb.1: 1382; CHECK-MVE-NEXT: .LCPI26_0: 1383; CHECK-MVE-NEXT: .long 0x00000000 @ float 0 1384; CHECK-MVE-NEXT: .LCPI26_1: 1385; CHECK-MVE-NEXT: .long 0x48ffffe0 @ float 524287 1386; 1387; CHECK-MVEFP-LABEL: test_unsigned_v4f32_v4i19: 1388; CHECK-MVEFP: @ %bb.0: 1389; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x7ffff 1390; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0 1391; CHECK-MVEFP-NEXT: vmin.u32 q0, q0, q1 1392; CHECK-MVEFP-NEXT: bx lr 1393 %x = call <4 x i19> @llvm.fptoui.sat.v4f32.v4i19(<4 x float> %f) 1394 ret <4 x i19> %x 1395} 1396 1397define arm_aapcs_vfpcc <4 x i32> @test_unsigned_v4f32_v4i32_duplicate(<4 x float> %f) { 1398; CHECK-MVE-LABEL: test_unsigned_v4f32_v4i32_duplicate: 1399; CHECK-MVE: @ %bb.0: 1400; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2 1401; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0 1402; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s3 1403; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s1 1404; CHECK-MVE-NEXT: vmov r0, s2 1405; CHECK-MVE-NEXT: vmov r1, s0 1406; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0 1407; CHECK-MVE-NEXT: vmov r0, s4 1408; CHECK-MVE-NEXT: vmov r1, s6 1409; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0 1410; CHECK-MVE-NEXT: bx lr 1411; 1412; CHECK-MVEFP-LABEL: test_unsigned_v4f32_v4i32_duplicate: 1413; CHECK-MVEFP: @ %bb.0: 1414; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0 1415; CHECK-MVEFP-NEXT: bx lr 1416 %x = call <4 x i32> @llvm.fptoui.sat.v4f32.v4i32(<4 x float> %f) 1417 ret <4 x i32> %x 1418} 1419 1420define arm_aapcs_vfpcc <4 x i50> @test_unsigned_v4f32_v4i50(<4 x float> %f) { 1421; CHECK-LABEL: test_unsigned_v4f32_v4i50: 1422; CHECK: @ %bb.0: 1423; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} 1424; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr} 1425; CHECK-NEXT: .vsave {d8, d9, d10} 1426; CHECK-NEXT: vpush {d8, d9, d10} 1427; CHECK-NEXT: vmov q4, q0 1428; CHECK-NEXT: mov r8, r0 1429; CHECK-NEXT: vmov r0, s16 1430; CHECK-NEXT: bl __aeabi_f2ulz 1431; CHECK-NEXT: mov r5, r0 1432; CHECK-NEXT: vmov r0, s19 1433; CHECK-NEXT: vcmp.f32 s16, #0 1434; CHECK-NEXT: mov r9, r1 1435; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1436; CHECK-NEXT: vmov r7, s18 1437; CHECK-NEXT: vldr s20, .LCPI28_0 1438; CHECK-NEXT: itt lt 1439; CHECK-NEXT: movlt.w r9, #0 1440; CHECK-NEXT: movlt r5, #0 1441; CHECK-NEXT: bl __aeabi_f2ulz 1442; CHECK-NEXT: mov r4, r0 1443; CHECK-NEXT: vcmp.f32 s19, #0 1444; CHECK-NEXT: mov r0, r7 1445; CHECK-NEXT: mov r10, r1 1446; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1447; CHECK-NEXT: itt lt 1448; CHECK-NEXT: movlt.w r10, #0 1449; CHECK-NEXT: movlt r4, #0 1450; CHECK-NEXT: bl __aeabi_f2ulz 1451; CHECK-NEXT: mov r7, r0 1452; CHECK-NEXT: vmov r0, s17 1453; CHECK-NEXT: vcmp.f32 s18, #0 1454; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1455; CHECK-NEXT: vcmp.f32 s18, s20 1456; CHECK-NEXT: itt lt 1457; CHECK-NEXT: movlt r1, #0 1458; CHECK-NEXT: movlt r7, #0 1459; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1460; CHECK-NEXT: vcmp.f32 s19, s20 1461; CHECK-NEXT: it gt 1462; CHECK-NEXT: movgt.w r7, #-1 1463; CHECK-NEXT: itt gt 1464; CHECK-NEXT: movwgt r1, #65535 1465; CHECK-NEXT: movtgt r1, #3 1466; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1467; CHECK-NEXT: it gt 1468; CHECK-NEXT: movgt.w r4, #-1 1469; CHECK-NEXT: itt gt 1470; CHECK-NEXT: movwgt r10, #65535 1471; CHECK-NEXT: movtgt r10, #3 1472; CHECK-NEXT: mov r3, r10 1473; CHECK-NEXT: bfc r1, #18, #14 1474; CHECK-NEXT: bfc r3, #18, #14 1475; CHECK-NEXT: mov r6, r7 1476; CHECK-NEXT: vcmp.f32 s16, s20 1477; CHECK-NEXT: lsll r4, r3, #22 1478; CHECK-NEXT: lsrl r6, r1, #28 1479; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1480; CHECK-NEXT: it gt 1481; CHECK-NEXT: movgt.w r5, #-1 1482; CHECK-NEXT: str.w r5, [r8] 1483; CHECK-NEXT: itt gt 1484; CHECK-NEXT: movwgt r9, #65535 1485; CHECK-NEXT: movtgt r9, #3 1486; CHECK-NEXT: orrs r1, r3 1487; CHECK-NEXT: str.w r1, [r8, #20] 1488; CHECK-NEXT: bl __aeabi_f2ulz 1489; CHECK-NEXT: vcmp.f32 s17, #0 1490; CHECK-NEXT: orr.w r2, r6, r4 1491; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1492; CHECK-NEXT: itt lt 1493; CHECK-NEXT: movlt r0, #0 1494; CHECK-NEXT: movlt r1, #0 1495; CHECK-NEXT: vcmp.f32 s17, s20 1496; CHECK-NEXT: bfc r9, #18, #14 1497; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1498; CHECK-NEXT: itt gt 1499; CHECK-NEXT: movwgt r1, #65535 1500; CHECK-NEXT: movtgt r1, #3 1501; CHECK-NEXT: str.w r2, [r8, #16] 1502; CHECK-NEXT: lsr.w r2, r10, #10 1503; CHECK-NEXT: strb.w r2, [r8, #24] 1504; CHECK-NEXT: it gt 1505; CHECK-NEXT: movgt.w r0, #-1 1506; CHECK-NEXT: mov r2, r0 1507; CHECK-NEXT: bfc r1, #18, #14 1508; CHECK-NEXT: lsrl r2, r1, #14 1509; CHECK-NEXT: orr.w r0, r9, r0, lsl #18 1510; CHECK-NEXT: orr.w r1, r1, r7, lsl #4 1511; CHECK-NEXT: strd r2, r1, [r8, #8] 1512; CHECK-NEXT: str.w r0, [r8, #4] 1513; CHECK-NEXT: vpop {d8, d9, d10} 1514; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc} 1515; CHECK-NEXT: .p2align 2 1516; CHECK-NEXT: @ %bb.1: 1517; CHECK-NEXT: .LCPI28_0: 1518; CHECK-NEXT: .long 0x587fffff @ float 1.12589984E+15 1519 %x = call <4 x i50> @llvm.fptoui.sat.v4f32.v4i50(<4 x float> %f) 1520 ret <4 x i50> %x 1521} 1522 1523define arm_aapcs_vfpcc <4 x i64> @test_unsigned_v4f32_v4i64(<4 x float> %f) { 1524; CHECK-LABEL: test_unsigned_v4f32_v4i64: 1525; CHECK: @ %bb.0: 1526; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 1527; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 1528; CHECK-NEXT: .pad #4 1529; CHECK-NEXT: sub sp, #4 1530; CHECK-NEXT: .vsave {d8, d9, d10} 1531; CHECK-NEXT: vpush {d8, d9, d10} 1532; CHECK-NEXT: vmov q4, q0 1533; CHECK-NEXT: vmov r0, s19 1534; CHECK-NEXT: bl __aeabi_f2ulz 1535; CHECK-NEXT: mov r11, r0 1536; CHECK-NEXT: vmov r0, s18 1537; CHECK-NEXT: vldr s20, .LCPI29_0 1538; CHECK-NEXT: vcmp.f32 s19, #0 1539; CHECK-NEXT: mov r10, r1 1540; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1541; CHECK-NEXT: itt lt 1542; CHECK-NEXT: movlt.w r11, #0 1543; CHECK-NEXT: movlt.w r10, #0 1544; CHECK-NEXT: vcmp.f32 s19, s20 1545; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1546; CHECK-NEXT: vmov r9, s17 1547; CHECK-NEXT: vmov r8, s16 1548; CHECK-NEXT: itt gt 1549; CHECK-NEXT: movgt.w r10, #-1 1550; CHECK-NEXT: movgt.w r11, #-1 1551; CHECK-NEXT: bl __aeabi_f2ulz 1552; CHECK-NEXT: mov r7, r0 1553; CHECK-NEXT: vcmp.f32 s18, #0 1554; CHECK-NEXT: mov r6, r1 1555; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1556; CHECK-NEXT: mov r0, r9 1557; CHECK-NEXT: itt lt 1558; CHECK-NEXT: movlt r6, #0 1559; CHECK-NEXT: movlt r7, #0 1560; CHECK-NEXT: vcmp.f32 s18, s20 1561; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1562; CHECK-NEXT: itt gt 1563; CHECK-NEXT: movgt.w r7, #-1 1564; CHECK-NEXT: movgt.w r6, #-1 1565; CHECK-NEXT: bl __aeabi_f2ulz 1566; CHECK-NEXT: mov r5, r0 1567; CHECK-NEXT: vcmp.f32 s17, #0 1568; CHECK-NEXT: mov r4, r1 1569; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1570; CHECK-NEXT: mov r0, r8 1571; CHECK-NEXT: itt lt 1572; CHECK-NEXT: movlt r5, #0 1573; CHECK-NEXT: movlt r4, #0 1574; CHECK-NEXT: vcmp.f32 s17, s20 1575; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1576; CHECK-NEXT: itt gt 1577; CHECK-NEXT: movgt.w r4, #-1 1578; CHECK-NEXT: movgt.w r5, #-1 1579; CHECK-NEXT: bl __aeabi_f2ulz 1580; CHECK-NEXT: vcmp.f32 s16, #0 1581; CHECK-NEXT: vmov q1[2], q1[0], r7, r11 1582; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1583; CHECK-NEXT: itt lt 1584; CHECK-NEXT: movlt r1, #0 1585; CHECK-NEXT: movlt r0, #0 1586; CHECK-NEXT: vcmp.f32 s16, s20 1587; CHECK-NEXT: vmov q1[3], q1[1], r6, r10 1588; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1589; CHECK-NEXT: itt gt 1590; CHECK-NEXT: movgt.w r0, #-1 1591; CHECK-NEXT: movgt.w r1, #-1 1592; CHECK-NEXT: vmov q0[2], q0[0], r0, r5 1593; CHECK-NEXT: vmov q0[3], q0[1], r1, r4 1594; CHECK-NEXT: vpop {d8, d9, d10} 1595; CHECK-NEXT: add sp, #4 1596; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 1597; CHECK-NEXT: .p2align 2 1598; CHECK-NEXT: @ %bb.1: 1599; CHECK-NEXT: .LCPI29_0: 1600; CHECK-NEXT: .long 0x5f7fffff @ float 1.8446743E+19 1601 %x = call <4 x i64> @llvm.fptoui.sat.v4f32.v4i64(<4 x float> %f) 1602 ret <4 x i64> %x 1603} 1604 1605define arm_aapcs_vfpcc <4 x i100> @test_unsigned_v4f32_v4i100(<4 x float> %f) { 1606; CHECK-LABEL: test_unsigned_v4f32_v4i100: 1607; CHECK: @ %bb.0: 1608; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 1609; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 1610; CHECK-NEXT: .pad #4 1611; CHECK-NEXT: sub sp, #4 1612; CHECK-NEXT: .vsave {d8, d9, d10} 1613; CHECK-NEXT: vpush {d8, d9, d10} 1614; CHECK-NEXT: .pad #8 1615; CHECK-NEXT: sub sp, #8 1616; CHECK-NEXT: vmov q4, q0 1617; CHECK-NEXT: mov r4, r0 1618; CHECK-NEXT: vmov r0, s18 1619; CHECK-NEXT: bl __fixunssfti 1620; CHECK-NEXT: vmov r6, s17 1621; CHECK-NEXT: vldr s20, .LCPI30_0 1622; CHECK-NEXT: vcmp.f32 s18, #0 1623; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1624; CHECK-NEXT: itttt lt 1625; CHECK-NEXT: movlt r3, #0 1626; CHECK-NEXT: movlt r0, #0 1627; CHECK-NEXT: movlt r1, #0 1628; CHECK-NEXT: movlt r2, #0 1629; CHECK-NEXT: vcmp.f32 s18, s20 1630; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1631; CHECK-NEXT: it gt 1632; CHECK-NEXT: movgt.w r2, #-1 1633; CHECK-NEXT: str.w r2, [r4, #33] 1634; CHECK-NEXT: it gt 1635; CHECK-NEXT: movgt.w r1, #-1 1636; CHECK-NEXT: str.w r1, [r4, #29] 1637; CHECK-NEXT: it gt 1638; CHECK-NEXT: movgt.w r0, #-1 1639; CHECK-NEXT: str.w r0, [r4, #25] 1640; CHECK-NEXT: it gt 1641; CHECK-NEXT: movgt r3, #15 1642; CHECK-NEXT: vmov r7, s19 1643; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill 1644; CHECK-NEXT: mov r0, r6 1645; CHECK-NEXT: bl __fixunssfti 1646; CHECK-NEXT: mov r10, r0 1647; CHECK-NEXT: vcmp.f32 s17, #0 1648; CHECK-NEXT: mov r5, r1 1649; CHECK-NEXT: mov r6, r2 1650; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1651; CHECK-NEXT: mov r0, r7 1652; CHECK-NEXT: itttt lt 1653; CHECK-NEXT: movlt.w r10, #0 1654; CHECK-NEXT: movlt r5, #0 1655; CHECK-NEXT: movlt r6, #0 1656; CHECK-NEXT: movlt r3, #0 1657; CHECK-NEXT: vcmp.f32 s17, s20 1658; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1659; CHECK-NEXT: it gt 1660; CHECK-NEXT: movgt r3, #15 1661; CHECK-NEXT: str r3, [sp] @ 4-byte Spill 1662; CHECK-NEXT: ittt gt 1663; CHECK-NEXT: movgt.w r6, #-1 1664; CHECK-NEXT: movgt.w r5, #-1 1665; CHECK-NEXT: movgt.w r10, #-1 1666; CHECK-NEXT: bl __fixunssfti 1667; CHECK-NEXT: mov r7, r0 1668; CHECK-NEXT: vmov r0, s16 1669; CHECK-NEXT: vcmp.f32 s19, #0 1670; CHECK-NEXT: mov r9, r1 1671; CHECK-NEXT: mov r8, r2 1672; CHECK-NEXT: mov r11, r3 1673; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1674; CHECK-NEXT: itttt lt 1675; CHECK-NEXT: movlt.w r9, #0 1676; CHECK-NEXT: movlt r7, #0 1677; CHECK-NEXT: movlt.w r8, #0 1678; CHECK-NEXT: movlt.w r11, #0 1679; CHECK-NEXT: vcmp.f32 s19, s20 1680; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1681; CHECK-NEXT: itttt gt 1682; CHECK-NEXT: movgt.w r11, #15 1683; CHECK-NEXT: movgt.w r8, #-1 1684; CHECK-NEXT: movgt.w r7, #-1 1685; CHECK-NEXT: movgt.w r9, #-1 1686; CHECK-NEXT: bl __fixunssfti 1687; CHECK-NEXT: vcmp.f32 s16, #0 1688; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1689; CHECK-NEXT: itttt lt 1690; CHECK-NEXT: movlt r3, #0 1691; CHECK-NEXT: movlt r0, #0 1692; CHECK-NEXT: movlt r1, #0 1693; CHECK-NEXT: movlt r2, #0 1694; CHECK-NEXT: vcmp.f32 s16, s20 1695; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1696; CHECK-NEXT: it gt 1697; CHECK-NEXT: movgt.w r2, #-1 1698; CHECK-NEXT: str r2, [r4, #8] 1699; CHECK-NEXT: it gt 1700; CHECK-NEXT: movgt.w r1, #-1 1701; CHECK-NEXT: str r1, [r4, #4] 1702; CHECK-NEXT: it gt 1703; CHECK-NEXT: movgt.w r0, #-1 1704; CHECK-NEXT: str r0, [r4] 1705; CHECK-NEXT: mov r0, r7 1706; CHECK-NEXT: lsrl r0, r9, #28 1707; CHECK-NEXT: and r1, r11, #15 1708; CHECK-NEXT: str.w r0, [r4, #41] 1709; CHECK-NEXT: mov r0, r10 1710; CHECK-NEXT: lsrl r0, r5, #28 1711; CHECK-NEXT: str r0, [r4, #16] 1712; CHECK-NEXT: orr.w r0, r9, r8, lsl #4 1713; CHECK-NEXT: lsrl r8, r1, #28 1714; CHECK-NEXT: str.w r0, [r4, #45] 1715; CHECK-NEXT: strb.w r8, [r4, #49] 1716; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload 1717; CHECK-NEXT: and r0, r0, #15 1718; CHECK-NEXT: orr.w r0, r0, r7, lsl #4 1719; CHECK-NEXT: str.w r0, [r4, #37] 1720; CHECK-NEXT: orr.w r0, r5, r6, lsl #4 1721; CHECK-NEXT: str r0, [r4, #20] 1722; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload 1723; CHECK-NEXT: and r1, r0, #15 1724; CHECK-NEXT: lsrl r6, r1, #28 1725; CHECK-NEXT: strb r6, [r4, #24] 1726; CHECK-NEXT: it gt 1727; CHECK-NEXT: movgt r3, #15 1728; CHECK-NEXT: and r0, r3, #15 1729; CHECK-NEXT: orr.w r0, r0, r10, lsl #4 1730; CHECK-NEXT: str r0, [r4, #12] 1731; CHECK-NEXT: add sp, #8 1732; CHECK-NEXT: vpop {d8, d9, d10} 1733; CHECK-NEXT: add sp, #4 1734; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 1735; CHECK-NEXT: .p2align 2 1736; CHECK-NEXT: @ %bb.1: 1737; CHECK-NEXT: .LCPI30_0: 1738; CHECK-NEXT: .long 0x717fffff @ float 1.26765052E+30 1739 %x = call <4 x i100> @llvm.fptoui.sat.v4f32.v4i100(<4 x float> %f) 1740 ret <4 x i100> %x 1741} 1742 1743define arm_aapcs_vfpcc <4 x i128> @test_unsigned_v4f32_v4i128(<4 x float> %f) { 1744; CHECK-LABEL: test_unsigned_v4f32_v4i128: 1745; CHECK: @ %bb.0: 1746; CHECK-NEXT: .save {r4, r5, r6, r7, lr} 1747; CHECK-NEXT: push {r4, r5, r6, r7, lr} 1748; CHECK-NEXT: .pad #4 1749; CHECK-NEXT: sub sp, #4 1750; CHECK-NEXT: .vsave {d8, d9, d10} 1751; CHECK-NEXT: vpush {d8, d9, d10} 1752; CHECK-NEXT: vmov q4, q0 1753; CHECK-NEXT: mov r4, r0 1754; CHECK-NEXT: vmov r0, s19 1755; CHECK-NEXT: bl __fixunssfti 1756; CHECK-NEXT: vmov r5, s18 1757; CHECK-NEXT: vldr s20, .LCPI31_0 1758; CHECK-NEXT: vcmp.f32 s19, #0 1759; CHECK-NEXT: add.w r12, r4, #48 1760; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1761; CHECK-NEXT: itttt lt 1762; CHECK-NEXT: movlt r0, #0 1763; CHECK-NEXT: movlt r1, #0 1764; CHECK-NEXT: movlt r2, #0 1765; CHECK-NEXT: movlt r3, #0 1766; CHECK-NEXT: vcmp.f32 s19, s20 1767; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1768; CHECK-NEXT: it gt 1769; CHECK-NEXT: movgt.w r3, #-1 1770; CHECK-NEXT: ittt gt 1771; CHECK-NEXT: movgt.w r2, #-1 1772; CHECK-NEXT: movgt.w r1, #-1 1773; CHECK-NEXT: movgt.w r0, #-1 1774; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3} 1775; CHECK-NEXT: vmov r7, s16 1776; CHECK-NEXT: vmov r6, s17 1777; CHECK-NEXT: mov r0, r5 1778; CHECK-NEXT: bl __fixunssfti 1779; CHECK-NEXT: vcmp.f32 s18, #0 1780; CHECK-NEXT: add.w r12, r4, #32 1781; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1782; CHECK-NEXT: itttt lt 1783; CHECK-NEXT: movlt r0, #0 1784; CHECK-NEXT: movlt r1, #0 1785; CHECK-NEXT: movlt r2, #0 1786; CHECK-NEXT: movlt r3, #0 1787; CHECK-NEXT: vcmp.f32 s18, s20 1788; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1789; CHECK-NEXT: itttt gt 1790; CHECK-NEXT: movgt.w r3, #-1 1791; CHECK-NEXT: movgt.w r2, #-1 1792; CHECK-NEXT: movgt.w r1, #-1 1793; CHECK-NEXT: movgt.w r0, #-1 1794; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3} 1795; CHECK-NEXT: mov r0, r6 1796; CHECK-NEXT: bl __fixunssfti 1797; CHECK-NEXT: vcmp.f32 s17, #0 1798; CHECK-NEXT: add.w r12, r4, #16 1799; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1800; CHECK-NEXT: itttt lt 1801; CHECK-NEXT: movlt r0, #0 1802; CHECK-NEXT: movlt r1, #0 1803; CHECK-NEXT: movlt r2, #0 1804; CHECK-NEXT: movlt r3, #0 1805; CHECK-NEXT: vcmp.f32 s17, s20 1806; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1807; CHECK-NEXT: itttt gt 1808; CHECK-NEXT: movgt.w r3, #-1 1809; CHECK-NEXT: movgt.w r2, #-1 1810; CHECK-NEXT: movgt.w r1, #-1 1811; CHECK-NEXT: movgt.w r0, #-1 1812; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3} 1813; CHECK-NEXT: mov r0, r7 1814; CHECK-NEXT: bl __fixunssfti 1815; CHECK-NEXT: vcmp.f32 s16, #0 1816; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1817; CHECK-NEXT: itttt lt 1818; CHECK-NEXT: movlt r0, #0 1819; CHECK-NEXT: movlt r1, #0 1820; CHECK-NEXT: movlt r2, #0 1821; CHECK-NEXT: movlt r3, #0 1822; CHECK-NEXT: vcmp.f32 s16, s20 1823; CHECK-NEXT: vmrs APSR_nzcv, fpscr 1824; CHECK-NEXT: itttt gt 1825; CHECK-NEXT: movgt.w r3, #-1 1826; CHECK-NEXT: movgt.w r2, #-1 1827; CHECK-NEXT: movgt.w r1, #-1 1828; CHECK-NEXT: movgt.w r0, #-1 1829; CHECK-NEXT: stm r4!, {r0, r1, r2, r3} 1830; CHECK-NEXT: vpop {d8, d9, d10} 1831; CHECK-NEXT: add sp, #4 1832; CHECK-NEXT: pop {r4, r5, r6, r7, pc} 1833; CHECK-NEXT: .p2align 2 1834; CHECK-NEXT: @ %bb.1: 1835; CHECK-NEXT: .LCPI31_0: 1836; CHECK-NEXT: .long 0x7f7fffff @ float 3.40282347E+38 1837 %x = call <4 x i128> @llvm.fptoui.sat.v4f32.v4i128(<4 x float> %f) 1838 ret <4 x i128> %x 1839} 1840 1841; 1842; 2-Vector double to signed integer -- result size variation 1843; 1844 1845declare <2 x i1> @llvm.fptoui.sat.v2f64.v2i1 (<2 x double>) 1846declare <2 x i8> @llvm.fptoui.sat.v2f64.v2i8 (<2 x double>) 1847declare <2 x i13> @llvm.fptoui.sat.v2f64.v2i13 (<2 x double>) 1848declare <2 x i16> @llvm.fptoui.sat.v2f64.v2i16 (<2 x double>) 1849declare <2 x i19> @llvm.fptoui.sat.v2f64.v2i19 (<2 x double>) 1850declare <2 x i50> @llvm.fptoui.sat.v2f64.v2i50 (<2 x double>) 1851declare <2 x i64> @llvm.fptoui.sat.v2f64.v2i64 (<2 x double>) 1852declare <2 x i100> @llvm.fptoui.sat.v2f64.v2i100(<2 x double>) 1853declare <2 x i128> @llvm.fptoui.sat.v2f64.v2i128(<2 x double>) 1854 1855define arm_aapcs_vfpcc <2 x i1> @test_unsigned_v2f64_v2i1(<2 x double> %f) { 1856; CHECK-LABEL: test_unsigned_v2f64_v2i1: 1857; CHECK: @ %bb.0: 1858; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 1859; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 1860; CHECK-NEXT: .pad #4 1861; CHECK-NEXT: sub sp, #4 1862; CHECK-NEXT: .vsave {d8, d9} 1863; CHECK-NEXT: vpush {d8, d9} 1864; CHECK-NEXT: .pad #8 1865; CHECK-NEXT: sub sp, #8 1866; CHECK-NEXT: vmov q4, q0 1867; CHECK-NEXT: vldr d0, .LCPI32_0 1868; CHECK-NEXT: vmov r4, r8, d8 1869; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill 1870; CHECK-NEXT: vmov r10, r3, d0 1871; CHECK-NEXT: str r3, [sp] @ 4-byte Spill 1872; CHECK-NEXT: mov r0, r4 1873; CHECK-NEXT: mov r1, r8 1874; CHECK-NEXT: mov r2, r10 1875; CHECK-NEXT: bl __aeabi_dcmpge 1876; CHECK-NEXT: mov r9, r0 1877; CHECK-NEXT: mov r0, r4 1878; CHECK-NEXT: mov r1, r8 1879; CHECK-NEXT: bl __aeabi_d2uiz 1880; CHECK-NEXT: vldr d0, .LCPI32_1 1881; CHECK-NEXT: cmp.w r9, #0 1882; CHECK-NEXT: csel r7, r0, r9, ne 1883; CHECK-NEXT: mov r0, r4 1884; CHECK-NEXT: vmov r11, r3, d0 1885; CHECK-NEXT: mov r1, r8 1886; CHECK-NEXT: vmov r6, r5, d9 1887; CHECK-NEXT: mov r2, r11 1888; CHECK-NEXT: mov r8, r3 1889; CHECK-NEXT: bl __aeabi_dcmpgt 1890; CHECK-NEXT: cmp r0, #0 1891; CHECK-NEXT: it ne 1892; CHECK-NEXT: movne r7, #1 1893; CHECK-NEXT: and r0, r7, #1 1894; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload 1895; CHECK-NEXT: rsbs r0, r0, #0 1896; CHECK-NEXT: movs r7, #0 1897; CHECK-NEXT: bfi r7, r0, #0, #1 1898; CHECK-NEXT: mov r0, r6 1899; CHECK-NEXT: mov r1, r5 1900; CHECK-NEXT: mov r2, r10 1901; CHECK-NEXT: bl __aeabi_dcmpge 1902; CHECK-NEXT: mov r4, r0 1903; CHECK-NEXT: mov r0, r6 1904; CHECK-NEXT: mov r1, r5 1905; CHECK-NEXT: bl __aeabi_d2uiz 1906; CHECK-NEXT: cmp r4, #0 1907; CHECK-NEXT: mov r1, r5 1908; CHECK-NEXT: csel r4, r0, r4, ne 1909; CHECK-NEXT: mov r0, r6 1910; CHECK-NEXT: mov r2, r11 1911; CHECK-NEXT: mov r3, r8 1912; CHECK-NEXT: bl __aeabi_dcmpgt 1913; CHECK-NEXT: cmp r0, #0 1914; CHECK-NEXT: it ne 1915; CHECK-NEXT: movne r4, #1 1916; CHECK-NEXT: and r0, r4, #1 1917; CHECK-NEXT: rsbs r0, r0, #0 1918; CHECK-NEXT: bfi r7, r0, #1, #1 1919; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload 1920; CHECK-NEXT: strb r7, [r0] 1921; CHECK-NEXT: add sp, #8 1922; CHECK-NEXT: vpop {d8, d9} 1923; CHECK-NEXT: add sp, #4 1924; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 1925; CHECK-NEXT: .p2align 3 1926; CHECK-NEXT: @ %bb.1: 1927; CHECK-NEXT: .LCPI32_0: 1928; CHECK-NEXT: .long 0 @ double 0 1929; CHECK-NEXT: .long 0 1930; CHECK-NEXT: .LCPI32_1: 1931; CHECK-NEXT: .long 0 @ double 1 1932; CHECK-NEXT: .long 1072693248 1933 %x = call <2 x i1> @llvm.fptoui.sat.v2f64.v2i1(<2 x double> %f) 1934 ret <2 x i1> %x 1935} 1936 1937define arm_aapcs_vfpcc <2 x i8> @test_unsigned_v2f64_v2i8(<2 x double> %f) { 1938; CHECK-LABEL: test_unsigned_v2f64_v2i8: 1939; CHECK: @ %bb.0: 1940; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 1941; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 1942; CHECK-NEXT: .pad #4 1943; CHECK-NEXT: sub sp, #4 1944; CHECK-NEXT: .vsave {d8, d9} 1945; CHECK-NEXT: vpush {d8, d9} 1946; CHECK-NEXT: .pad #8 1947; CHECK-NEXT: sub sp, #8 1948; CHECK-NEXT: vmov q4, q0 1949; CHECK-NEXT: vldr d0, .LCPI33_0 1950; CHECK-NEXT: vmov r6, r7, d9 1951; CHECK-NEXT: vmov r11, r3, d0 1952; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill 1953; CHECK-NEXT: mov r0, r6 1954; CHECK-NEXT: mov r1, r7 1955; CHECK-NEXT: mov r2, r11 1956; CHECK-NEXT: bl __aeabi_dcmpge 1957; CHECK-NEXT: mov r8, r0 1958; CHECK-NEXT: mov r0, r6 1959; CHECK-NEXT: mov r1, r7 1960; CHECK-NEXT: bl __aeabi_d2ulz 1961; CHECK-NEXT: vldr d0, .LCPI33_1 1962; CHECK-NEXT: cmp.w r8, #0 1963; CHECK-NEXT: csel r9, r0, r8, ne 1964; CHECK-NEXT: csel r8, r1, r8, ne 1965; CHECK-NEXT: vmov r10, r3, d0 1966; CHECK-NEXT: mov r0, r6 1967; CHECK-NEXT: mov r1, r7 1968; CHECK-NEXT: vmov r5, r4, d8 1969; CHECK-NEXT: str r3, [sp] @ 4-byte Spill 1970; CHECK-NEXT: mov r2, r10 1971; CHECK-NEXT: bl __aeabi_dcmpgt 1972; CHECK-NEXT: cmp r0, #0 1973; CHECK-NEXT: itt ne 1974; CHECK-NEXT: movne.w r8, #0 1975; CHECK-NEXT: movne.w r9, #255 1976; CHECK-NEXT: ldr r3, [sp, #4] @ 4-byte Reload 1977; CHECK-NEXT: mov r0, r5 1978; CHECK-NEXT: mov r1, r4 1979; CHECK-NEXT: mov r2, r11 1980; CHECK-NEXT: bl __aeabi_dcmpge 1981; CHECK-NEXT: mov r6, r0 1982; CHECK-NEXT: mov r0, r5 1983; CHECK-NEXT: mov r1, r4 1984; CHECK-NEXT: bl __aeabi_d2ulz 1985; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload 1986; CHECK-NEXT: cmp r6, #0 1987; CHECK-NEXT: csel r7, r1, r6, ne 1988; CHECK-NEXT: csel r6, r0, r6, ne 1989; CHECK-NEXT: mov r0, r5 1990; CHECK-NEXT: mov r1, r4 1991; CHECK-NEXT: mov r2, r10 1992; CHECK-NEXT: bl __aeabi_dcmpgt 1993; CHECK-NEXT: cmp r0, #0 1994; CHECK-NEXT: itt ne 1995; CHECK-NEXT: movne r6, #255 1996; CHECK-NEXT: movne r7, #0 1997; CHECK-NEXT: vmov q0[2], q0[0], r6, r9 1998; CHECK-NEXT: vmov q0[3], q0[1], r7, r8 1999; CHECK-NEXT: add sp, #8 2000; CHECK-NEXT: vpop {d8, d9} 2001; CHECK-NEXT: add sp, #4 2002; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 2003; CHECK-NEXT: .p2align 3 2004; CHECK-NEXT: @ %bb.1: 2005; CHECK-NEXT: .LCPI33_0: 2006; CHECK-NEXT: .long 0 @ double 0 2007; CHECK-NEXT: .long 0 2008; CHECK-NEXT: .LCPI33_1: 2009; CHECK-NEXT: .long 0 @ double 255 2010; CHECK-NEXT: .long 1081073664 2011 %x = call <2 x i8> @llvm.fptoui.sat.v2f64.v2i8(<2 x double> %f) 2012 ret <2 x i8> %x 2013} 2014 2015define arm_aapcs_vfpcc <2 x i13> @test_unsigned_v2f64_v2i13(<2 x double> %f) { 2016; CHECK-LABEL: test_unsigned_v2f64_v2i13: 2017; CHECK: @ %bb.0: 2018; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2019; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2020; CHECK-NEXT: .pad #4 2021; CHECK-NEXT: sub sp, #4 2022; CHECK-NEXT: .vsave {d8, d9} 2023; CHECK-NEXT: vpush {d8, d9} 2024; CHECK-NEXT: .pad #8 2025; CHECK-NEXT: sub sp, #8 2026; CHECK-NEXT: vmov q4, q0 2027; CHECK-NEXT: vldr d0, .LCPI34_0 2028; CHECK-NEXT: vmov r6, r7, d9 2029; CHECK-NEXT: vmov r11, r3, d0 2030; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill 2031; CHECK-NEXT: mov r0, r6 2032; CHECK-NEXT: mov r1, r7 2033; CHECK-NEXT: mov r2, r11 2034; CHECK-NEXT: bl __aeabi_dcmpge 2035; CHECK-NEXT: mov r8, r0 2036; CHECK-NEXT: mov r0, r6 2037; CHECK-NEXT: mov r1, r7 2038; CHECK-NEXT: bl __aeabi_d2ulz 2039; CHECK-NEXT: vldr d0, .LCPI34_1 2040; CHECK-NEXT: cmp.w r8, #0 2041; CHECK-NEXT: csel r9, r0, r8, ne 2042; CHECK-NEXT: csel r8, r1, r8, ne 2043; CHECK-NEXT: vmov r10, r3, d0 2044; CHECK-NEXT: mov r0, r6 2045; CHECK-NEXT: mov r1, r7 2046; CHECK-NEXT: vmov r5, r4, d8 2047; CHECK-NEXT: str r3, [sp] @ 4-byte Spill 2048; CHECK-NEXT: mov r2, r10 2049; CHECK-NEXT: bl __aeabi_dcmpgt 2050; CHECK-NEXT: cmp r0, #0 2051; CHECK-NEXT: itt ne 2052; CHECK-NEXT: movne.w r8, #0 2053; CHECK-NEXT: movwne r9, #8191 2054; CHECK-NEXT: ldr r3, [sp, #4] @ 4-byte Reload 2055; CHECK-NEXT: mov r0, r5 2056; CHECK-NEXT: mov r1, r4 2057; CHECK-NEXT: mov r2, r11 2058; CHECK-NEXT: bl __aeabi_dcmpge 2059; CHECK-NEXT: mov r6, r0 2060; CHECK-NEXT: mov r0, r5 2061; CHECK-NEXT: mov r1, r4 2062; CHECK-NEXT: bl __aeabi_d2ulz 2063; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload 2064; CHECK-NEXT: cmp r6, #0 2065; CHECK-NEXT: csel r7, r1, r6, ne 2066; CHECK-NEXT: csel r6, r0, r6, ne 2067; CHECK-NEXT: mov r0, r5 2068; CHECK-NEXT: mov r1, r4 2069; CHECK-NEXT: mov r2, r10 2070; CHECK-NEXT: bl __aeabi_dcmpgt 2071; CHECK-NEXT: cmp r0, #0 2072; CHECK-NEXT: itt ne 2073; CHECK-NEXT: movwne r6, #8191 2074; CHECK-NEXT: movne r7, #0 2075; CHECK-NEXT: vmov q0[2], q0[0], r6, r9 2076; CHECK-NEXT: vmov q0[3], q0[1], r7, r8 2077; CHECK-NEXT: add sp, #8 2078; CHECK-NEXT: vpop {d8, d9} 2079; CHECK-NEXT: add sp, #4 2080; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 2081; CHECK-NEXT: .p2align 3 2082; CHECK-NEXT: @ %bb.1: 2083; CHECK-NEXT: .LCPI34_0: 2084; CHECK-NEXT: .long 0 @ double 0 2085; CHECK-NEXT: .long 0 2086; CHECK-NEXT: .LCPI34_1: 2087; CHECK-NEXT: .long 0 @ double 8191 2088; CHECK-NEXT: .long 1086324480 2089 %x = call <2 x i13> @llvm.fptoui.sat.v2f64.v2i13(<2 x double> %f) 2090 ret <2 x i13> %x 2091} 2092 2093define arm_aapcs_vfpcc <2 x i16> @test_unsigned_v2f64_v2i16(<2 x double> %f) { 2094; CHECK-LABEL: test_unsigned_v2f64_v2i16: 2095; CHECK: @ %bb.0: 2096; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2097; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2098; CHECK-NEXT: .pad #4 2099; CHECK-NEXT: sub sp, #4 2100; CHECK-NEXT: .vsave {d8, d9} 2101; CHECK-NEXT: vpush {d8, d9} 2102; CHECK-NEXT: .pad #8 2103; CHECK-NEXT: sub sp, #8 2104; CHECK-NEXT: vmov q4, q0 2105; CHECK-NEXT: vldr d0, .LCPI35_0 2106; CHECK-NEXT: vmov r6, r7, d9 2107; CHECK-NEXT: vmov r11, r3, d0 2108; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill 2109; CHECK-NEXT: mov r0, r6 2110; CHECK-NEXT: mov r1, r7 2111; CHECK-NEXT: mov r2, r11 2112; CHECK-NEXT: bl __aeabi_dcmpge 2113; CHECK-NEXT: mov r8, r0 2114; CHECK-NEXT: mov r0, r6 2115; CHECK-NEXT: mov r1, r7 2116; CHECK-NEXT: bl __aeabi_d2ulz 2117; CHECK-NEXT: vldr d0, .LCPI35_1 2118; CHECK-NEXT: cmp.w r8, #0 2119; CHECK-NEXT: csel r9, r0, r8, ne 2120; CHECK-NEXT: csel r8, r1, r8, ne 2121; CHECK-NEXT: vmov r10, r3, d0 2122; CHECK-NEXT: mov r0, r6 2123; CHECK-NEXT: mov r1, r7 2124; CHECK-NEXT: vmov r5, r4, d8 2125; CHECK-NEXT: str r3, [sp] @ 4-byte Spill 2126; CHECK-NEXT: mov r2, r10 2127; CHECK-NEXT: bl __aeabi_dcmpgt 2128; CHECK-NEXT: cmp r0, #0 2129; CHECK-NEXT: itt ne 2130; CHECK-NEXT: movne.w r8, #0 2131; CHECK-NEXT: movwne r9, #65535 2132; CHECK-NEXT: ldr r3, [sp, #4] @ 4-byte Reload 2133; CHECK-NEXT: mov r0, r5 2134; CHECK-NEXT: mov r1, r4 2135; CHECK-NEXT: mov r2, r11 2136; CHECK-NEXT: bl __aeabi_dcmpge 2137; CHECK-NEXT: mov r6, r0 2138; CHECK-NEXT: mov r0, r5 2139; CHECK-NEXT: mov r1, r4 2140; CHECK-NEXT: bl __aeabi_d2ulz 2141; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload 2142; CHECK-NEXT: cmp r6, #0 2143; CHECK-NEXT: csel r7, r1, r6, ne 2144; CHECK-NEXT: csel r6, r0, r6, ne 2145; CHECK-NEXT: mov r0, r5 2146; CHECK-NEXT: mov r1, r4 2147; CHECK-NEXT: mov r2, r10 2148; CHECK-NEXT: bl __aeabi_dcmpgt 2149; CHECK-NEXT: cmp r0, #0 2150; CHECK-NEXT: itt ne 2151; CHECK-NEXT: movwne r6, #65535 2152; CHECK-NEXT: movne r7, #0 2153; CHECK-NEXT: vmov q0[2], q0[0], r6, r9 2154; CHECK-NEXT: vmov q0[3], q0[1], r7, r8 2155; CHECK-NEXT: add sp, #8 2156; CHECK-NEXT: vpop {d8, d9} 2157; CHECK-NEXT: add sp, #4 2158; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 2159; CHECK-NEXT: .p2align 3 2160; CHECK-NEXT: @ %bb.1: 2161; CHECK-NEXT: .LCPI35_0: 2162; CHECK-NEXT: .long 0 @ double 0 2163; CHECK-NEXT: .long 0 2164; CHECK-NEXT: .LCPI35_1: 2165; CHECK-NEXT: .long 0 @ double 65535 2166; CHECK-NEXT: .long 1089470432 2167 %x = call <2 x i16> @llvm.fptoui.sat.v2f64.v2i16(<2 x double> %f) 2168 ret <2 x i16> %x 2169} 2170 2171define arm_aapcs_vfpcc <2 x i19> @test_unsigned_v2f64_v2i19(<2 x double> %f) { 2172; CHECK-LABEL: test_unsigned_v2f64_v2i19: 2173; CHECK: @ %bb.0: 2174; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2175; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2176; CHECK-NEXT: .pad #4 2177; CHECK-NEXT: sub sp, #4 2178; CHECK-NEXT: .vsave {d8, d9} 2179; CHECK-NEXT: vpush {d8, d9} 2180; CHECK-NEXT: .pad #16 2181; CHECK-NEXT: sub sp, #16 2182; CHECK-NEXT: vmov q4, q0 2183; CHECK-NEXT: vldr d0, .LCPI36_0 2184; CHECK-NEXT: vmov r11, r5, d8 2185; CHECK-NEXT: vmov r6, r7, d0 2186; CHECK-NEXT: str r5, [sp, #12] @ 4-byte Spill 2187; CHECK-NEXT: mov r0, r11 2188; CHECK-NEXT: mov r1, r5 2189; CHECK-NEXT: mov r2, r6 2190; CHECK-NEXT: mov r3, r7 2191; CHECK-NEXT: bl __aeabi_dcmpge 2192; CHECK-NEXT: mov r4, r0 2193; CHECK-NEXT: mov r0, r11 2194; CHECK-NEXT: mov r1, r5 2195; CHECK-NEXT: bl __aeabi_d2ulz 2196; CHECK-NEXT: vldr d0, .LCPI36_1 2197; CHECK-NEXT: vmov r5, r8, d9 2198; CHECK-NEXT: cmp r4, #0 2199; CHECK-NEXT: vmov r3, r2, d0 2200; CHECK-NEXT: csel r9, r1, r4, ne 2201; CHECK-NEXT: csel r10, r0, r4, ne 2202; CHECK-NEXT: mov r0, r5 2203; CHECK-NEXT: mov r1, r8 2204; CHECK-NEXT: strd r3, r2, [sp, #4] @ 8-byte Folded Spill 2205; CHECK-NEXT: mov r2, r6 2206; CHECK-NEXT: mov r3, r7 2207; CHECK-NEXT: bl __aeabi_dcmpge 2208; CHECK-NEXT: mov r4, r0 2209; CHECK-NEXT: mov r0, r5 2210; CHECK-NEXT: mov r1, r8 2211; CHECK-NEXT: bl __aeabi_d2ulz 2212; CHECK-NEXT: cmp r4, #0 2213; CHECK-NEXT: ldr r7, [sp, #4] @ 4-byte Reload 2214; CHECK-NEXT: csel r6, r0, r4, ne 2215; CHECK-NEXT: mov r0, r5 2216; CHECK-NEXT: ldr r5, [sp, #8] @ 4-byte Reload 2217; CHECK-NEXT: csel r4, r1, r4, ne 2218; CHECK-NEXT: mov r1, r8 2219; CHECK-NEXT: mov r2, r7 2220; CHECK-NEXT: mov r3, r5 2221; CHECK-NEXT: bl __aeabi_dcmpgt 2222; CHECK-NEXT: cmp r0, #0 2223; CHECK-NEXT: ittt ne 2224; CHECK-NEXT: movne r4, #0 2225; CHECK-NEXT: movwne r6, #65535 2226; CHECK-NEXT: movtne r6, #7 2227; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload 2228; CHECK-NEXT: mov r0, r11 2229; CHECK-NEXT: mov r2, r7 2230; CHECK-NEXT: mov r3, r5 2231; CHECK-NEXT: bl __aeabi_dcmpgt 2232; CHECK-NEXT: cmp r0, #0 2233; CHECK-NEXT: ittt ne 2234; CHECK-NEXT: movwne r10, #65535 2235; CHECK-NEXT: movtne r10, #7 2236; CHECK-NEXT: movne.w r9, #0 2237; CHECK-NEXT: vmov q0[2], q0[0], r10, r6 2238; CHECK-NEXT: vmov q0[3], q0[1], r9, r4 2239; CHECK-NEXT: add sp, #16 2240; CHECK-NEXT: vpop {d8, d9} 2241; CHECK-NEXT: add sp, #4 2242; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 2243; CHECK-NEXT: .p2align 3 2244; CHECK-NEXT: @ %bb.1: 2245; CHECK-NEXT: .LCPI36_0: 2246; CHECK-NEXT: .long 0 @ double 0 2247; CHECK-NEXT: .long 0 2248; CHECK-NEXT: .LCPI36_1: 2249; CHECK-NEXT: .long 0 @ double 524287 2250; CHECK-NEXT: .long 1092616188 2251 %x = call <2 x i19> @llvm.fptoui.sat.v2f64.v2i19(<2 x double> %f) 2252 ret <2 x i19> %x 2253} 2254 2255define arm_aapcs_vfpcc <2 x i32> @test_unsigned_v2f64_v2i32_duplicate(<2 x double> %f) { 2256; CHECK-LABEL: test_unsigned_v2f64_v2i32_duplicate: 2257; CHECK: @ %bb.0: 2258; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2259; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2260; CHECK-NEXT: .pad #4 2261; CHECK-NEXT: sub sp, #4 2262; CHECK-NEXT: .vsave {d8, d9} 2263; CHECK-NEXT: vpush {d8, d9} 2264; CHECK-NEXT: .pad #8 2265; CHECK-NEXT: sub sp, #8 2266; CHECK-NEXT: vmov q4, q0 2267; CHECK-NEXT: vldr d0, .LCPI37_0 2268; CHECK-NEXT: vmov r6, r7, d9 2269; CHECK-NEXT: vmov r11, r3, d0 2270; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill 2271; CHECK-NEXT: mov r0, r6 2272; CHECK-NEXT: mov r1, r7 2273; CHECK-NEXT: mov r2, r11 2274; CHECK-NEXT: bl __aeabi_dcmpge 2275; CHECK-NEXT: mov r8, r0 2276; CHECK-NEXT: mov r0, r6 2277; CHECK-NEXT: mov r1, r7 2278; CHECK-NEXT: bl __aeabi_d2ulz 2279; CHECK-NEXT: vldr d0, .LCPI37_1 2280; CHECK-NEXT: cmp.w r8, #0 2281; CHECK-NEXT: csel r9, r0, r8, ne 2282; CHECK-NEXT: csel r8, r1, r8, ne 2283; CHECK-NEXT: vmov r10, r3, d0 2284; CHECK-NEXT: mov r0, r6 2285; CHECK-NEXT: mov r1, r7 2286; CHECK-NEXT: vmov r5, r4, d8 2287; CHECK-NEXT: str r3, [sp] @ 4-byte Spill 2288; CHECK-NEXT: mov r2, r10 2289; CHECK-NEXT: bl __aeabi_dcmpgt 2290; CHECK-NEXT: cmp r0, #0 2291; CHECK-NEXT: itt ne 2292; CHECK-NEXT: movne.w r8, #0 2293; CHECK-NEXT: movne.w r9, #-1 2294; CHECK-NEXT: ldr r3, [sp, #4] @ 4-byte Reload 2295; CHECK-NEXT: mov r0, r5 2296; CHECK-NEXT: mov r1, r4 2297; CHECK-NEXT: mov r2, r11 2298; CHECK-NEXT: bl __aeabi_dcmpge 2299; CHECK-NEXT: mov r6, r0 2300; CHECK-NEXT: mov r0, r5 2301; CHECK-NEXT: mov r1, r4 2302; CHECK-NEXT: bl __aeabi_d2ulz 2303; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload 2304; CHECK-NEXT: cmp r6, #0 2305; CHECK-NEXT: csel r7, r1, r6, ne 2306; CHECK-NEXT: csel r6, r0, r6, ne 2307; CHECK-NEXT: mov r0, r5 2308; CHECK-NEXT: mov r1, r4 2309; CHECK-NEXT: mov r2, r10 2310; CHECK-NEXT: bl __aeabi_dcmpgt 2311; CHECK-NEXT: cmp r0, #0 2312; CHECK-NEXT: itt ne 2313; CHECK-NEXT: movne.w r6, #-1 2314; CHECK-NEXT: movne r7, #0 2315; CHECK-NEXT: vmov q0[2], q0[0], r6, r9 2316; CHECK-NEXT: vmov q0[3], q0[1], r7, r8 2317; CHECK-NEXT: add sp, #8 2318; CHECK-NEXT: vpop {d8, d9} 2319; CHECK-NEXT: add sp, #4 2320; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 2321; CHECK-NEXT: .p2align 3 2322; CHECK-NEXT: @ %bb.1: 2323; CHECK-NEXT: .LCPI37_0: 2324; CHECK-NEXT: .long 0 @ double 0 2325; CHECK-NEXT: .long 0 2326; CHECK-NEXT: .LCPI37_1: 2327; CHECK-NEXT: .long 4292870144 @ double 4294967295 2328; CHECK-NEXT: .long 1106247679 2329 %x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f) 2330 ret <2 x i32> %x 2331} 2332 2333define arm_aapcs_vfpcc <2 x i50> @test_unsigned_v2f64_v2i50(<2 x double> %f) { 2334; CHECK-LABEL: test_unsigned_v2f64_v2i50: 2335; CHECK: @ %bb.0: 2336; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2337; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2338; CHECK-NEXT: .pad #4 2339; CHECK-NEXT: sub sp, #4 2340; CHECK-NEXT: .vsave {d8, d9} 2341; CHECK-NEXT: vpush {d8, d9} 2342; CHECK-NEXT: .pad #16 2343; CHECK-NEXT: sub sp, #16 2344; CHECK-NEXT: vmov q4, q0 2345; CHECK-NEXT: vldr d0, .LCPI38_0 2346; CHECK-NEXT: vmov r11, r5, d8 2347; CHECK-NEXT: vmov r6, r7, d0 2348; CHECK-NEXT: str r5, [sp, #12] @ 4-byte Spill 2349; CHECK-NEXT: mov r0, r11 2350; CHECK-NEXT: mov r1, r5 2351; CHECK-NEXT: mov r2, r6 2352; CHECK-NEXT: mov r3, r7 2353; CHECK-NEXT: bl __aeabi_dcmpge 2354; CHECK-NEXT: mov r4, r0 2355; CHECK-NEXT: mov r0, r11 2356; CHECK-NEXT: mov r1, r5 2357; CHECK-NEXT: bl __aeabi_d2ulz 2358; CHECK-NEXT: vldr d0, .LCPI38_1 2359; CHECK-NEXT: vmov r5, r8, d9 2360; CHECK-NEXT: cmp r4, #0 2361; CHECK-NEXT: vmov r3, r2, d0 2362; CHECK-NEXT: csel r10, r0, r4, ne 2363; CHECK-NEXT: csel r9, r1, r4, ne 2364; CHECK-NEXT: mov r0, r5 2365; CHECK-NEXT: mov r1, r8 2366; CHECK-NEXT: strd r3, r2, [sp, #4] @ 8-byte Folded Spill 2367; CHECK-NEXT: mov r2, r6 2368; CHECK-NEXT: mov r3, r7 2369; CHECK-NEXT: bl __aeabi_dcmpge 2370; CHECK-NEXT: mov r4, r0 2371; CHECK-NEXT: mov r0, r5 2372; CHECK-NEXT: mov r1, r8 2373; CHECK-NEXT: bl __aeabi_d2ulz 2374; CHECK-NEXT: cmp r4, #0 2375; CHECK-NEXT: ldr r7, [sp, #4] @ 4-byte Reload 2376; CHECK-NEXT: csel r6, r1, r4, ne 2377; CHECK-NEXT: csel r4, r0, r4, ne 2378; CHECK-NEXT: mov r0, r5 2379; CHECK-NEXT: ldr r5, [sp, #8] @ 4-byte Reload 2380; CHECK-NEXT: mov r1, r8 2381; CHECK-NEXT: mov r2, r7 2382; CHECK-NEXT: mov r3, r5 2383; CHECK-NEXT: bl __aeabi_dcmpgt 2384; CHECK-NEXT: cmp r0, #0 2385; CHECK-NEXT: ittt ne 2386; CHECK-NEXT: movne.w r4, #-1 2387; CHECK-NEXT: movwne r6, #65535 2388; CHECK-NEXT: movtne r6, #3 2389; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload 2390; CHECK-NEXT: mov r0, r11 2391; CHECK-NEXT: mov r2, r7 2392; CHECK-NEXT: mov r3, r5 2393; CHECK-NEXT: bl __aeabi_dcmpgt 2394; CHECK-NEXT: cmp r0, #0 2395; CHECK-NEXT: ittt ne 2396; CHECK-NEXT: movwne r9, #65535 2397; CHECK-NEXT: movtne r9, #3 2398; CHECK-NEXT: movne.w r10, #-1 2399; CHECK-NEXT: vmov q0[2], q0[0], r10, r4 2400; CHECK-NEXT: vmov q0[3], q0[1], r9, r6 2401; CHECK-NEXT: add sp, #16 2402; CHECK-NEXT: vpop {d8, d9} 2403; CHECK-NEXT: add sp, #4 2404; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 2405; CHECK-NEXT: .p2align 3 2406; CHECK-NEXT: @ %bb.1: 2407; CHECK-NEXT: .LCPI38_0: 2408; CHECK-NEXT: .long 0 @ double 0 2409; CHECK-NEXT: .long 0 2410; CHECK-NEXT: .LCPI38_1: 2411; CHECK-NEXT: .long 4294967288 @ double 1125899906842623 2412; CHECK-NEXT: .long 1125122047 2413 %x = call <2 x i50> @llvm.fptoui.sat.v2f64.v2i50(<2 x double> %f) 2414 ret <2 x i50> %x 2415} 2416 2417define arm_aapcs_vfpcc <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) { 2418; CHECK-LABEL: test_unsigned_v2f64_v2i64: 2419; CHECK: @ %bb.0: 2420; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2421; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2422; CHECK-NEXT: .pad #4 2423; CHECK-NEXT: sub sp, #4 2424; CHECK-NEXT: .vsave {d8, d9} 2425; CHECK-NEXT: vpush {d8, d9} 2426; CHECK-NEXT: .pad #8 2427; CHECK-NEXT: sub sp, #8 2428; CHECK-NEXT: vmov q4, q0 2429; CHECK-NEXT: vldr d0, .LCPI39_0 2430; CHECK-NEXT: vmov r6, r7, d9 2431; CHECK-NEXT: vmov r11, r3, d0 2432; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill 2433; CHECK-NEXT: mov r0, r6 2434; CHECK-NEXT: mov r1, r7 2435; CHECK-NEXT: mov r2, r11 2436; CHECK-NEXT: bl __aeabi_dcmpge 2437; CHECK-NEXT: mov r8, r0 2438; CHECK-NEXT: mov r0, r6 2439; CHECK-NEXT: mov r1, r7 2440; CHECK-NEXT: bl __aeabi_d2ulz 2441; CHECK-NEXT: vldr d0, .LCPI39_1 2442; CHECK-NEXT: cmp.w r8, #0 2443; CHECK-NEXT: csel r9, r0, r8, ne 2444; CHECK-NEXT: csel r8, r1, r8, ne 2445; CHECK-NEXT: vmov r10, r3, d0 2446; CHECK-NEXT: mov r0, r6 2447; CHECK-NEXT: mov r1, r7 2448; CHECK-NEXT: vmov r5, r4, d8 2449; CHECK-NEXT: str r3, [sp] @ 4-byte Spill 2450; CHECK-NEXT: mov r2, r10 2451; CHECK-NEXT: bl __aeabi_dcmpgt 2452; CHECK-NEXT: cmp r0, #0 2453; CHECK-NEXT: itt ne 2454; CHECK-NEXT: movne.w r8, #-1 2455; CHECK-NEXT: movne.w r9, #-1 2456; CHECK-NEXT: ldr r3, [sp, #4] @ 4-byte Reload 2457; CHECK-NEXT: mov r0, r5 2458; CHECK-NEXT: mov r1, r4 2459; CHECK-NEXT: mov r2, r11 2460; CHECK-NEXT: bl __aeabi_dcmpge 2461; CHECK-NEXT: mov r6, r0 2462; CHECK-NEXT: mov r0, r5 2463; CHECK-NEXT: mov r1, r4 2464; CHECK-NEXT: bl __aeabi_d2ulz 2465; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload 2466; CHECK-NEXT: cmp r6, #0 2467; CHECK-NEXT: csel r7, r1, r6, ne 2468; CHECK-NEXT: csel r6, r0, r6, ne 2469; CHECK-NEXT: mov r0, r5 2470; CHECK-NEXT: mov r1, r4 2471; CHECK-NEXT: mov r2, r10 2472; CHECK-NEXT: bl __aeabi_dcmpgt 2473; CHECK-NEXT: cmp r0, #0 2474; CHECK-NEXT: itt ne 2475; CHECK-NEXT: movne.w r6, #-1 2476; CHECK-NEXT: movne.w r7, #-1 2477; CHECK-NEXT: vmov q0[2], q0[0], r6, r9 2478; CHECK-NEXT: vmov q0[3], q0[1], r7, r8 2479; CHECK-NEXT: add sp, #8 2480; CHECK-NEXT: vpop {d8, d9} 2481; CHECK-NEXT: add sp, #4 2482; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 2483; CHECK-NEXT: .p2align 3 2484; CHECK-NEXT: @ %bb.1: 2485; CHECK-NEXT: .LCPI39_0: 2486; CHECK-NEXT: .long 0 @ double 0 2487; CHECK-NEXT: .long 0 2488; CHECK-NEXT: .LCPI39_1: 2489; CHECK-NEXT: .long 4294967295 @ double 1.844674407370955E+19 2490; CHECK-NEXT: .long 1139802111 2491 %x = call <2 x i64> @llvm.fptoui.sat.v2f64.v2i64(<2 x double> %f) 2492 ret <2 x i64> %x 2493} 2494 2495define arm_aapcs_vfpcc <2 x i100> @test_unsigned_v2f64_v2i100(<2 x double> %f) { 2496; CHECK-LABEL: test_unsigned_v2f64_v2i100: 2497; CHECK: @ %bb.0: 2498; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2499; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2500; CHECK-NEXT: .pad #4 2501; CHECK-NEXT: sub sp, #4 2502; CHECK-NEXT: .vsave {d8, d9} 2503; CHECK-NEXT: vpush {d8, d9} 2504; CHECK-NEXT: .pad #48 2505; CHECK-NEXT: sub sp, #48 2506; CHECK-NEXT: vmov q4, q0 2507; CHECK-NEXT: vldr d0, .LCPI40_0 2508; CHECK-NEXT: vmov r11, r4, d8 2509; CHECK-NEXT: mov r6, r0 2510; CHECK-NEXT: vmov r2, r3, d0 2511; CHECK-NEXT: str r3, [sp, #36] @ 4-byte Spill 2512; CHECK-NEXT: mov r0, r11 2513; CHECK-NEXT: mov r1, r4 2514; CHECK-NEXT: mov r9, r2 2515; CHECK-NEXT: bl __aeabi_dcmpge 2516; CHECK-NEXT: mov r8, r0 2517; CHECK-NEXT: mov r0, r11 2518; CHECK-NEXT: mov r1, r4 2519; CHECK-NEXT: mov r5, r4 2520; CHECK-NEXT: bl __fixunsdfti 2521; CHECK-NEXT: vldr d0, .LCPI40_1 2522; CHECK-NEXT: cmp.w r8, #0 2523; CHECK-NEXT: str r3, [sp, #28] @ 4-byte Spill 2524; CHECK-NEXT: csel r4, r2, r8, ne 2525; CHECK-NEXT: vmov r10, r3, d0 2526; CHECK-NEXT: strd r1, r0, [sp, #16] @ 8-byte Folded Spill 2527; CHECK-NEXT: mov r0, r11 2528; CHECK-NEXT: mov r1, r5 2529; CHECK-NEXT: str r5, [sp, #40] @ 4-byte Spill 2530; CHECK-NEXT: mov r2, r10 2531; CHECK-NEXT: mov r8, r3 2532; CHECK-NEXT: bl __aeabi_dcmpgt 2533; CHECK-NEXT: cmp r0, #0 2534; CHECK-NEXT: it ne 2535; CHECK-NEXT: movne.w r4, #-1 2536; CHECK-NEXT: str r4, [r6, #8] 2537; CHECK-NEXT: mov r0, r11 2538; CHECK-NEXT: ldr r7, [sp, #36] @ 4-byte Reload 2539; CHECK-NEXT: mov r1, r5 2540; CHECK-NEXT: mov r2, r9 2541; CHECK-NEXT: mov r3, r7 2542; CHECK-NEXT: bl __aeabi_dcmpge 2543; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload 2544; CHECK-NEXT: cmp r0, #0 2545; CHECK-NEXT: mov r2, r10 2546; CHECK-NEXT: mov r3, r8 2547; CHECK-NEXT: csel r4, r1, r0, ne 2548; CHECK-NEXT: mov r0, r11 2549; CHECK-NEXT: mov r1, r5 2550; CHECK-NEXT: str.w r10, [sp, #44] @ 4-byte Spill 2551; CHECK-NEXT: bl __aeabi_dcmpgt 2552; CHECK-NEXT: cmp r0, #0 2553; CHECK-NEXT: it ne 2554; CHECK-NEXT: movne.w r4, #-1 2555; CHECK-NEXT: str r4, [r6, #4] 2556; CHECK-NEXT: mov r5, r6 2557; CHECK-NEXT: str r6, [sp, #12] @ 4-byte Spill 2558; CHECK-NEXT: mov r0, r11 2559; CHECK-NEXT: ldr r6, [sp, #40] @ 4-byte Reload 2560; CHECK-NEXT: mov r2, r9 2561; CHECK-NEXT: mov r3, r7 2562; CHECK-NEXT: str.w r11, [sp, #24] @ 4-byte Spill 2563; CHECK-NEXT: mov r1, r6 2564; CHECK-NEXT: bl __aeabi_dcmpge 2565; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload 2566; CHECK-NEXT: cmp r0, #0 2567; CHECK-NEXT: mov r2, r10 2568; CHECK-NEXT: mov r3, r8 2569; CHECK-NEXT: csel r4, r1, r0, ne 2570; CHECK-NEXT: mov r1, r6 2571; CHECK-NEXT: mov r0, r11 2572; CHECK-NEXT: mov r6, r8 2573; CHECK-NEXT: bl __aeabi_dcmpgt 2574; CHECK-NEXT: vmov r8, r11, d9 2575; CHECK-NEXT: cmp r0, #0 2576; CHECK-NEXT: mov r2, r9 2577; CHECK-NEXT: mov r3, r7 2578; CHECK-NEXT: it ne 2579; CHECK-NEXT: movne.w r4, #-1 2580; CHECK-NEXT: str r4, [r5] 2581; CHECK-NEXT: mov r10, r9 2582; CHECK-NEXT: str.w r9, [sp, #32] @ 4-byte Spill 2583; CHECK-NEXT: mov r5, r7 2584; CHECK-NEXT: mov r0, r8 2585; CHECK-NEXT: mov r1, r11 2586; CHECK-NEXT: bl __aeabi_dcmpge 2587; CHECK-NEXT: mov r9, r0 2588; CHECK-NEXT: mov r0, r8 2589; CHECK-NEXT: mov r1, r11 2590; CHECK-NEXT: bl __fixunsdfti 2591; CHECK-NEXT: ldr r4, [sp, #44] @ 4-byte Reload 2592; CHECK-NEXT: cmp.w r9, #0 2593; CHECK-NEXT: strd r3, r0, [sp, #16] @ 8-byte Folded Spill 2594; CHECK-NEXT: csel r7, r1, r9, ne 2595; CHECK-NEXT: str r2, [sp, #8] @ 4-byte Spill 2596; CHECK-NEXT: mov r0, r8 2597; CHECK-NEXT: mov r1, r11 2598; CHECK-NEXT: mov r2, r4 2599; CHECK-NEXT: mov r3, r6 2600; CHECK-NEXT: str r6, [sp, #4] @ 4-byte Spill 2601; CHECK-NEXT: bl __aeabi_dcmpgt 2602; CHECK-NEXT: cmp r0, #0 2603; CHECK-NEXT: mov r0, r8 2604; CHECK-NEXT: mov r1, r11 2605; CHECK-NEXT: mov r2, r10 2606; CHECK-NEXT: mov r3, r5 2607; CHECK-NEXT: it ne 2608; CHECK-NEXT: movne.w r7, #-1 2609; CHECK-NEXT: bl __aeabi_dcmpge 2610; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload 2611; CHECK-NEXT: cmp r0, #0 2612; CHECK-NEXT: mov r2, r4 2613; CHECK-NEXT: mov r3, r6 2614; CHECK-NEXT: csel r9, r1, r0, ne 2615; CHECK-NEXT: mov r0, r8 2616; CHECK-NEXT: mov r1, r11 2617; CHECK-NEXT: bl __aeabi_dcmpgt 2618; CHECK-NEXT: cmp r0, #0 2619; CHECK-NEXT: mov r0, r9 2620; CHECK-NEXT: it ne 2621; CHECK-NEXT: movne.w r0, #-1 2622; CHECK-NEXT: ldr.w r9, [sp, #12] @ 4-byte Reload 2623; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill 2624; CHECK-NEXT: lsrl r0, r7, #28 2625; CHECK-NEXT: mov r1, r11 2626; CHECK-NEXT: mov r3, r5 2627; CHECK-NEXT: str.w r0, [r9, #16] 2628; CHECK-NEXT: mov r0, r8 2629; CHECK-NEXT: ldr r4, [sp, #32] @ 4-byte Reload 2630; CHECK-NEXT: mov r2, r4 2631; CHECK-NEXT: bl __aeabi_dcmpge 2632; CHECK-NEXT: ldr r6, [sp, #4] @ 4-byte Reload 2633; CHECK-NEXT: cmp r0, #0 2634; CHECK-NEXT: ldr r1, [sp, #8] @ 4-byte Reload 2635; CHECK-NEXT: ldr r2, [sp, #44] @ 4-byte Reload 2636; CHECK-NEXT: csel r10, r1, r0, ne 2637; CHECK-NEXT: mov r0, r8 2638; CHECK-NEXT: mov r1, r11 2639; CHECK-NEXT: mov r3, r6 2640; CHECK-NEXT: bl __aeabi_dcmpgt 2641; CHECK-NEXT: cmp r0, #0 2642; CHECK-NEXT: it ne 2643; CHECK-NEXT: movne.w r10, #-1 2644; CHECK-NEXT: orr.w r0, r7, r10, lsl #4 2645; CHECK-NEXT: str.w r0, [r9, #20] 2646; CHECK-NEXT: mov r0, r8 2647; CHECK-NEXT: mov r1, r11 2648; CHECK-NEXT: mov r2, r4 2649; CHECK-NEXT: mov r3, r5 2650; CHECK-NEXT: bl __aeabi_dcmpge 2651; CHECK-NEXT: ldr r5, [sp, #44] @ 4-byte Reload 2652; CHECK-NEXT: cmp r0, #0 2653; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload 2654; CHECK-NEXT: mov r3, r6 2655; CHECK-NEXT: csel r7, r1, r0, ne 2656; CHECK-NEXT: mov r0, r8 2657; CHECK-NEXT: mov r1, r11 2658; CHECK-NEXT: mov r2, r5 2659; CHECK-NEXT: mov r8, r6 2660; CHECK-NEXT: bl __aeabi_dcmpgt 2661; CHECK-NEXT: cmp r0, #0 2662; CHECK-NEXT: it ne 2663; CHECK-NEXT: movne r7, #15 2664; CHECK-NEXT: and r1, r7, #15 2665; CHECK-NEXT: lsrl r10, r1, #28 2666; CHECK-NEXT: strb.w r10, [r9, #24] 2667; CHECK-NEXT: ldr r6, [sp, #24] @ 4-byte Reload 2668; CHECK-NEXT: ldr r4, [sp, #40] @ 4-byte Reload 2669; CHECK-NEXT: ldrd r2, r3, [sp, #32] @ 8-byte Folded Reload 2670; CHECK-NEXT: mov r0, r6 2671; CHECK-NEXT: mov r1, r4 2672; CHECK-NEXT: bl __aeabi_dcmpge 2673; CHECK-NEXT: ldr r1, [sp, #28] @ 4-byte Reload 2674; CHECK-NEXT: cmp r0, #0 2675; CHECK-NEXT: mov r2, r5 2676; CHECK-NEXT: mov r3, r8 2677; CHECK-NEXT: csel r7, r1, r0, ne 2678; CHECK-NEXT: mov r0, r6 2679; CHECK-NEXT: mov r1, r4 2680; CHECK-NEXT: bl __aeabi_dcmpgt 2681; CHECK-NEXT: cmp r0, #0 2682; CHECK-NEXT: it ne 2683; CHECK-NEXT: movne r7, #15 2684; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload 2685; CHECK-NEXT: and r0, r7, #15 2686; CHECK-NEXT: orr.w r0, r0, r1, lsl #4 2687; CHECK-NEXT: str.w r0, [r9, #12] 2688; CHECK-NEXT: add sp, #48 2689; CHECK-NEXT: vpop {d8, d9} 2690; CHECK-NEXT: add sp, #4 2691; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 2692; CHECK-NEXT: .p2align 3 2693; CHECK-NEXT: @ %bb.1: 2694; CHECK-NEXT: .LCPI40_0: 2695; CHECK-NEXT: .long 0 @ double 0 2696; CHECK-NEXT: .long 0 2697; CHECK-NEXT: .LCPI40_1: 2698; CHECK-NEXT: .long 4294967295 @ double 1.2676506002282293E+30 2699; CHECK-NEXT: .long 1177550847 2700 %x = call <2 x i100> @llvm.fptoui.sat.v2f64.v2i100(<2 x double> %f) 2701 ret <2 x i100> %x 2702} 2703 2704define arm_aapcs_vfpcc <2 x i128> @test_unsigned_v2f64_v2i128(<2 x double> %f) { 2705; CHECK-LABEL: test_unsigned_v2f64_v2i128: 2706; CHECK: @ %bb.0: 2707; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2708; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 2709; CHECK-NEXT: .pad #4 2710; CHECK-NEXT: sub sp, #4 2711; CHECK-NEXT: .vsave {d8, d9} 2712; CHECK-NEXT: vpush {d8, d9} 2713; CHECK-NEXT: .pad #24 2714; CHECK-NEXT: sub sp, #24 2715; CHECK-NEXT: vmov q4, q0 2716; CHECK-NEXT: vldr d0, .LCPI41_0 2717; CHECK-NEXT: vmov r8, r7, d9 2718; CHECK-NEXT: mov r4, r0 2719; CHECK-NEXT: vmov r2, r9, d0 2720; CHECK-NEXT: mov r0, r8 2721; CHECK-NEXT: mov r1, r7 2722; CHECK-NEXT: mov r3, r9 2723; CHECK-NEXT: mov r11, r2 2724; CHECK-NEXT: bl __aeabi_dcmpge 2725; CHECK-NEXT: mov r6, r0 2726; CHECK-NEXT: mov r0, r8 2727; CHECK-NEXT: mov r1, r7 2728; CHECK-NEXT: bl __fixunsdfti 2729; CHECK-NEXT: vldr d0, .LCPI41_1 2730; CHECK-NEXT: cmp r6, #0 2731; CHECK-NEXT: strd r1, r0, [sp, #8] @ 8-byte Folded Spill 2732; CHECK-NEXT: csel r6, r3, r6, ne 2733; CHECK-NEXT: vmov r10, r5, d0 2734; CHECK-NEXT: str r2, [sp] @ 4-byte Spill 2735; CHECK-NEXT: mov r0, r8 2736; CHECK-NEXT: mov r1, r7 2737; CHECK-NEXT: str r5, [sp, #16] @ 4-byte Spill 2738; CHECK-NEXT: mov r2, r10 2739; CHECK-NEXT: mov r3, r5 2740; CHECK-NEXT: bl __aeabi_dcmpgt 2741; CHECK-NEXT: cmp r0, #0 2742; CHECK-NEXT: mov r0, r8 2743; CHECK-NEXT: mov r1, r7 2744; CHECK-NEXT: mov r2, r11 2745; CHECK-NEXT: mov r3, r9 2746; CHECK-NEXT: it ne 2747; CHECK-NEXT: movne.w r6, #-1 2748; CHECK-NEXT: str r6, [r4, #28] 2749; CHECK-NEXT: str.w r11, [sp, #20] @ 4-byte Spill 2750; CHECK-NEXT: bl __aeabi_dcmpge 2751; CHECK-NEXT: ldr r6, [sp, #16] @ 4-byte Reload 2752; CHECK-NEXT: cmp r0, #0 2753; CHECK-NEXT: ldr r1, [sp] @ 4-byte Reload 2754; CHECK-NEXT: mov r2, r10 2755; CHECK-NEXT: csel r5, r1, r0, ne 2756; CHECK-NEXT: mov r0, r8 2757; CHECK-NEXT: mov r1, r7 2758; CHECK-NEXT: mov r3, r6 2759; CHECK-NEXT: bl __aeabi_dcmpgt 2760; CHECK-NEXT: cmp r0, #0 2761; CHECK-NEXT: it ne 2762; CHECK-NEXT: movne.w r5, #-1 2763; CHECK-NEXT: mov r0, r8 2764; CHECK-NEXT: mov r1, r7 2765; CHECK-NEXT: mov r2, r11 2766; CHECK-NEXT: mov r3, r9 2767; CHECK-NEXT: str r5, [r4, #24] 2768; CHECK-NEXT: mov r5, r4 2769; CHECK-NEXT: mov r4, r9 2770; CHECK-NEXT: bl __aeabi_dcmpge 2771; CHECK-NEXT: ldr r1, [sp, #8] @ 4-byte Reload 2772; CHECK-NEXT: cmp r0, #0 2773; CHECK-NEXT: mov r2, r10 2774; CHECK-NEXT: mov r3, r6 2775; CHECK-NEXT: csel r9, r1, r0, ne 2776; CHECK-NEXT: mov r0, r8 2777; CHECK-NEXT: mov r1, r7 2778; CHECK-NEXT: bl __aeabi_dcmpgt 2779; CHECK-NEXT: cmp r0, #0 2780; CHECK-NEXT: it ne 2781; CHECK-NEXT: movne.w r9, #-1 2782; CHECK-NEXT: str r5, [sp, #4] @ 4-byte Spill 2783; CHECK-NEXT: mov r0, r8 2784; CHECK-NEXT: str.w r9, [r5, #20] 2785; CHECK-NEXT: mov r1, r7 2786; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload 2787; CHECK-NEXT: mov r3, r4 2788; CHECK-NEXT: vmov r6, r11, d8 2789; CHECK-NEXT: mov r9, r4 2790; CHECK-NEXT: bl __aeabi_dcmpge 2791; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload 2792; CHECK-NEXT: cmp r0, #0 2793; CHECK-NEXT: mov r2, r10 2794; CHECK-NEXT: csel r4, r1, r0, ne 2795; CHECK-NEXT: mov r1, r7 2796; CHECK-NEXT: ldr r7, [sp, #16] @ 4-byte Reload 2797; CHECK-NEXT: mov r0, r8 2798; CHECK-NEXT: mov r3, r7 2799; CHECK-NEXT: bl __aeabi_dcmpgt 2800; CHECK-NEXT: cmp r0, #0 2801; CHECK-NEXT: it ne 2802; CHECK-NEXT: movne.w r4, #-1 2803; CHECK-NEXT: str r4, [r5, #16] 2804; CHECK-NEXT: mov r0, r6 2805; CHECK-NEXT: ldr r5, [sp, #20] @ 4-byte Reload 2806; CHECK-NEXT: mov r1, r11 2807; CHECK-NEXT: mov r3, r9 2808; CHECK-NEXT: mov r2, r5 2809; CHECK-NEXT: bl __aeabi_dcmpge 2810; CHECK-NEXT: mov r8, r0 2811; CHECK-NEXT: mov r0, r6 2812; CHECK-NEXT: mov r1, r11 2813; CHECK-NEXT: bl __fixunsdfti 2814; CHECK-NEXT: cmp.w r8, #0 2815; CHECK-NEXT: strd r1, r0, [sp, #8] @ 8-byte Folded Spill 2816; CHECK-NEXT: csel r4, r3, r8, ne 2817; CHECK-NEXT: str r2, [sp] @ 4-byte Spill 2818; CHECK-NEXT: mov r0, r6 2819; CHECK-NEXT: mov r1, r11 2820; CHECK-NEXT: mov r2, r10 2821; CHECK-NEXT: mov r3, r7 2822; CHECK-NEXT: mov r8, r7 2823; CHECK-NEXT: bl __aeabi_dcmpgt 2824; CHECK-NEXT: cmp r0, #0 2825; CHECK-NEXT: it ne 2826; CHECK-NEXT: movne.w r4, #-1 2827; CHECK-NEXT: ldr r7, [sp, #4] @ 4-byte Reload 2828; CHECK-NEXT: mov r0, r6 2829; CHECK-NEXT: mov r1, r11 2830; CHECK-NEXT: mov r2, r5 2831; CHECK-NEXT: mov r3, r9 2832; CHECK-NEXT: str r4, [r7, #12] 2833; CHECK-NEXT: bl __aeabi_dcmpge 2834; CHECK-NEXT: ldr r1, [sp] @ 4-byte Reload 2835; CHECK-NEXT: cmp r0, #0 2836; CHECK-NEXT: mov r2, r10 2837; CHECK-NEXT: mov r3, r8 2838; CHECK-NEXT: csel r4, r1, r0, ne 2839; CHECK-NEXT: mov r0, r6 2840; CHECK-NEXT: mov r1, r11 2841; CHECK-NEXT: bl __aeabi_dcmpgt 2842; CHECK-NEXT: cmp r0, #0 2843; CHECK-NEXT: mov r0, r6 2844; CHECK-NEXT: mov r1, r11 2845; CHECK-NEXT: mov r2, r5 2846; CHECK-NEXT: mov r3, r9 2847; CHECK-NEXT: it ne 2848; CHECK-NEXT: movne.w r4, #-1 2849; CHECK-NEXT: str r4, [r7, #8] 2850; CHECK-NEXT: bl __aeabi_dcmpge 2851; CHECK-NEXT: ldr r1, [sp, #8] @ 4-byte Reload 2852; CHECK-NEXT: cmp r0, #0 2853; CHECK-NEXT: mov r2, r10 2854; CHECK-NEXT: mov r3, r8 2855; CHECK-NEXT: csel r4, r1, r0, ne 2856; CHECK-NEXT: mov r0, r6 2857; CHECK-NEXT: mov r1, r11 2858; CHECK-NEXT: bl __aeabi_dcmpgt 2859; CHECK-NEXT: cmp r0, #0 2860; CHECK-NEXT: mov r0, r6 2861; CHECK-NEXT: mov r1, r11 2862; CHECK-NEXT: mov r2, r5 2863; CHECK-NEXT: mov r3, r9 2864; CHECK-NEXT: it ne 2865; CHECK-NEXT: movne.w r4, #-1 2866; CHECK-NEXT: str r4, [r7, #4] 2867; CHECK-NEXT: bl __aeabi_dcmpge 2868; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload 2869; CHECK-NEXT: cmp r0, #0 2870; CHECK-NEXT: mov r2, r10 2871; CHECK-NEXT: mov r3, r8 2872; CHECK-NEXT: csel r4, r1, r0, ne 2873; CHECK-NEXT: mov r0, r6 2874; CHECK-NEXT: mov r1, r11 2875; CHECK-NEXT: bl __aeabi_dcmpgt 2876; CHECK-NEXT: cmp r0, #0 2877; CHECK-NEXT: it ne 2878; CHECK-NEXT: movne.w r4, #-1 2879; CHECK-NEXT: str r4, [r7] 2880; CHECK-NEXT: add sp, #24 2881; CHECK-NEXT: vpop {d8, d9} 2882; CHECK-NEXT: add sp, #4 2883; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 2884; CHECK-NEXT: .p2align 3 2885; CHECK-NEXT: @ %bb.1: 2886; CHECK-NEXT: .LCPI41_0: 2887; CHECK-NEXT: .long 0 @ double 0 2888; CHECK-NEXT: .long 0 2889; CHECK-NEXT: .LCPI41_1: 2890; CHECK-NEXT: .long 4294967295 @ double 3.4028236692093843E+38 2891; CHECK-NEXT: .long 1206910975 2892 %x = call <2 x i128> @llvm.fptoui.sat.v2f64.v2i128(<2 x double> %f) 2893 ret <2 x i128> %x 2894} 2895 2896; 2897; 4-Vector half to signed integer -- result size variation 2898; 2899 2900declare <8 x i1> @llvm.fptoui.sat.v8f16.v8i1 (<8 x half>) 2901declare <8 x i8> @llvm.fptoui.sat.v8f16.v8i8 (<8 x half>) 2902declare <8 x i13> @llvm.fptoui.sat.v8f16.v8i13 (<8 x half>) 2903declare <8 x i16> @llvm.fptoui.sat.v8f16.v8i16 (<8 x half>) 2904declare <8 x i19> @llvm.fptoui.sat.v8f16.v8i19 (<8 x half>) 2905declare <8 x i50> @llvm.fptoui.sat.v8f16.v8i50 (<8 x half>) 2906declare <8 x i64> @llvm.fptoui.sat.v8f16.v8i64 (<8 x half>) 2907declare <8 x i100> @llvm.fptoui.sat.v8f16.v8i100(<8 x half>) 2908declare <8 x i128> @llvm.fptoui.sat.v8f16.v8i128(<8 x half>) 2909 2910define arm_aapcs_vfpcc <8 x i1> @test_unsigned_v8f16_v8i1(<8 x half> %f) { 2911; CHECK-LABEL: test_unsigned_v8f16_v8i1: 2912; CHECK: @ %bb.0: 2913; CHECK-NEXT: vldr s4, .LCPI42_0 2914; CHECK-NEXT: vcvtt.f32.f16 s8, s3 2915; CHECK-NEXT: vcvtb.f32.f16 s10, s3 2916; CHECK-NEXT: vcvtb.f32.f16 s3, s0 2917; CHECK-NEXT: vmov.f32 s6, #1.000000e+00 2918; CHECK-NEXT: vmaxnm.f32 s3, s3, s4 2919; CHECK-NEXT: vminnm.f32 s3, s3, s6 2920; CHECK-NEXT: vcvtt.f32.f16 s0, s0 2921; CHECK-NEXT: vcvt.u32.f32 s3, s3 2922; CHECK-NEXT: vmaxnm.f32 s0, s0, s4 2923; CHECK-NEXT: vminnm.f32 s0, s0, s6 2924; CHECK-NEXT: movs r1, #0 2925; CHECK-NEXT: vcvt.u32.f32 s0, s0 2926; CHECK-NEXT: vcvtt.f32.f16 s14, s1 2927; CHECK-NEXT: vcvtb.f32.f16 s1, s1 2928; CHECK-NEXT: vmaxnm.f32 s14, s14, s4 2929; CHECK-NEXT: vmaxnm.f32 s1, s1, s4 2930; CHECK-NEXT: vminnm.f32 s14, s14, s6 2931; CHECK-NEXT: vminnm.f32 s1, s1, s6 2932; CHECK-NEXT: vcvt.u32.f32 s14, s14 2933; CHECK-NEXT: vcvt.u32.f32 s1, s1 2934; CHECK-NEXT: vcvtt.f32.f16 s12, s2 2935; CHECK-NEXT: vmov r2, s3 2936; CHECK-NEXT: vcvtb.f32.f16 s2, s2 2937; CHECK-NEXT: vmaxnm.f32 s2, s2, s4 2938; CHECK-NEXT: vmaxnm.f32 s12, s12, s4 2939; CHECK-NEXT: vminnm.f32 s2, s2, s6 2940; CHECK-NEXT: vminnm.f32 s12, s12, s6 2941; CHECK-NEXT: vcvt.u32.f32 s2, s2 2942; CHECK-NEXT: vmaxnm.f32 s10, s10, s4 2943; CHECK-NEXT: vcvt.u32.f32 s12, s12 2944; CHECK-NEXT: vminnm.f32 s10, s10, s6 2945; CHECK-NEXT: vcvt.u32.f32 s10, s10 2946; CHECK-NEXT: vmaxnm.f32 s8, s8, s4 2947; CHECK-NEXT: vminnm.f32 s8, s8, s6 2948; CHECK-NEXT: vcvt.u32.f32 s8, s8 2949; CHECK-NEXT: and r2, r2, #1 2950; CHECK-NEXT: rsbs r2, r2, #0 2951; CHECK-NEXT: bfi r1, r2, #0, #1 2952; CHECK-NEXT: vmov r2, s0 2953; CHECK-NEXT: and r2, r2, #1 2954; CHECK-NEXT: rsbs r2, r2, #0 2955; CHECK-NEXT: bfi r1, r2, #1, #1 2956; CHECK-NEXT: vmov r2, s1 2957; CHECK-NEXT: and r2, r2, #1 2958; CHECK-NEXT: rsbs r2, r2, #0 2959; CHECK-NEXT: bfi r1, r2, #2, #1 2960; CHECK-NEXT: vmov r2, s14 2961; CHECK-NEXT: and r2, r2, #1 2962; CHECK-NEXT: rsbs r2, r2, #0 2963; CHECK-NEXT: bfi r1, r2, #3, #1 2964; CHECK-NEXT: vmov r2, s2 2965; CHECK-NEXT: and r2, r2, #1 2966; CHECK-NEXT: rsbs r2, r2, #0 2967; CHECK-NEXT: bfi r1, r2, #4, #1 2968; CHECK-NEXT: vmov r2, s12 2969; CHECK-NEXT: and r2, r2, #1 2970; CHECK-NEXT: rsbs r2, r2, #0 2971; CHECK-NEXT: bfi r1, r2, #5, #1 2972; CHECK-NEXT: vmov r2, s10 2973; CHECK-NEXT: and r2, r2, #1 2974; CHECK-NEXT: rsbs r2, r2, #0 2975; CHECK-NEXT: bfi r1, r2, #6, #1 2976; CHECK-NEXT: vmov r2, s8 2977; CHECK-NEXT: and r2, r2, #1 2978; CHECK-NEXT: rsbs r2, r2, #0 2979; CHECK-NEXT: bfi r1, r2, #7, #1 2980; CHECK-NEXT: strb r1, [r0] 2981; CHECK-NEXT: bx lr 2982; CHECK-NEXT: .p2align 2 2983; CHECK-NEXT: @ %bb.1: 2984; CHECK-NEXT: .LCPI42_0: 2985; CHECK-NEXT: .long 0x00000000 @ float 0 2986 %x = call <8 x i1> @llvm.fptoui.sat.v8f16.v8i1(<8 x half> %f) 2987 ret <8 x i1> %x 2988} 2989 2990define arm_aapcs_vfpcc <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) { 2991; CHECK-MVE-LABEL: test_unsigned_v8f16_v8i8: 2992; CHECK-MVE: @ %bb.0: 2993; CHECK-MVE-NEXT: vldr s6, .LCPI43_1 2994; CHECK-MVE-NEXT: vcvtt.f32.f16 s10, s2 2995; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2 2996; CHECK-MVE-NEXT: vldr s4, .LCPI43_0 2997; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6 2998; CHECK-MVE-NEXT: vcvtt.f32.f16 s8, s3 2999; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4 3000; CHECK-MVE-NEXT: vcvtb.f32.f16 s12, s3 3001; CHECK-MVE-NEXT: vcvt.u32.f32 s5, s2 3002; CHECK-MVE-NEXT: vcvtt.f32.f16 s2, s0 3003; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6 3004; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0 3005; CHECK-MVE-NEXT: vmaxnm.f32 s0, s0, s6 3006; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4 3007; CHECK-MVE-NEXT: vminnm.f32 s0, s0, s4 3008; CHECK-MVE-NEXT: vcvt.u32.f32 s7, s2 3009; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s1 3010; CHECK-MVE-NEXT: vcvtt.f32.f16 s14, s1 3011; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6 3012; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0 3013; CHECK-MVE-NEXT: vmaxnm.f32 s8, s8, s6 3014; CHECK-MVE-NEXT: vmaxnm.f32 s10, s10, s6 3015; CHECK-MVE-NEXT: vmaxnm.f32 s12, s12, s6 3016; CHECK-MVE-NEXT: vmaxnm.f32 s14, s14, s6 3017; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4 3018; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s4 3019; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s4 3020; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s4 3021; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s4 3022; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s2 3023; CHECK-MVE-NEXT: vcvt.u32.f32 s14, s14 3024; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s10 3025; CHECK-MVE-NEXT: vcvt.u32.f32 s12, s12 3026; CHECK-MVE-NEXT: vmov r0, s0 3027; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s8 3028; CHECK-MVE-NEXT: vmov.16 q0[0], r0 3029; CHECK-MVE-NEXT: vmov r0, s7 3030; CHECK-MVE-NEXT: vmov.16 q0[1], r0 3031; CHECK-MVE-NEXT: vmov r0, s4 3032; CHECK-MVE-NEXT: vmov.16 q0[2], r0 3033; CHECK-MVE-NEXT: vmov r0, s14 3034; CHECK-MVE-NEXT: vmov.16 q0[3], r0 3035; CHECK-MVE-NEXT: vmov r0, s5 3036; CHECK-MVE-NEXT: vmov.16 q0[4], r0 3037; CHECK-MVE-NEXT: vmov r0, s10 3038; CHECK-MVE-NEXT: vmov.16 q0[5], r0 3039; CHECK-MVE-NEXT: vmov r0, s12 3040; CHECK-MVE-NEXT: vmov.16 q0[6], r0 3041; CHECK-MVE-NEXT: vmov r0, s8 3042; CHECK-MVE-NEXT: vmov.16 q0[7], r0 3043; CHECK-MVE-NEXT: bx lr 3044; CHECK-MVE-NEXT: .p2align 2 3045; CHECK-MVE-NEXT: @ %bb.1: 3046; CHECK-MVE-NEXT: .LCPI43_0: 3047; CHECK-MVE-NEXT: .long 0x437f0000 @ float 255 3048; CHECK-MVE-NEXT: .LCPI43_1: 3049; CHECK-MVE-NEXT: .long 0x00000000 @ float 0 3050; 3051; CHECK-MVEFP-LABEL: test_unsigned_v8f16_v8i8: 3052; CHECK-MVEFP: @ %bb.0: 3053; CHECK-MVEFP-NEXT: vcvt.u16.f16 q0, q0 3054; CHECK-MVEFP-NEXT: vqmovnb.u16 q0, q0 3055; CHECK-MVEFP-NEXT: vmovlb.u8 q0, q0 3056; CHECK-MVEFP-NEXT: bx lr 3057 %x = call <8 x i8> @llvm.fptoui.sat.v8f16.v8i8(<8 x half> %f) 3058 ret <8 x i8> %x 3059} 3060 3061define arm_aapcs_vfpcc <8 x i13> @test_unsigned_v8f16_v8i13(<8 x half> %f) { 3062; CHECK-MVE-LABEL: test_unsigned_v8f16_v8i13: 3063; CHECK-MVE: @ %bb.0: 3064; CHECK-MVE-NEXT: vldr s6, .LCPI44_1 3065; CHECK-MVE-NEXT: vcvtt.f32.f16 s10, s2 3066; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2 3067; CHECK-MVE-NEXT: vldr s4, .LCPI44_0 3068; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6 3069; CHECK-MVE-NEXT: vcvtt.f32.f16 s8, s3 3070; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4 3071; CHECK-MVE-NEXT: vcvtb.f32.f16 s12, s3 3072; CHECK-MVE-NEXT: vcvt.u32.f32 s5, s2 3073; CHECK-MVE-NEXT: vcvtt.f32.f16 s2, s0 3074; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6 3075; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0 3076; CHECK-MVE-NEXT: vmaxnm.f32 s0, s0, s6 3077; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4 3078; CHECK-MVE-NEXT: vminnm.f32 s0, s0, s4 3079; CHECK-MVE-NEXT: vcvt.u32.f32 s7, s2 3080; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s1 3081; CHECK-MVE-NEXT: vcvtt.f32.f16 s14, s1 3082; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6 3083; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0 3084; CHECK-MVE-NEXT: vmaxnm.f32 s8, s8, s6 3085; CHECK-MVE-NEXT: vmaxnm.f32 s10, s10, s6 3086; CHECK-MVE-NEXT: vmaxnm.f32 s12, s12, s6 3087; CHECK-MVE-NEXT: vmaxnm.f32 s14, s14, s6 3088; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4 3089; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s4 3090; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s4 3091; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s4 3092; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s4 3093; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s2 3094; CHECK-MVE-NEXT: vcvt.u32.f32 s14, s14 3095; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s10 3096; CHECK-MVE-NEXT: vcvt.u32.f32 s12, s12 3097; CHECK-MVE-NEXT: vmov r0, s0 3098; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s8 3099; CHECK-MVE-NEXT: vmov.16 q0[0], r0 3100; CHECK-MVE-NEXT: vmov r0, s7 3101; CHECK-MVE-NEXT: vmov.16 q0[1], r0 3102; CHECK-MVE-NEXT: vmov r0, s4 3103; CHECK-MVE-NEXT: vmov.16 q0[2], r0 3104; CHECK-MVE-NEXT: vmov r0, s14 3105; CHECK-MVE-NEXT: vmov.16 q0[3], r0 3106; CHECK-MVE-NEXT: vmov r0, s5 3107; CHECK-MVE-NEXT: vmov.16 q0[4], r0 3108; CHECK-MVE-NEXT: vmov r0, s10 3109; CHECK-MVE-NEXT: vmov.16 q0[5], r0 3110; CHECK-MVE-NEXT: vmov r0, s12 3111; CHECK-MVE-NEXT: vmov.16 q0[6], r0 3112; CHECK-MVE-NEXT: vmov r0, s8 3113; CHECK-MVE-NEXT: vmov.16 q0[7], r0 3114; CHECK-MVE-NEXT: bx lr 3115; CHECK-MVE-NEXT: .p2align 2 3116; CHECK-MVE-NEXT: @ %bb.1: 3117; CHECK-MVE-NEXT: .LCPI44_0: 3118; CHECK-MVE-NEXT: .long 0x45fff800 @ float 8191 3119; CHECK-MVE-NEXT: .LCPI44_1: 3120; CHECK-MVE-NEXT: .long 0x00000000 @ float 0 3121; 3122; CHECK-MVEFP-LABEL: test_unsigned_v8f16_v8i13: 3123; CHECK-MVEFP: @ %bb.0: 3124; CHECK-MVEFP-NEXT: vmvn.i16 q1, #0xe000 3125; CHECK-MVEFP-NEXT: vcvt.u16.f16 q0, q0 3126; CHECK-MVEFP-NEXT: vmin.u16 q0, q0, q1 3127; CHECK-MVEFP-NEXT: bx lr 3128 %x = call <8 x i13> @llvm.fptoui.sat.v8f16.v8i13(<8 x half> %f) 3129 ret <8 x i13> %x 3130} 3131 3132define arm_aapcs_vfpcc <8 x i16> @test_unsigned_v8f16_v8i16(<8 x half> %f) { 3133; CHECK-MVE-LABEL: test_unsigned_v8f16_v8i16: 3134; CHECK-MVE: @ %bb.0: 3135; CHECK-MVE-NEXT: vldr s6, .LCPI45_1 3136; CHECK-MVE-NEXT: vcvtt.f32.f16 s10, s2 3137; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2 3138; CHECK-MVE-NEXT: vldr s4, .LCPI45_0 3139; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6 3140; CHECK-MVE-NEXT: vcvtt.f32.f16 s8, s3 3141; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4 3142; CHECK-MVE-NEXT: vcvtb.f32.f16 s12, s3 3143; CHECK-MVE-NEXT: vcvt.u32.f32 s5, s2 3144; CHECK-MVE-NEXT: vcvtt.f32.f16 s2, s0 3145; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6 3146; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0 3147; CHECK-MVE-NEXT: vmaxnm.f32 s0, s0, s6 3148; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4 3149; CHECK-MVE-NEXT: vminnm.f32 s0, s0, s4 3150; CHECK-MVE-NEXT: vcvt.u32.f32 s7, s2 3151; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s1 3152; CHECK-MVE-NEXT: vcvtt.f32.f16 s14, s1 3153; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6 3154; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0 3155; CHECK-MVE-NEXT: vmaxnm.f32 s8, s8, s6 3156; CHECK-MVE-NEXT: vmaxnm.f32 s10, s10, s6 3157; CHECK-MVE-NEXT: vmaxnm.f32 s12, s12, s6 3158; CHECK-MVE-NEXT: vmaxnm.f32 s14, s14, s6 3159; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4 3160; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s4 3161; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s4 3162; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s4 3163; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s4 3164; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s2 3165; CHECK-MVE-NEXT: vcvt.u32.f32 s14, s14 3166; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s10 3167; CHECK-MVE-NEXT: vcvt.u32.f32 s12, s12 3168; CHECK-MVE-NEXT: vmov r0, s0 3169; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s8 3170; CHECK-MVE-NEXT: vmov.16 q0[0], r0 3171; CHECK-MVE-NEXT: vmov r0, s7 3172; CHECK-MVE-NEXT: vmov.16 q0[1], r0 3173; CHECK-MVE-NEXT: vmov r0, s4 3174; CHECK-MVE-NEXT: vmov.16 q0[2], r0 3175; CHECK-MVE-NEXT: vmov r0, s14 3176; CHECK-MVE-NEXT: vmov.16 q0[3], r0 3177; CHECK-MVE-NEXT: vmov r0, s5 3178; CHECK-MVE-NEXT: vmov.16 q0[4], r0 3179; CHECK-MVE-NEXT: vmov r0, s10 3180; CHECK-MVE-NEXT: vmov.16 q0[5], r0 3181; CHECK-MVE-NEXT: vmov r0, s12 3182; CHECK-MVE-NEXT: vmov.16 q0[6], r0 3183; CHECK-MVE-NEXT: vmov r0, s8 3184; CHECK-MVE-NEXT: vmov.16 q0[7], r0 3185; CHECK-MVE-NEXT: bx lr 3186; CHECK-MVE-NEXT: .p2align 2 3187; CHECK-MVE-NEXT: @ %bb.1: 3188; CHECK-MVE-NEXT: .LCPI45_0: 3189; CHECK-MVE-NEXT: .long 0x477fff00 @ float 65535 3190; CHECK-MVE-NEXT: .LCPI45_1: 3191; CHECK-MVE-NEXT: .long 0x00000000 @ float 0 3192; 3193; CHECK-MVEFP-LABEL: test_unsigned_v8f16_v8i16: 3194; CHECK-MVEFP: @ %bb.0: 3195; CHECK-MVEFP-NEXT: vcvt.u16.f16 q0, q0 3196; CHECK-MVEFP-NEXT: bx lr 3197 %x = call <8 x i16> @llvm.fptoui.sat.v8f16.v8i16(<8 x half> %f) 3198 ret <8 x i16> %x 3199} 3200 3201define arm_aapcs_vfpcc <8 x i19> @test_unsigned_v8f16_v8i19(<8 x half> %f) { 3202; CHECK-LABEL: test_unsigned_v8f16_v8i19: 3203; CHECK: @ %bb.0: 3204; CHECK-NEXT: .save {r4, r5, r6, r7, r9, r11, lr} 3205; CHECK-NEXT: push.w {r4, r5, r6, r7, r9, r11, lr} 3206; CHECK-NEXT: vldr s4, .LCPI46_0 3207; CHECK-NEXT: vcvtb.f32.f16 s14, s1 3208; CHECK-NEXT: vldr s6, .LCPI46_1 3209; CHECK-NEXT: vcvtt.f32.f16 s12, s1 3210; CHECK-NEXT: vmaxnm.f32 s14, s14, s4 3211; CHECK-NEXT: vmaxnm.f32 s12, s12, s4 3212; CHECK-NEXT: vminnm.f32 s14, s14, s6 3213; CHECK-NEXT: vminnm.f32 s12, s12, s6 3214; CHECK-NEXT: vcvt.u32.f32 s14, s14 3215; CHECK-NEXT: vcvtb.f32.f16 s10, s0 3216; CHECK-NEXT: vcvt.u32.f32 s12, s12 3217; CHECK-NEXT: vcvtt.f32.f16 s0, s0 3218; CHECK-NEXT: vmaxnm.f32 s0, s0, s4 3219; CHECK-NEXT: vmaxnm.f32 s10, s10, s4 3220; CHECK-NEXT: vminnm.f32 s0, s0, s6 3221; CHECK-NEXT: vminnm.f32 s10, s10, s6 3222; CHECK-NEXT: vcvt.u32.f32 s0, s0 3223; CHECK-NEXT: movs r1, #0 3224; CHECK-NEXT: vcvt.u32.f32 s10, s10 3225; CHECK-NEXT: vcvtt.f32.f16 s8, s2 3226; CHECK-NEXT: vcvtb.f32.f16 s2, s2 3227; CHECK-NEXT: vmaxnm.f32 s8, s8, s4 3228; CHECK-NEXT: vmov r2, s14 3229; CHECK-NEXT: vmaxnm.f32 s2, s2, s4 3230; CHECK-NEXT: vmov r4, s12 3231; CHECK-NEXT: vminnm.f32 s2, s2, s6 3232; CHECK-NEXT: vcvt.u32.f32 s2, s2 3233; CHECK-NEXT: vminnm.f32 s8, s8, s6 3234; CHECK-NEXT: vcvt.u32.f32 s8, s8 3235; CHECK-NEXT: mov.w r11, #0 3236; CHECK-NEXT: vmov r12, s0 3237; CHECK-NEXT: vcvtt.f32.f16 s0, s3 3238; CHECK-NEXT: lsll r12, r1, #19 3239; CHECK-NEXT: vmaxnm.f32 s0, s0, s4 3240; CHECK-NEXT: vminnm.f32 s0, s0, s6 3241; CHECK-NEXT: movs r5, #0 3242; CHECK-NEXT: vcvt.u32.f32 s0, s0 3243; CHECK-NEXT: movs r7, #0 3244; CHECK-NEXT: mov.w r9, #0 3245; CHECK-NEXT: movs r3, #0 3246; CHECK-NEXT: orr.w r1, r1, r2, lsl #6 3247; CHECK-NEXT: lsrl r2, r5, #26 3248; CHECK-NEXT: orr.w r1, r1, r4, lsl #25 3249; CHECK-NEXT: str r1, [r0, #4] 3250; CHECK-NEXT: vmov r1, s10 3251; CHECK-NEXT: lsrl r4, r11, #7 3252; CHECK-NEXT: orr.w r1, r1, r12 3253; CHECK-NEXT: str r1, [r0] 3254; CHECK-NEXT: orr.w r1, r2, r4 3255; CHECK-NEXT: vmov r2, s2 3256; CHECK-NEXT: lsll r2, r7, #12 3257; CHECK-NEXT: vmov r4, s8 3258; CHECK-NEXT: orrs r2, r1 3259; CHECK-NEXT: movs r1, #0 3260; CHECK-NEXT: lsll r4, r1, #31 3261; CHECK-NEXT: orr.w r12, r2, r4 3262; CHECK-NEXT: vmov r4, s0 3263; CHECK-NEXT: vcvtb.f32.f16 s0, s3 3264; CHECK-NEXT: lsll r4, r3, #5 3265; CHECK-NEXT: vmaxnm.f32 s0, s0, s4 3266; CHECK-NEXT: vminnm.f32 s0, s0, s6 3267; CHECK-NEXT: vcvt.u32.f32 s0, s0 3268; CHECK-NEXT: vmov r2, s0 3269; CHECK-NEXT: mov r6, r2 3270; CHECK-NEXT: lsrl r6, r9, #14 3271; CHECK-NEXT: orr.w r3, r6, r4 3272; CHECK-NEXT: strh r3, [r0, #16] 3273; CHECK-NEXT: str.w r12, [r0, #8] 3274; CHECK-NEXT: lsrs r3, r3, #16 3275; CHECK-NEXT: strb r3, [r0, #18] 3276; CHECK-NEXT: orr.w r3, r5, r11 3277; CHECK-NEXT: orrs r3, r7 3278; CHECK-NEXT: orrs r1, r3 3279; CHECK-NEXT: orr.w r1, r1, r2, lsl #18 3280; CHECK-NEXT: str r1, [r0, #12] 3281; CHECK-NEXT: pop.w {r4, r5, r6, r7, r9, r11, pc} 3282; CHECK-NEXT: .p2align 2 3283; CHECK-NEXT: @ %bb.1: 3284; CHECK-NEXT: .LCPI46_0: 3285; CHECK-NEXT: .long 0x00000000 @ float 0 3286; CHECK-NEXT: .LCPI46_1: 3287; CHECK-NEXT: .long 0x48ffffe0 @ float 524287 3288 %x = call <8 x i19> @llvm.fptoui.sat.v8f16.v8i19(<8 x half> %f) 3289 ret <8 x i19> %x 3290} 3291 3292define arm_aapcs_vfpcc <8 x i32> @test_unsigned_v8f16_v8i32_duplicate(<8 x half> %f) { 3293; CHECK-LABEL: test_unsigned_v8f16_v8i32_duplicate: 3294; CHECK: @ %bb.0: 3295; CHECK-NEXT: vmovx.f16 s4, s3 3296; CHECK-NEXT: vmovx.f16 s6, s0 3297; CHECK-NEXT: vcvt.u32.f16 s8, s4 3298; CHECK-NEXT: vmovx.f16 s4, s2 3299; CHECK-NEXT: vcvt.u32.f16 s10, s4 3300; CHECK-NEXT: vmovx.f16 s4, s1 3301; CHECK-NEXT: vcvt.u32.f16 s14, s2 3302; CHECK-NEXT: vcvt.u32.f16 s2, s1 3303; CHECK-NEXT: vcvt.u32.f16 s0, s0 3304; CHECK-NEXT: vcvt.u32.f16 s4, s4 3305; CHECK-NEXT: vcvt.u32.f16 s6, s6 3306; CHECK-NEXT: vmov r0, s2 3307; CHECK-NEXT: vmov r1, s0 3308; CHECK-NEXT: vcvt.u32.f16 s12, s3 3309; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 3310; CHECK-NEXT: vmov r0, s4 3311; CHECK-NEXT: vmov r1, s6 3312; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 3313; CHECK-NEXT: vmov r0, s12 3314; CHECK-NEXT: vmov r1, s14 3315; CHECK-NEXT: vmov q1[2], q1[0], r1, r0 3316; CHECK-NEXT: vmov r0, s8 3317; CHECK-NEXT: vmov r1, s10 3318; CHECK-NEXT: vmov q1[3], q1[1], r1, r0 3319; CHECK-NEXT: bx lr 3320 %x = call <8 x i32> @llvm.fptoui.sat.v8f16.v8i32(<8 x half> %f) 3321 ret <8 x i32> %x 3322} 3323 3324define arm_aapcs_vfpcc <8 x i50> @test_unsigned_v8f16_v8i50(<8 x half> %f) { 3325; CHECK-LABEL: test_unsigned_v8f16_v8i50: 3326; CHECK: @ %bb.0: 3327; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 3328; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 3329; CHECK-NEXT: .pad #4 3330; CHECK-NEXT: sub sp, #4 3331; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} 3332; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} 3333; CHECK-NEXT: .pad #24 3334; CHECK-NEXT: sub sp, #24 3335; CHECK-NEXT: vmov q4, q0 3336; CHECK-NEXT: mov r10, r0 3337; CHECK-NEXT: vcvtb.f32.f16 s22, s18 3338; CHECK-NEXT: str r0, [sp] @ 4-byte Spill 3339; CHECK-NEXT: vmov r0, s22 3340; CHECK-NEXT: bl __aeabi_f2ulz 3341; CHECK-NEXT: vcvtt.f32.f16 s26, s17 3342; CHECK-NEXT: mov r6, r0 3343; CHECK-NEXT: vmov r0, s26 3344; CHECK-NEXT: vcvtt.f32.f16 s20, s18 3345; CHECK-NEXT: vcvtb.f32.f16 s24, s17 3346; CHECK-NEXT: vcmp.f32 s22, #0 3347; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3348; CHECK-NEXT: it lt 3349; CHECK-NEXT: movlt r1, #0 3350; CHECK-NEXT: vmov r8, s20 3351; CHECK-NEXT: vldr s18, .LCPI48_0 3352; CHECK-NEXT: vmov r9, s24 3353; CHECK-NEXT: mov r4, r1 3354; CHECK-NEXT: it lt 3355; CHECK-NEXT: movlt r6, #0 3356; CHECK-NEXT: bl __aeabi_f2ulz 3357; CHECK-NEXT: vcmp.f32 s26, #0 3358; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3359; CHECK-NEXT: it lt 3360; CHECK-NEXT: movlt r1, #0 3361; CHECK-NEXT: it lt 3362; CHECK-NEXT: movlt r0, #0 3363; CHECK-NEXT: mov r7, r0 3364; CHECK-NEXT: mov r0, r9 3365; CHECK-NEXT: mov r5, r1 3366; CHECK-NEXT: bl __aeabi_f2ulz 3367; CHECK-NEXT: vcmp.f32 s24, #0 3368; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3369; CHECK-NEXT: itt lt 3370; CHECK-NEXT: movlt r1, #0 3371; CHECK-NEXT: movlt r0, #0 3372; CHECK-NEXT: vcmp.f32 s24, s18 3373; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3374; CHECK-NEXT: it gt 3375; CHECK-NEXT: movgt.w r0, #-1 3376; CHECK-NEXT: vcmp.f32 s26, s18 3377; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill 3378; CHECK-NEXT: itt gt 3379; CHECK-NEXT: movwgt r1, #65535 3380; CHECK-NEXT: movtgt r1, #3 3381; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3382; CHECK-NEXT: mov r0, r8 3383; CHECK-NEXT: vcmp.f32 s22, s18 3384; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill 3385; CHECK-NEXT: it gt 3386; CHECK-NEXT: movgt.w r7, #-1 3387; CHECK-NEXT: str r7, [sp, #12] @ 4-byte Spill 3388; CHECK-NEXT: itt gt 3389; CHECK-NEXT: movwgt r5, #65535 3390; CHECK-NEXT: movtgt r5, #3 3391; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill 3392; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3393; CHECK-NEXT: it gt 3394; CHECK-NEXT: movgt.w r6, #-1 3395; CHECK-NEXT: str.w r6, [r10, #25] 3396; CHECK-NEXT: itt gt 3397; CHECK-NEXT: movwgt r4, #65535 3398; CHECK-NEXT: movtgt r4, #3 3399; CHECK-NEXT: str r4, [sp, #4] @ 4-byte Spill 3400; CHECK-NEXT: bl __aeabi_f2ulz 3401; CHECK-NEXT: vcmp.f32 s20, #0 3402; CHECK-NEXT: mov r6, r0 3403; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3404; CHECK-NEXT: vcmp.f32 s20, s18 3405; CHECK-NEXT: vcvtb.f32.f16 s20, s19 3406; CHECK-NEXT: mov r5, r1 3407; CHECK-NEXT: vmov r0, s20 3408; CHECK-NEXT: itt lt 3409; CHECK-NEXT: movlt r5, #0 3410; CHECK-NEXT: movlt r6, #0 3411; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3412; CHECK-NEXT: ittt gt 3413; CHECK-NEXT: movgt.w r6, #-1 3414; CHECK-NEXT: movwgt r5, #65535 3415; CHECK-NEXT: movtgt r5, #3 3416; CHECK-NEXT: bl __aeabi_f2ulz 3417; CHECK-NEXT: vcmp.f32 s20, #0 3418; CHECK-NEXT: mov r9, r0 3419; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3420; CHECK-NEXT: vcmp.f32 s20, s18 3421; CHECK-NEXT: vcvtt.f32.f16 s20, s19 3422; CHECK-NEXT: mov r11, r1 3423; CHECK-NEXT: vmov r0, s20 3424; CHECK-NEXT: itt lt 3425; CHECK-NEXT: movlt.w r11, #0 3426; CHECK-NEXT: movlt.w r9, #0 3427; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3428; CHECK-NEXT: ittt gt 3429; CHECK-NEXT: movgt.w r9, #-1 3430; CHECK-NEXT: movwgt r11, #65535 3431; CHECK-NEXT: movtgt r11, #3 3432; CHECK-NEXT: bl __aeabi_f2ulz 3433; CHECK-NEXT: vcmp.f32 s20, #0 3434; CHECK-NEXT: mov r10, r0 3435; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3436; CHECK-NEXT: vcmp.f32 s20, s18 3437; CHECK-NEXT: vcvtb.f32.f16 s20, s16 3438; CHECK-NEXT: mov r7, r1 3439; CHECK-NEXT: vmov r0, s20 3440; CHECK-NEXT: itt lt 3441; CHECK-NEXT: movlt r7, #0 3442; CHECK-NEXT: movlt.w r10, #0 3443; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3444; CHECK-NEXT: ittt gt 3445; CHECK-NEXT: movgt.w r10, #-1 3446; CHECK-NEXT: movwgt r7, #65535 3447; CHECK-NEXT: movtgt r7, #3 3448; CHECK-NEXT: bl __aeabi_f2ulz 3449; CHECK-NEXT: vcmp.f32 s20, #0 3450; CHECK-NEXT: mov r8, r1 3451; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3452; CHECK-NEXT: itt lt 3453; CHECK-NEXT: movlt.w r8, #0 3454; CHECK-NEXT: movlt r0, #0 3455; CHECK-NEXT: vcmp.f32 s20, s18 3456; CHECK-NEXT: bfc r11, #18, #14 3457; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3458; CHECK-NEXT: it gt 3459; CHECK-NEXT: movgt.w r0, #-1 3460; CHECK-NEXT: ldr r4, [sp] @ 4-byte Reload 3461; CHECK-NEXT: mov r2, r9 3462; CHECK-NEXT: lsrl r2, r11, #28 3463; CHECK-NEXT: bfc r5, #18, #14 3464; CHECK-NEXT: vcvtt.f32.f16 s16, s16 3465; CHECK-NEXT: str r0, [r4] 3466; CHECK-NEXT: lsr.w r0, r7, #10 3467; CHECK-NEXT: bfc r7, #18, #14 3468; CHECK-NEXT: lsll r10, r7, #22 3469; CHECK-NEXT: orr.w r1, r11, r7 3470; CHECK-NEXT: str.w r1, [r4, #45] 3471; CHECK-NEXT: orr.w r1, r2, r10 3472; CHECK-NEXT: str.w r1, [r4, #41] 3473; CHECK-NEXT: strb.w r0, [r4, #49] 3474; CHECK-NEXT: mov r0, r6 3475; CHECK-NEXT: lsrl r0, r5, #14 3476; CHECK-NEXT: mov r7, r4 3477; CHECK-NEXT: orr.w r1, r5, r9, lsl #4 3478; CHECK-NEXT: str.w r1, [r4, #37] 3479; CHECK-NEXT: str.w r0, [r4, #33] 3480; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload 3481; CHECK-NEXT: bfc r0, #18, #14 3482; CHECK-NEXT: orr.w r0, r0, r6, lsl #18 3483; CHECK-NEXT: str.w r0, [r4, #29] 3484; CHECK-NEXT: vmov r0, s16 3485; CHECK-NEXT: ldr r5, [sp, #8] @ 4-byte Reload 3486; CHECK-NEXT: ldr r3, [sp, #16] @ 4-byte Reload 3487; CHECK-NEXT: ldr.w r9, [sp, #20] @ 4-byte Reload 3488; CHECK-NEXT: mov r1, r5 3489; CHECK-NEXT: ldr r4, [sp, #12] @ 4-byte Reload 3490; CHECK-NEXT: bfc r1, #18, #14 3491; CHECK-NEXT: bfc r3, #18, #14 3492; CHECK-NEXT: mov r6, r9 3493; CHECK-NEXT: lsll r4, r1, #22 3494; CHECK-NEXT: lsrl r6, r3, #28 3495; CHECK-NEXT: itt gt 3496; CHECK-NEXT: movwgt r8, #65535 3497; CHECK-NEXT: movtgt r8, #3 3498; CHECK-NEXT: orrs r1, r3 3499; CHECK-NEXT: str r1, [r7, #20] 3500; CHECK-NEXT: bl __aeabi_f2ulz 3501; CHECK-NEXT: vcmp.f32 s16, #0 3502; CHECK-NEXT: orr.w r2, r6, r4 3503; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3504; CHECK-NEXT: itt lt 3505; CHECK-NEXT: movlt r0, #0 3506; CHECK-NEXT: movlt r1, #0 3507; CHECK-NEXT: vcmp.f32 s16, s18 3508; CHECK-NEXT: bfc r8, #18, #14 3509; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3510; CHECK-NEXT: itt gt 3511; CHECK-NEXT: movwgt r1, #65535 3512; CHECK-NEXT: movtgt r1, #3 3513; CHECK-NEXT: str r2, [r7, #16] 3514; CHECK-NEXT: lsr.w r2, r5, #10 3515; CHECK-NEXT: strb r2, [r7, #24] 3516; CHECK-NEXT: it gt 3517; CHECK-NEXT: movgt.w r0, #-1 3518; CHECK-NEXT: mov r2, r0 3519; CHECK-NEXT: bfc r1, #18, #14 3520; CHECK-NEXT: lsrl r2, r1, #14 3521; CHECK-NEXT: orr.w r0, r8, r0, lsl #18 3522; CHECK-NEXT: orr.w r1, r1, r9, lsl #4 3523; CHECK-NEXT: strd r2, r1, [r7, #8] 3524; CHECK-NEXT: str r0, [r7, #4] 3525; CHECK-NEXT: add sp, #24 3526; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} 3527; CHECK-NEXT: add sp, #4 3528; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 3529; CHECK-NEXT: .p2align 2 3530; CHECK-NEXT: @ %bb.1: 3531; CHECK-NEXT: .LCPI48_0: 3532; CHECK-NEXT: .long 0x587fffff @ float 1.12589984E+15 3533 %x = call <8 x i50> @llvm.fptoui.sat.v8f16.v8i50(<8 x half> %f) 3534 ret <8 x i50> %x 3535} 3536 3537define arm_aapcs_vfpcc <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) { 3538; CHECK-LABEL: test_unsigned_v8f16_v8i64: 3539; CHECK: @ %bb.0: 3540; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 3541; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 3542; CHECK-NEXT: .pad #4 3543; CHECK-NEXT: sub sp, #4 3544; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14} 3545; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14} 3546; CHECK-NEXT: vmov q4, q0 3547; CHECK-NEXT: vcvtt.f32.f16 s22, s19 3548; CHECK-NEXT: vmov r0, s22 3549; CHECK-NEXT: bl __aeabi_f2ulz 3550; CHECK-NEXT: vcvtb.f32.f16 s26, s19 3551; CHECK-NEXT: mov r9, r0 3552; CHECK-NEXT: vmov r0, s26 3553; CHECK-NEXT: vldr s28, .LCPI49_0 3554; CHECK-NEXT: vcmp.f32 s22, #0 3555; CHECK-NEXT: mov r8, r1 3556; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3557; CHECK-NEXT: vcvtt.f32.f16 s20, s16 3558; CHECK-NEXT: vcvtt.f32.f16 s24, s18 3559; CHECK-NEXT: itt lt 3560; CHECK-NEXT: movlt.w r9, #0 3561; CHECK-NEXT: movlt.w r8, #0 3562; CHECK-NEXT: vcmp.f32 s22, s28 3563; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3564; CHECK-NEXT: vmov r6, s20 3565; CHECK-NEXT: vmov r4, s24 3566; CHECK-NEXT: itt gt 3567; CHECK-NEXT: movgt.w r8, #-1 3568; CHECK-NEXT: movgt.w r9, #-1 3569; CHECK-NEXT: bl __aeabi_f2ulz 3570; CHECK-NEXT: mov r10, r0 3571; CHECK-NEXT: vcmp.f32 s26, #0 3572; CHECK-NEXT: mov r11, r1 3573; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3574; CHECK-NEXT: mov r0, r4 3575; CHECK-NEXT: itt lt 3576; CHECK-NEXT: movlt.w r11, #0 3577; CHECK-NEXT: movlt.w r10, #0 3578; CHECK-NEXT: vcmp.f32 s26, s28 3579; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3580; CHECK-NEXT: itt gt 3581; CHECK-NEXT: movgt.w r10, #-1 3582; CHECK-NEXT: movgt.w r11, #-1 3583; CHECK-NEXT: bl __aeabi_f2ulz 3584; CHECK-NEXT: mov r5, r0 3585; CHECK-NEXT: vcmp.f32 s24, #0 3586; CHECK-NEXT: mov r4, r1 3587; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3588; CHECK-NEXT: mov r0, r6 3589; CHECK-NEXT: itt lt 3590; CHECK-NEXT: movlt r5, #0 3591; CHECK-NEXT: movlt r4, #0 3592; CHECK-NEXT: vcmp.f32 s24, s28 3593; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3594; CHECK-NEXT: itt gt 3595; CHECK-NEXT: movgt.w r4, #-1 3596; CHECK-NEXT: movgt.w r5, #-1 3597; CHECK-NEXT: bl __aeabi_f2ulz 3598; CHECK-NEXT: vcvtb.f32.f16 s16, s16 3599; CHECK-NEXT: mov r7, r0 3600; CHECK-NEXT: vmov r0, s16 3601; CHECK-NEXT: mov r6, r1 3602; CHECK-NEXT: vcmp.f32 s20, #0 3603; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3604; CHECK-NEXT: itt lt 3605; CHECK-NEXT: movlt r7, #0 3606; CHECK-NEXT: movlt r6, #0 3607; CHECK-NEXT: vcmp.f32 s20, s28 3608; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3609; CHECK-NEXT: itt gt 3610; CHECK-NEXT: movgt.w r6, #-1 3611; CHECK-NEXT: movgt.w r7, #-1 3612; CHECK-NEXT: bl __aeabi_f2ulz 3613; CHECK-NEXT: vcmp.f32 s16, #0 3614; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3615; CHECK-NEXT: vcmp.f32 s16, s28 3616; CHECK-NEXT: itt lt 3617; CHECK-NEXT: movlt r1, #0 3618; CHECK-NEXT: movlt r0, #0 3619; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3620; CHECK-NEXT: it gt 3621; CHECK-NEXT: movgt.w r0, #-1 3622; CHECK-NEXT: vcvtt.f32.f16 s16, s17 3623; CHECK-NEXT: vmov q5[2], q5[0], r0, r7 3624; CHECK-NEXT: vmov r0, s16 3625; CHECK-NEXT: it gt 3626; CHECK-NEXT: movgt.w r1, #-1 3627; CHECK-NEXT: vmov q5[3], q5[1], r1, r6 3628; CHECK-NEXT: bl __aeabi_f2ulz 3629; CHECK-NEXT: vcmp.f32 s16, #0 3630; CHECK-NEXT: mov r7, r0 3631; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3632; CHECK-NEXT: vcmp.f32 s16, s28 3633; CHECK-NEXT: vcvtb.f32.f16 s16, s17 3634; CHECK-NEXT: mov r6, r1 3635; CHECK-NEXT: vmov r0, s16 3636; CHECK-NEXT: itt lt 3637; CHECK-NEXT: movlt r7, #0 3638; CHECK-NEXT: movlt r6, #0 3639; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3640; CHECK-NEXT: itt gt 3641; CHECK-NEXT: movgt.w r6, #-1 3642; CHECK-NEXT: movgt.w r7, #-1 3643; CHECK-NEXT: bl __aeabi_f2ulz 3644; CHECK-NEXT: vcmp.f32 s16, #0 3645; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3646; CHECK-NEXT: vcmp.f32 s16, s28 3647; CHECK-NEXT: itt lt 3648; CHECK-NEXT: movlt r1, #0 3649; CHECK-NEXT: movlt r0, #0 3650; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3651; CHECK-NEXT: it gt 3652; CHECK-NEXT: movgt.w r0, #-1 3653; CHECK-NEXT: vcvtb.f32.f16 s16, s18 3654; CHECK-NEXT: vmov q6[2], q6[0], r0, r7 3655; CHECK-NEXT: vmov r0, s16 3656; CHECK-NEXT: it gt 3657; CHECK-NEXT: movgt.w r1, #-1 3658; CHECK-NEXT: vmov q6[3], q6[1], r1, r6 3659; CHECK-NEXT: bl __aeabi_f2ulz 3660; CHECK-NEXT: vcmp.f32 s16, #0 3661; CHECK-NEXT: vmov q3[2], q3[0], r10, r9 3662; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3663; CHECK-NEXT: itt lt 3664; CHECK-NEXT: movlt r1, #0 3665; CHECK-NEXT: movlt r0, #0 3666; CHECK-NEXT: vcmp.f32 s16, s28 3667; CHECK-NEXT: vmov q3[3], q3[1], r11, r8 3668; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3669; CHECK-NEXT: itt gt 3670; CHECK-NEXT: movgt.w r0, #-1 3671; CHECK-NEXT: movgt.w r1, #-1 3672; CHECK-NEXT: vmov q2[2], q2[0], r0, r5 3673; CHECK-NEXT: vmov q0, q5 3674; CHECK-NEXT: vmov q2[3], q2[1], r1, r4 3675; CHECK-NEXT: vmov q1, q6 3676; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14} 3677; CHECK-NEXT: add sp, #4 3678; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 3679; CHECK-NEXT: .p2align 2 3680; CHECK-NEXT: @ %bb.1: 3681; CHECK-NEXT: .LCPI49_0: 3682; CHECK-NEXT: .long 0x5f7fffff @ float 1.8446743E+19 3683 %x = call <8 x i64> @llvm.fptoui.sat.v8f16.v8i64(<8 x half> %f) 3684 ret <8 x i64> %x 3685} 3686 3687define arm_aapcs_vfpcc <8 x i100> @test_unsigned_v8f16_v8i100(<8 x half> %f) { 3688; CHECK-LABEL: test_unsigned_v8f16_v8i100: 3689; CHECK: @ %bb.0: 3690; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} 3691; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} 3692; CHECK-NEXT: .pad #4 3693; CHECK-NEXT: sub sp, #4 3694; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12} 3695; CHECK-NEXT: vpush {d8, d9, d10, d11, d12} 3696; CHECK-NEXT: .pad #56 3697; CHECK-NEXT: sub sp, #56 3698; CHECK-NEXT: vmov q4, q0 3699; CHECK-NEXT: mov r4, r0 3700; CHECK-NEXT: vcvtb.f32.f16 s22, s17 3701; CHECK-NEXT: vmov r0, s22 3702; CHECK-NEXT: bl __fixunssfti 3703; CHECK-NEXT: vcvtb.f32.f16 s24, s18 3704; CHECK-NEXT: mov r8, r0 3705; CHECK-NEXT: vmov r0, s24 3706; CHECK-NEXT: vldr s20, .LCPI50_0 3707; CHECK-NEXT: vcmp.f32 s22, #0 3708; CHECK-NEXT: mov r9, r1 3709; CHECK-NEXT: mov r10, r2 3710; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3711; CHECK-NEXT: itttt lt 3712; CHECK-NEXT: movlt.w r10, #0 3713; CHECK-NEXT: movlt.w r9, #0 3714; CHECK-NEXT: movlt.w r8, #0 3715; CHECK-NEXT: movlt r3, #0 3716; CHECK-NEXT: vcmp.f32 s22, s20 3717; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3718; CHECK-NEXT: it gt 3719; CHECK-NEXT: movgt r3, #15 3720; CHECK-NEXT: str r3, [sp, #52] @ 4-byte Spill 3721; CHECK-NEXT: ittt gt 3722; CHECK-NEXT: movgt.w r8, #-1 3723; CHECK-NEXT: movgt.w r9, #-1 3724; CHECK-NEXT: movgt.w r10, #-1 3725; CHECK-NEXT: bl __fixunssfti 3726; CHECK-NEXT: vcvtb.f32.f16 s22, s19 3727; CHECK-NEXT: mov r5, r0 3728; CHECK-NEXT: vmov r0, s22 3729; CHECK-NEXT: mov r6, r1 3730; CHECK-NEXT: vcmp.f32 s24, #0 3731; CHECK-NEXT: mov r7, r2 3732; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3733; CHECK-NEXT: itttt lt 3734; CHECK-NEXT: movlt r7, #0 3735; CHECK-NEXT: movlt r6, #0 3736; CHECK-NEXT: movlt r5, #0 3737; CHECK-NEXT: movlt r3, #0 3738; CHECK-NEXT: vcmp.f32 s24, s20 3739; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3740; CHECK-NEXT: it gt 3741; CHECK-NEXT: movgt r3, #15 3742; CHECK-NEXT: str r3, [sp, #48] @ 4-byte Spill 3743; CHECK-NEXT: ittt gt 3744; CHECK-NEXT: movgt.w r5, #-1 3745; CHECK-NEXT: movgt.w r6, #-1 3746; CHECK-NEXT: movgt.w r7, #-1 3747; CHECK-NEXT: bl __fixunssfti 3748; CHECK-NEXT: vcmp.f32 s22, #0 3749; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3750; CHECK-NEXT: vcmp.f32 s22, s20 3751; CHECK-NEXT: itttt lt 3752; CHECK-NEXT: movlt r3, #0 3753; CHECK-NEXT: movlt r0, #0 3754; CHECK-NEXT: movlt r1, #0 3755; CHECK-NEXT: movlt r2, #0 3756; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3757; CHECK-NEXT: it gt 3758; CHECK-NEXT: movgt.w r2, #-1 3759; CHECK-NEXT: str.w r2, [r4, #83] 3760; CHECK-NEXT: it gt 3761; CHECK-NEXT: movgt.w r1, #-1 3762; CHECK-NEXT: str.w r1, [r4, #79] 3763; CHECK-NEXT: it gt 3764; CHECK-NEXT: movgt.w r0, #-1 3765; CHECK-NEXT: vcvtt.f32.f16 s22, s16 3766; CHECK-NEXT: str.w r0, [r4, #75] 3767; CHECK-NEXT: vmov r0, s22 3768; CHECK-NEXT: str.w r7, [r4, #58] 3769; CHECK-NEXT: str.w r6, [r4, #54] 3770; CHECK-NEXT: str.w r5, [r4, #50] 3771; CHECK-NEXT: str.w r10, [r4, #33] 3772; CHECK-NEXT: str.w r9, [r4, #29] 3773; CHECK-NEXT: str.w r8, [r4, #25] 3774; CHECK-NEXT: it gt 3775; CHECK-NEXT: movgt r3, #15 3776; CHECK-NEXT: str r3, [sp, #40] @ 4-byte Spill 3777; CHECK-NEXT: bl __fixunssfti 3778; CHECK-NEXT: vcmp.f32 s22, #0 3779; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3780; CHECK-NEXT: vcmp.f32 s22, s20 3781; CHECK-NEXT: itttt lt 3782; CHECK-NEXT: movlt r0, #0 3783; CHECK-NEXT: movlt r1, #0 3784; CHECK-NEXT: movlt r2, #0 3785; CHECK-NEXT: movlt r3, #0 3786; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3787; CHECK-NEXT: it gt 3788; CHECK-NEXT: movgt r3, #15 3789; CHECK-NEXT: str r3, [sp, #44] @ 4-byte Spill 3790; CHECK-NEXT: it gt 3791; CHECK-NEXT: movgt.w r2, #-1 3792; CHECK-NEXT: str r2, [sp, #36] @ 4-byte Spill 3793; CHECK-NEXT: it gt 3794; CHECK-NEXT: movgt.w r1, #-1 3795; CHECK-NEXT: str r1, [sp, #32] @ 4-byte Spill 3796; CHECK-NEXT: it gt 3797; CHECK-NEXT: movgt.w r0, #-1 3798; CHECK-NEXT: vcvtt.f32.f16 s22, s17 3799; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill 3800; CHECK-NEXT: vmov r0, s22 3801; CHECK-NEXT: bl __fixunssfti 3802; CHECK-NEXT: vcmp.f32 s22, #0 3803; CHECK-NEXT: mov r5, r1 3804; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3805; CHECK-NEXT: itttt lt 3806; CHECK-NEXT: movlt r5, #0 3807; CHECK-NEXT: movlt r0, #0 3808; CHECK-NEXT: movlt r2, #0 3809; CHECK-NEXT: movlt r3, #0 3810; CHECK-NEXT: vcmp.f32 s22, s20 3811; CHECK-NEXT: vcvtt.f32.f16 s18, s18 3812; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3813; CHECK-NEXT: it gt 3814; CHECK-NEXT: movgt r3, #15 3815; CHECK-NEXT: str r3, [sp, #28] @ 4-byte Spill 3816; CHECK-NEXT: it gt 3817; CHECK-NEXT: movgt.w r2, #-1 3818; CHECK-NEXT: str r2, [sp, #20] @ 4-byte Spill 3819; CHECK-NEXT: it gt 3820; CHECK-NEXT: movgt.w r0, #-1 3821; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill 3822; CHECK-NEXT: vmov r0, s18 3823; CHECK-NEXT: it gt 3824; CHECK-NEXT: movgt.w r5, #-1 3825; CHECK-NEXT: bl __fixunssfti 3826; CHECK-NEXT: vcmp.f32 s18, #0 3827; CHECK-NEXT: mov r9, r1 3828; CHECK-NEXT: mov r8, r2 3829; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3830; CHECK-NEXT: vcmp.f32 s18, s20 3831; CHECK-NEXT: itttt lt 3832; CHECK-NEXT: movlt r0, #0 3833; CHECK-NEXT: movlt.w r9, #0 3834; CHECK-NEXT: movlt.w r8, #0 3835; CHECK-NEXT: movlt r3, #0 3836; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3837; CHECK-NEXT: it gt 3838; CHECK-NEXT: movgt r3, #15 3839; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill 3840; CHECK-NEXT: ittt gt 3841; CHECK-NEXT: movgt.w r8, #-1 3842; CHECK-NEXT: movgt.w r9, #-1 3843; CHECK-NEXT: movgt.w r0, #-1 3844; CHECK-NEXT: vcvtt.f32.f16 s18, s19 3845; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill 3846; CHECK-NEXT: vmov r0, s18 3847; CHECK-NEXT: bl __fixunssfti 3848; CHECK-NEXT: vcvtb.f32.f16 s16, s16 3849; CHECK-NEXT: mov r6, r0 3850; CHECK-NEXT: vmov r0, s16 3851; CHECK-NEXT: mov r11, r1 3852; CHECK-NEXT: vcmp.f32 s18, #0 3853; CHECK-NEXT: mov r10, r2 3854; CHECK-NEXT: mov r7, r3 3855; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3856; CHECK-NEXT: itttt lt 3857; CHECK-NEXT: movlt.w r11, #0 3858; CHECK-NEXT: movlt r6, #0 3859; CHECK-NEXT: movlt.w r10, #0 3860; CHECK-NEXT: movlt r7, #0 3861; CHECK-NEXT: vcmp.f32 s18, s20 3862; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3863; CHECK-NEXT: itttt gt 3864; CHECK-NEXT: movgt r7, #15 3865; CHECK-NEXT: movgt.w r10, #-1 3866; CHECK-NEXT: movgt.w r6, #-1 3867; CHECK-NEXT: movgt.w r11, #-1 3868; CHECK-NEXT: bl __fixunssfti 3869; CHECK-NEXT: vcmp.f32 s16, #0 3870; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3871; CHECK-NEXT: itttt lt 3872; CHECK-NEXT: movlt r3, #0 3873; CHECK-NEXT: movlt r0, #0 3874; CHECK-NEXT: movlt r1, #0 3875; CHECK-NEXT: movlt r2, #0 3876; CHECK-NEXT: vcmp.f32 s16, s20 3877; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3878; CHECK-NEXT: it gt 3879; CHECK-NEXT: movgt.w r2, #-1 3880; CHECK-NEXT: str r2, [r4, #8] 3881; CHECK-NEXT: it gt 3882; CHECK-NEXT: movgt.w r1, #-1 3883; CHECK-NEXT: str r1, [r4, #4] 3884; CHECK-NEXT: it gt 3885; CHECK-NEXT: movgt.w r0, #-1 3886; CHECK-NEXT: str r0, [r4] 3887; CHECK-NEXT: mov r0, r6 3888; CHECK-NEXT: lsrl r0, r11, #28 3889; CHECK-NEXT: and r1, r7, #15 3890; CHECK-NEXT: str.w r0, [r4, #91] 3891; CHECK-NEXT: ldr r2, [sp, #8] @ 4-byte Reload 3892; CHECK-NEXT: mov r0, r2 3893; CHECK-NEXT: lsrl r0, r9, #28 3894; CHECK-NEXT: str.w r0, [r4, #66] 3895; CHECK-NEXT: ldr.w lr, [sp, #16] @ 4-byte Reload 3896; CHECK-NEXT: mov r0, lr 3897; CHECK-NEXT: lsrl r0, r5, #28 3898; CHECK-NEXT: str r5, [sp, #4] @ 4-byte Spill 3899; CHECK-NEXT: str.w r0, [r4, #41] 3900; CHECK-NEXT: ldr.w r12, [sp, #24] @ 4-byte Reload 3901; CHECK-NEXT: ldr r5, [sp, #32] @ 4-byte Reload 3902; CHECK-NEXT: mov r0, r12 3903; CHECK-NEXT: lsrl r0, r5, #28 3904; CHECK-NEXT: str r0, [r4, #16] 3905; CHECK-NEXT: orr.w r0, r11, r10, lsl #4 3906; CHECK-NEXT: lsrl r10, r1, #28 3907; CHECK-NEXT: str.w r0, [r4, #95] 3908; CHECK-NEXT: strb.w r10, [r4, #99] 3909; CHECK-NEXT: ldr r0, [sp, #40] @ 4-byte Reload 3910; CHECK-NEXT: and r0, r0, #15 3911; CHECK-NEXT: orr.w r0, r0, r6, lsl #4 3912; CHECK-NEXT: str.w r0, [r4, #87] 3913; CHECK-NEXT: orr.w r0, r9, r8, lsl #4 3914; CHECK-NEXT: str.w r0, [r4, #70] 3915; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload 3916; CHECK-NEXT: and r1, r0, #15 3917; CHECK-NEXT: lsrl r8, r1, #28 3918; CHECK-NEXT: strb.w r8, [r4, #74] 3919; CHECK-NEXT: ldr r0, [sp, #48] @ 4-byte Reload 3920; CHECK-NEXT: and r0, r0, #15 3921; CHECK-NEXT: orr.w r0, r0, r2, lsl #4 3922; CHECK-NEXT: str.w r0, [r4, #62] 3923; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload 3924; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload 3925; CHECK-NEXT: orr.w r0, r0, r2, lsl #4 3926; CHECK-NEXT: str.w r0, [r4, #45] 3927; CHECK-NEXT: ldr r0, [sp, #28] @ 4-byte Reload 3928; CHECK-NEXT: and r1, r0, #15 3929; CHECK-NEXT: lsrl r2, r1, #28 3930; CHECK-NEXT: strb.w r2, [r4, #49] 3931; CHECK-NEXT: ldr r0, [sp, #52] @ 4-byte Reload 3932; CHECK-NEXT: and r0, r0, #15 3933; CHECK-NEXT: orr.w r0, r0, lr, lsl #4 3934; CHECK-NEXT: str.w r0, [r4, #37] 3935; CHECK-NEXT: ldr r2, [sp, #36] @ 4-byte Reload 3936; CHECK-NEXT: orr.w r0, r5, r2, lsl #4 3937; CHECK-NEXT: str r0, [r4, #20] 3938; CHECK-NEXT: ldr r0, [sp, #44] @ 4-byte Reload 3939; CHECK-NEXT: and r1, r0, #15 3940; CHECK-NEXT: lsrl r2, r1, #28 3941; CHECK-NEXT: strb r2, [r4, #24] 3942; CHECK-NEXT: it gt 3943; CHECK-NEXT: movgt r3, #15 3944; CHECK-NEXT: and r0, r3, #15 3945; CHECK-NEXT: orr.w r0, r0, r12, lsl #4 3946; CHECK-NEXT: str r0, [r4, #12] 3947; CHECK-NEXT: add sp, #56 3948; CHECK-NEXT: vpop {d8, d9, d10, d11, d12} 3949; CHECK-NEXT: add sp, #4 3950; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 3951; CHECK-NEXT: .p2align 2 3952; CHECK-NEXT: @ %bb.1: 3953; CHECK-NEXT: .LCPI50_0: 3954; CHECK-NEXT: .long 0x717fffff @ float 1.26765052E+30 3955 %x = call <8 x i100> @llvm.fptoui.sat.v8f16.v8i100(<8 x half> %f) 3956 ret <8 x i100> %x 3957} 3958 3959define arm_aapcs_vfpcc <8 x i128> @test_unsigned_v8f16_v8i128(<8 x half> %f) { 3960; CHECK-LABEL: test_unsigned_v8f16_v8i128: 3961; CHECK: @ %bb.0: 3962; CHECK-NEXT: .save {r4, r5, r6, r7, lr} 3963; CHECK-NEXT: push {r4, r5, r6, r7, lr} 3964; CHECK-NEXT: .pad #4 3965; CHECK-NEXT: sub sp, #4 3966; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14} 3967; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14} 3968; CHECK-NEXT: vmov q4, q0 3969; CHECK-NEXT: mov r4, r0 3970; CHECK-NEXT: vcvtt.f32.f16 s24, s19 3971; CHECK-NEXT: vcvtb.f32.f16 s22, s16 3972; CHECK-NEXT: vmov r0, s24 3973; CHECK-NEXT: vcvtb.f32.f16 s28, s19 3974; CHECK-NEXT: vldr s20, .LCPI51_0 3975; CHECK-NEXT: vmov r5, s22 3976; CHECK-NEXT: vmov r7, s28 3977; CHECK-NEXT: vcvtt.f32.f16 s26, s18 3978; CHECK-NEXT: bl __fixunssfti 3979; CHECK-NEXT: vcmp.f32 s24, #0 3980; CHECK-NEXT: add.w r12, r4, #112 3981; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3982; CHECK-NEXT: itttt lt 3983; CHECK-NEXT: movlt r0, #0 3984; CHECK-NEXT: movlt r1, #0 3985; CHECK-NEXT: movlt r2, #0 3986; CHECK-NEXT: movlt r3, #0 3987; CHECK-NEXT: vcmp.f32 s24, s20 3988; CHECK-NEXT: vcvtb.f32.f16 s18, s18 3989; CHECK-NEXT: vmrs APSR_nzcv, fpscr 3990; CHECK-NEXT: it gt 3991; CHECK-NEXT: movgt.w r3, #-1 3992; CHECK-NEXT: ittt gt 3993; CHECK-NEXT: movgt.w r2, #-1 3994; CHECK-NEXT: movgt.w r1, #-1 3995; CHECK-NEXT: movgt.w r0, #-1 3996; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3} 3997; CHECK-NEXT: mov r0, r7 3998; CHECK-NEXT: vmov r6, s26 3999; CHECK-NEXT: bl __fixunssfti 4000; CHECK-NEXT: vcmp.f32 s28, #0 4001; CHECK-NEXT: add.w r12, r4, #96 4002; CHECK-NEXT: vmrs APSR_nzcv, fpscr 4003; CHECK-NEXT: itttt lt 4004; CHECK-NEXT: movlt r0, #0 4005; CHECK-NEXT: movlt r1, #0 4006; CHECK-NEXT: movlt r2, #0 4007; CHECK-NEXT: movlt r3, #0 4008; CHECK-NEXT: vcmp.f32 s28, s20 4009; CHECK-NEXT: vcvtt.f32.f16 s24, s17 4010; CHECK-NEXT: vmrs APSR_nzcv, fpscr 4011; CHECK-NEXT: it gt 4012; CHECK-NEXT: movgt.w r3, #-1 4013; CHECK-NEXT: ittt gt 4014; CHECK-NEXT: movgt.w r2, #-1 4015; CHECK-NEXT: movgt.w r1, #-1 4016; CHECK-NEXT: movgt.w r0, #-1 4017; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3} 4018; CHECK-NEXT: mov r0, r6 4019; CHECK-NEXT: vmov r7, s18 4020; CHECK-NEXT: bl __fixunssfti 4021; CHECK-NEXT: vcmp.f32 s26, #0 4022; CHECK-NEXT: add.w r12, r4, #80 4023; CHECK-NEXT: vmrs APSR_nzcv, fpscr 4024; CHECK-NEXT: vcmp.f32 s26, s20 4025; CHECK-NEXT: itttt lt 4026; CHECK-NEXT: movlt r0, #0 4027; CHECK-NEXT: movlt r1, #0 4028; CHECK-NEXT: movlt r2, #0 4029; CHECK-NEXT: movlt r3, #0 4030; CHECK-NEXT: vmrs APSR_nzcv, fpscr 4031; CHECK-NEXT: it gt 4032; CHECK-NEXT: movgt.w r3, #-1 4033; CHECK-NEXT: ittt gt 4034; CHECK-NEXT: movgt.w r2, #-1 4035; CHECK-NEXT: movgt.w r1, #-1 4036; CHECK-NEXT: movgt.w r0, #-1 4037; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3} 4038; CHECK-NEXT: mov r0, r7 4039; CHECK-NEXT: vmov r6, s24 4040; CHECK-NEXT: vcvtb.f32.f16 s26, s17 4041; CHECK-NEXT: bl __fixunssfti 4042; CHECK-NEXT: vcmp.f32 s18, #0 4043; CHECK-NEXT: add.w r12, r4, #64 4044; CHECK-NEXT: vmrs APSR_nzcv, fpscr 4045; CHECK-NEXT: itttt lt 4046; CHECK-NEXT: movlt r0, #0 4047; CHECK-NEXT: movlt r1, #0 4048; CHECK-NEXT: movlt r2, #0 4049; CHECK-NEXT: movlt r3, #0 4050; CHECK-NEXT: vcmp.f32 s18, s20 4051; CHECK-NEXT: vcvtt.f32.f16 s16, s16 4052; CHECK-NEXT: vmrs APSR_nzcv, fpscr 4053; CHECK-NEXT: it gt 4054; CHECK-NEXT: movgt.w r3, #-1 4055; CHECK-NEXT: ittt gt 4056; CHECK-NEXT: movgt.w r2, #-1 4057; CHECK-NEXT: movgt.w r1, #-1 4058; CHECK-NEXT: movgt.w r0, #-1 4059; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3} 4060; CHECK-NEXT: mov r0, r6 4061; CHECK-NEXT: vmov r7, s26 4062; CHECK-NEXT: bl __fixunssfti 4063; CHECK-NEXT: vcmp.f32 s24, #0 4064; CHECK-NEXT: add.w r12, r4, #48 4065; CHECK-NEXT: vmrs APSR_nzcv, fpscr 4066; CHECK-NEXT: itttt lt 4067; CHECK-NEXT: movlt r0, #0 4068; CHECK-NEXT: movlt r1, #0 4069; CHECK-NEXT: movlt r2, #0 4070; CHECK-NEXT: movlt r3, #0 4071; CHECK-NEXT: vcmp.f32 s24, s20 4072; CHECK-NEXT: vmrs APSR_nzcv, fpscr 4073; CHECK-NEXT: it gt 4074; CHECK-NEXT: movgt.w r3, #-1 4075; CHECK-NEXT: ittt gt 4076; CHECK-NEXT: movgt.w r2, #-1 4077; CHECK-NEXT: movgt.w r1, #-1 4078; CHECK-NEXT: movgt.w r0, #-1 4079; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3} 4080; CHECK-NEXT: mov r0, r7 4081; CHECK-NEXT: vmov r6, s16 4082; CHECK-NEXT: bl __fixunssfti 4083; CHECK-NEXT: vcmp.f32 s26, #0 4084; CHECK-NEXT: add.w r12, r4, #32 4085; CHECK-NEXT: vmrs APSR_nzcv, fpscr 4086; CHECK-NEXT: itttt lt 4087; CHECK-NEXT: movlt r0, #0 4088; CHECK-NEXT: movlt r1, #0 4089; CHECK-NEXT: movlt r2, #0 4090; CHECK-NEXT: movlt r3, #0 4091; CHECK-NEXT: vcmp.f32 s26, s20 4092; CHECK-NEXT: vmrs APSR_nzcv, fpscr 4093; CHECK-NEXT: itttt gt 4094; CHECK-NEXT: movgt.w r3, #-1 4095; CHECK-NEXT: movgt.w r2, #-1 4096; CHECK-NEXT: movgt.w r1, #-1 4097; CHECK-NEXT: movgt.w r0, #-1 4098; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3} 4099; CHECK-NEXT: mov r0, r6 4100; CHECK-NEXT: bl __fixunssfti 4101; CHECK-NEXT: vcmp.f32 s16, #0 4102; CHECK-NEXT: add.w r12, r4, #16 4103; CHECK-NEXT: vmrs APSR_nzcv, fpscr 4104; CHECK-NEXT: itttt lt 4105; CHECK-NEXT: movlt r0, #0 4106; CHECK-NEXT: movlt r1, #0 4107; CHECK-NEXT: movlt r2, #0 4108; CHECK-NEXT: movlt r3, #0 4109; CHECK-NEXT: vcmp.f32 s16, s20 4110; CHECK-NEXT: vmrs APSR_nzcv, fpscr 4111; CHECK-NEXT: itttt gt 4112; CHECK-NEXT: movgt.w r3, #-1 4113; CHECK-NEXT: movgt.w r2, #-1 4114; CHECK-NEXT: movgt.w r1, #-1 4115; CHECK-NEXT: movgt.w r0, #-1 4116; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3} 4117; CHECK-NEXT: mov r0, r5 4118; CHECK-NEXT: bl __fixunssfti 4119; CHECK-NEXT: vcmp.f32 s22, #0 4120; CHECK-NEXT: vmrs APSR_nzcv, fpscr 4121; CHECK-NEXT: itttt lt 4122; CHECK-NEXT: movlt r0, #0 4123; CHECK-NEXT: movlt r1, #0 4124; CHECK-NEXT: movlt r2, #0 4125; CHECK-NEXT: movlt r3, #0 4126; CHECK-NEXT: vcmp.f32 s22, s20 4127; CHECK-NEXT: vmrs APSR_nzcv, fpscr 4128; CHECK-NEXT: itttt gt 4129; CHECK-NEXT: movgt.w r3, #-1 4130; CHECK-NEXT: movgt.w r2, #-1 4131; CHECK-NEXT: movgt.w r1, #-1 4132; CHECK-NEXT: movgt.w r0, #-1 4133; CHECK-NEXT: stm r4!, {r0, r1, r2, r3} 4134; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14} 4135; CHECK-NEXT: add sp, #4 4136; CHECK-NEXT: pop {r4, r5, r6, r7, pc} 4137; CHECK-NEXT: .p2align 2 4138; CHECK-NEXT: @ %bb.1: 4139; CHECK-NEXT: .LCPI51_0: 4140; CHECK-NEXT: .long 0x7f7fffff @ float 3.40282347E+38 4141 %x = call <8 x i128> @llvm.fptoui.sat.v8f16.v8i128(<8 x half> %f) 4142 ret <8 x i128> %x 4143} 4144 4145