xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-ctpop.ll (revision 7b3bbd83c0c24087072ec5b22a76799ab31f87d5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; NOTE: Assertions have been autoenerated by utils/update_llc_test_checks.py
3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
4
5define arm_aapcs_vfpcc <2 x i64> @ctpop_2i64_t(<2 x i64> %src){
6; CHECK-LABEL: ctpop_2i64_t:
7; CHECK:       @ %bb.0: @ %entry
8; CHECK-NEXT:    .save {r4, r5, r7, lr}
9; CHECK-NEXT:    push {r4, r5, r7, lr}
10; CHECK-NEXT:    vmov r1, r2, d1
11; CHECK-NEXT:    mov.w lr, #1431655765
12; CHECK-NEXT:    vmov r3, r4, d0
13; CHECK-NEXT:    mov.w r12, #858993459
14; CHECK-NEXT:    vldr s1, .LCPI0_0
15; CHECK-NEXT:    vmov.f32 s3, s1
16; CHECK-NEXT:    and.w r0, lr, r2, lsr #1
17; CHECK-NEXT:    subs r0, r2, r0
18; CHECK-NEXT:    and.w r2, r12, r0, lsr #2
19; CHECK-NEXT:    bic r0, r0, #-858993460
20; CHECK-NEXT:    add r0, r2
21; CHECK-NEXT:    and.w r2, lr, r1, lsr #1
22; CHECK-NEXT:    subs r1, r1, r2
23; CHECK-NEXT:    add.w r0, r0, r0, lsr #4
24; CHECK-NEXT:    and.w r2, r12, r1, lsr #2
25; CHECK-NEXT:    bic r1, r1, #-858993460
26; CHECK-NEXT:    add r1, r2
27; CHECK-NEXT:    and.w r2, lr, r3, lsr #1
28; CHECK-NEXT:    subs r2, r3, r2
29; CHECK-NEXT:    bic r5, r0, #-252645136
30; CHECK-NEXT:    add.w r1, r1, r1, lsr #4
31; CHECK-NEXT:    mov.w r0, #16843009
32; CHECK-NEXT:    and.w r3, r12, r2, lsr #2
33; CHECK-NEXT:    bic r2, r2, #-858993460
34; CHECK-NEXT:    add r2, r3
35; CHECK-NEXT:    and.w r3, lr, r4, lsr #1
36; CHECK-NEXT:    subs r3, r4, r3
37; CHECK-NEXT:    bic r1, r1, #-252645136
38; CHECK-NEXT:    add.w r2, r2, r2, lsr #4
39; CHECK-NEXT:    muls r5, r0, r5
40; CHECK-NEXT:    and.w r4, r12, r3, lsr #2
41; CHECK-NEXT:    bic r3, r3, #-858993460
42; CHECK-NEXT:    bic r2, r2, #-252645136
43; CHECK-NEXT:    add r3, r4
44; CHECK-NEXT:    muls r1, r0, r1
45; CHECK-NEXT:    add.w r3, r3, r3, lsr #4
46; CHECK-NEXT:    muls r2, r0, r2
47; CHECK-NEXT:    bic r3, r3, #-252645136
48; CHECK-NEXT:    muls r0, r3, r0
49; CHECK-NEXT:    lsrs r1, r1, #24
50; CHECK-NEXT:    add.w r1, r1, r5, lsr #24
51; CHECK-NEXT:    lsrs r2, r2, #24
52; CHECK-NEXT:    vmov s2, r1
53; CHECK-NEXT:    add.w r0, r2, r0, lsr #24
54; CHECK-NEXT:    vmov s0, r0
55; CHECK-NEXT:    pop {r4, r5, r7, pc}
56; CHECK-NEXT:    .p2align 2
57; CHECK-NEXT:  @ %bb.1:
58; CHECK-NEXT:  .LCPI0_0:
59; CHECK-NEXT:    .long 0x00000000 @ float 0
60entry:
61  %0 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %src)
62  ret <2 x i64> %0
63}
64
65define arm_aapcs_vfpcc <4 x i32> @ctpop_4i32_t(<4 x i32> %src){
66; CHECK-LABEL: ctpop_4i32_t:
67; CHECK:       @ %bb.0: @ %entry
68; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
69; CHECK-NEXT:    vpush {d8, d9, d10, d11}
70; CHECK-NEXT:    vmov.i8 q4, #0x55
71; CHECK-NEXT:    vshr.u32 q5, q0, #1
72; CHECK-NEXT:    vand q4, q5, q4
73; CHECK-NEXT:    vmov.i8 q3, #0x33
74; CHECK-NEXT:    vsub.i32 q0, q0, q4
75; CHECK-NEXT:    vmov.i8 q2, #0xf
76; CHECK-NEXT:    vshr.u32 q4, q0, #2
77; CHECK-NEXT:    vand q0, q0, q3
78; CHECK-NEXT:    vand q4, q4, q3
79; CHECK-NEXT:    vmov.i8 q1, #0x1
80; CHECK-NEXT:    vadd.i32 q0, q0, q4
81; CHECK-NEXT:    vshr.u32 q3, q0, #4
82; CHECK-NEXT:    vadd.i32 q0, q0, q3
83; CHECK-NEXT:    vand q0, q0, q2
84; CHECK-NEXT:    vmul.i32 q0, q0, q1
85; CHECK-NEXT:    vshr.u32 q0, q0, #24
86; CHECK-NEXT:    vpop {d8, d9, d10, d11}
87; CHECK-NEXT:    bx lr
88entry:
89  %0 = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %src)
90  ret <4 x i32> %0
91}
92
93define arm_aapcs_vfpcc <8 x i16> @ctpop_8i16_t(<8 x i16> %src){
94; CHECK-LABEL: ctpop_8i16_t:
95; CHECK:       @ %bb.0: @ %entry
96; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
97; CHECK-NEXT:    vpush {d8, d9, d10, d11}
98; CHECK-NEXT:    vmov.i8 q4, #0x55
99; CHECK-NEXT:    vshr.u16 q5, q0, #1
100; CHECK-NEXT:    vand q4, q5, q4
101; CHECK-NEXT:    vmov.i8 q3, #0x33
102; CHECK-NEXT:    vsub.i16 q0, q0, q4
103; CHECK-NEXT:    vmov.i8 q2, #0xf
104; CHECK-NEXT:    vshr.u16 q4, q0, #2
105; CHECK-NEXT:    vand q0, q0, q3
106; CHECK-NEXT:    vand q4, q4, q3
107; CHECK-NEXT:    vmov.i8 q1, #0x1
108; CHECK-NEXT:    vadd.i16 q0, q0, q4
109; CHECK-NEXT:    vshr.u16 q3, q0, #4
110; CHECK-NEXT:    vadd.i16 q0, q0, q3
111; CHECK-NEXT:    vand q0, q0, q2
112; CHECK-NEXT:    vmul.i16 q0, q0, q1
113; CHECK-NEXT:    vshr.u16 q0, q0, #8
114; CHECK-NEXT:    vpop {d8, d9, d10, d11}
115; CHECK-NEXT:    bx lr
116entry:
117  %0 = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %src)
118  ret <8 x i16> %0
119}
120
121define arm_aapcs_vfpcc <16 x i8> @ctpop_16i8_t(<16 x i8> %src){
122; CHECK-LABEL: ctpop_16i8_t:
123; CHECK:       @ %bb.0: @ %entry
124; CHECK-NEXT:    .vsave {d8, d9}
125; CHECK-NEXT:    vpush {d8, d9}
126; CHECK-NEXT:    vmov.i8 q3, #0x55
127; CHECK-NEXT:    vshr.u8 q4, q0, #1
128; CHECK-NEXT:    vand q3, q4, q3
129; CHECK-NEXT:    vmov.i8 q2, #0x33
130; CHECK-NEXT:    vsub.i8 q0, q0, q3
131; CHECK-NEXT:    vmov.i8 q1, #0xf
132; CHECK-NEXT:    vshr.u8 q3, q0, #2
133; CHECK-NEXT:    vand q0, q0, q2
134; CHECK-NEXT:    vand q3, q3, q2
135; CHECK-NEXT:    vadd.i8 q0, q0, q3
136; CHECK-NEXT:    vshr.u8 q2, q0, #4
137; CHECK-NEXT:    vadd.i8 q0, q0, q2
138; CHECK-NEXT:    vand q0, q0, q1
139; CHECK-NEXT:    vpop {d8, d9}
140; CHECK-NEXT:    bx lr
141entry:
142  %0 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %src)
143  ret <16 x i8> %0
144}
145
146declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
147declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)
148declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>)
149declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)
150