1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s 3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -early-live-intervals -verify-machineinstrs -o - | FileCheck %s 4 5define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_0_t(<2 x i64> %src){ 6; CHECK-LABEL: ctlz_2i64_0_t: 7; CHECK: @ %bb.0: @ %entry 8; CHECK-NEXT: vmov r0, r1, d1 9; CHECK-NEXT: clz r0, r0 10; CHECK-NEXT: cmp r1, #0 11; CHECK-NEXT: add.w r0, r0, #32 12; CHECK-NEXT: it ne 13; CHECK-NEXT: clzne r0, r1 14; CHECK-NEXT: vmov s2, r0 15; CHECK-NEXT: vmov r0, r1, d0 16; CHECK-NEXT: vldr s1, .LCPI0_0 17; CHECK-NEXT: vmov.f32 s3, s1 18; CHECK-NEXT: clz r0, r0 19; CHECK-NEXT: cmp r1, #0 20; CHECK-NEXT: add.w r0, r0, #32 21; CHECK-NEXT: it ne 22; CHECK-NEXT: clzne r0, r1 23; CHECK-NEXT: vmov s0, r0 24; CHECK-NEXT: bx lr 25; CHECK-NEXT: .p2align 2 26; CHECK-NEXT: @ %bb.1: 27; CHECK-NEXT: .LCPI0_0: 28; CHECK-NEXT: .long 0x00000000 @ float 0 29entry: 30 %0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 0) 31 ret <2 x i64> %0 32} 33 34define arm_aapcs_vfpcc <4 x i32> @ctlz_4i32_0_t(<4 x i32> %src){ 35; CHECK-LABEL: ctlz_4i32_0_t: 36; CHECK: @ %bb.0: @ %entry 37; CHECK-NEXT: vclz.i32 q0, q0 38; CHECK-NEXT: bx lr 39entry: 40 %0 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 0) 41 ret <4 x i32> %0 42} 43 44define arm_aapcs_vfpcc <8 x i16> @ctlz_8i16_0_t(<8 x i16> %src){ 45; CHECK-LABEL: ctlz_8i16_0_t: 46; CHECK: @ %bb.0: @ %entry 47; CHECK-NEXT: vclz.i16 q0, q0 48; CHECK-NEXT: bx lr 49entry: 50 %0 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 0) 51 ret <8 x i16> %0 52} 53 54define arm_aapcs_vfpcc <16 x i8> @ctlz_16i8_0_t(<16 x i8> %src){ 55; CHECK-LABEL: ctlz_16i8_0_t: 56; CHECK: @ %bb.0: @ %entry 57; CHECK-NEXT: vclz.i8 q0, q0 58; CHECK-NEXT: bx lr 59entry: 60 %0 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 0) 61 ret <16 x i8> %0 62} 63 64define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_1_t(<2 x i64> %src){ 65; CHECK-LABEL: ctlz_2i64_1_t: 66; CHECK: @ %bb.0: @ %entry 67; CHECK-NEXT: vmov r0, r1, d1 68; CHECK-NEXT: clz r0, r0 69; CHECK-NEXT: cmp r1, #0 70; CHECK-NEXT: add.w r0, r0, #32 71; CHECK-NEXT: it ne 72; CHECK-NEXT: clzne r0, r1 73; CHECK-NEXT: vmov s2, r0 74; CHECK-NEXT: vmov r0, r1, d0 75; CHECK-NEXT: vldr s1, .LCPI4_0 76; CHECK-NEXT: vmov.f32 s3, s1 77; CHECK-NEXT: clz r0, r0 78; CHECK-NEXT: cmp r1, #0 79; CHECK-NEXT: add.w r0, r0, #32 80; CHECK-NEXT: it ne 81; CHECK-NEXT: clzne r0, r1 82; CHECK-NEXT: vmov s0, r0 83; CHECK-NEXT: bx lr 84; CHECK-NEXT: .p2align 2 85; CHECK-NEXT: @ %bb.1: 86; CHECK-NEXT: .LCPI4_0: 87; CHECK-NEXT: .long 0x00000000 @ float 0 88entry: 89 %0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 1) 90 ret <2 x i64> %0 91} 92 93define arm_aapcs_vfpcc <4 x i32> @ctlz_4i32_1_t(<4 x i32> %src){ 94; CHECK-LABEL: ctlz_4i32_1_t: 95; CHECK: @ %bb.0: @ %entry 96; CHECK-NEXT: vclz.i32 q0, q0 97; CHECK-NEXT: bx lr 98entry: 99 %0 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 1) 100 ret <4 x i32> %0 101} 102 103define arm_aapcs_vfpcc <8 x i16> @ctlz_8i16_1_t(<8 x i16> %src){ 104; CHECK-LABEL: ctlz_8i16_1_t: 105; CHECK: @ %bb.0: @ %entry 106; CHECK-NEXT: vclz.i16 q0, q0 107; CHECK-NEXT: bx lr 108entry: 109 %0 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 1) 110 ret <8 x i16> %0 111} 112 113define arm_aapcs_vfpcc <16 x i8> @ctlz_16i8_1_t(<16 x i8> %src){ 114; CHECK-LABEL: ctlz_16i8_1_t: 115; CHECK: @ %bb.0: @ %entry 116; CHECK-NEXT: vclz.i8 q0, q0 117; CHECK-NEXT: bx lr 118entry: 119 %0 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 1) 120 ret <16 x i8> %0 121} 122 123 124declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) 125declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) 126declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) 127declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) 128