xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-i64-add.ll (revision 8998ff53c91687b1065d095f6ac0ad7578131d73) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s --mattr=+mve -o - --verify-machineinstrs | FileCheck %s
3
4target triple = "thumbv8.1m.main-none-none-eabi"
5
6
7; Expected to not transform
8define arm_aapcs_vfpcc <2 x i64> @complex_add_v2i64(<2 x i64> %a, <2 x i64> %b) {
9; CHECK-LABEL: complex_add_v2i64:
10; CHECK:       @ %bb.0: @ %entry
11; CHECK-NEXT:    .save {r7, lr}
12; CHECK-NEXT:    push {r7, lr}
13; CHECK-NEXT:    vmov r0, r1, d0
14; CHECK-NEXT:    vmov r2, r3, d3
15; CHECK-NEXT:    adds.w lr, r2, r0
16; CHECK-NEXT:    adc.w r12, r3, r1
17; CHECK-NEXT:    vmov r2, r3, d1
18; CHECK-NEXT:    vmov r1, r0, d2
19; CHECK-NEXT:    subs r1, r1, r2
20; CHECK-NEXT:    vmov q0[2], q0[0], r1, lr
21; CHECK-NEXT:    sbcs r0, r3
22; CHECK-NEXT:    vmov q0[3], q0[1], r0, r12
23; CHECK-NEXT:    pop {r7, pc}
24entry:
25  %a.real = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <1 x i32> <i32 0>
26  %a.imag = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <1 x i32> <i32 1>
27  %b.real = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <1 x i32> <i32 0>
28  %b.imag = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <1 x i32> <i32 1>
29  %0 = sub <1 x i64> %b.real, %a.imag
30  %1 = add <1 x i64> %b.imag, %a.real
31  %interleaved.vec = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>
32  ret <2 x i64> %interleaved.vec
33}
34
35; Expected to not transform
36define arm_aapcs_vfpcc <4 x i64> @complex_add_v4i64(<4 x i64> %a, <4 x i64> %b) {
37; CHECK-LABEL: complex_add_v4i64:
38; CHECK:       @ %bb.0: @ %entry
39; CHECK-NEXT:    .save {r7, lr}
40; CHECK-NEXT:    push {r7, lr}
41; CHECK-NEXT:    .vsave {d8, d9}
42; CHECK-NEXT:    vpush {d8, d9}
43; CHECK-NEXT:    vmov q4, q1
44; CHECK-NEXT:    vmov r2, r3, d7
45; CHECK-NEXT:    vmov r0, r1, d8
46; CHECK-NEXT:    adds.w lr, r2, r0
47; CHECK-NEXT:    adc.w r12, r3, r1
48; CHECK-NEXT:    vmov r2, r3, d0
49; CHECK-NEXT:    vmov r1, r0, d5
50; CHECK-NEXT:    adds r1, r1, r2
51; CHECK-NEXT:    adcs r0, r3
52; CHECK-NEXT:    vmov q1[2], q1[0], r1, lr
53; CHECK-NEXT:    vmov q1[3], q1[1], r0, r12
54; CHECK-NEXT:    vmov r0, r1, d9
55; CHECK-NEXT:    vmov r2, r3, d6
56; CHECK-NEXT:    subs.w lr, r2, r0
57; CHECK-NEXT:    sbc.w r12, r3, r1
58; CHECK-NEXT:    vmov r2, r3, d1
59; CHECK-NEXT:    vmov r1, r0, d4
60; CHECK-NEXT:    vmov.f32 s2, s4
61; CHECK-NEXT:    vmov.f32 s3, s5
62; CHECK-NEXT:    subs r1, r1, r2
63; CHECK-NEXT:    vmov q2[2], q2[0], r1, lr
64; CHECK-NEXT:    sbcs r0, r3
65; CHECK-NEXT:    vmov q2[3], q2[1], r0, r12
66; CHECK-NEXT:    vmov.f32 s0, s8
67; CHECK-NEXT:    vmov.f32 s4, s10
68; CHECK-NEXT:    vmov.f32 s1, s9
69; CHECK-NEXT:    vmov.f32 s5, s11
70; CHECK-NEXT:    vpop {d8, d9}
71; CHECK-NEXT:    pop {r7, pc}
72entry:
73  %a.real = shufflevector <4 x i64> %a, <4 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>
74  %a.imag = shufflevector <4 x i64> %a, <4 x i64> zeroinitializer, <2 x i32> <i32 1, i32 3>
75  %b.real = shufflevector <4 x i64> %b, <4 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>
76  %b.imag = shufflevector <4 x i64> %b, <4 x i64> zeroinitializer, <2 x i32> <i32 1, i32 3>
77  %0 = sub <2 x i64> %b.real, %a.imag
78  %1 = add <2 x i64> %b.imag, %a.real
79  %interleaved.vec = shufflevector <2 x i64> %0, <2 x i64> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
80  ret <4 x i64> %interleaved.vec
81}
82
83; Expected to not transform
84define arm_aapcs_vfpcc <8 x i64> @complex_add_v8i64(<8 x i64> %a, <8 x i64> %b) {
85; CHECK-LABEL: complex_add_v8i64:
86; CHECK:       @ %bb.0: @ %entry
87; CHECK-NEXT:    .save {r7, lr}
88; CHECK-NEXT:    push {r7, lr}
89; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}
90; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13}
91; CHECK-NEXT:    add r2, sp, #72
92; CHECK-NEXT:    vmov q4, q1
93; CHECK-NEXT:    vldrw.u32 q5, [r2]
94; CHECK-NEXT:    vmov r0, r1, d8
95; CHECK-NEXT:    vmov r2, r3, d11
96; CHECK-NEXT:    adds.w lr, r2, r0
97; CHECK-NEXT:    adc.w r12, r3, r1
98; CHECK-NEXT:    add r1, sp, #56
99; CHECK-NEXT:    vldrw.u32 q6, [r1]
100; CHECK-NEXT:    vmov r2, r3, d0
101; CHECK-NEXT:    vmov r1, r0, d13
102; CHECK-NEXT:    adds r1, r1, r2
103; CHECK-NEXT:    adcs r0, r3
104; CHECK-NEXT:    vmov q1[2], q1[0], r1, lr
105; CHECK-NEXT:    vmov q1[3], q1[1], r0, r12
106; CHECK-NEXT:    vmov r0, r1, d9
107; CHECK-NEXT:    vmov r2, r3, d10
108; CHECK-NEXT:    subs.w lr, r2, r0
109; CHECK-NEXT:    sbc.w r12, r3, r1
110; CHECK-NEXT:    vmov r2, r3, d1
111; CHECK-NEXT:    vmov r1, r0, d12
112; CHECK-NEXT:    vmov.f32 s2, s4
113; CHECK-NEXT:    vmov.f32 s3, s5
114; CHECK-NEXT:    subs r1, r1, r2
115; CHECK-NEXT:    add r2, sp, #104
116; CHECK-NEXT:    vldrw.u32 q5, [r2]
117; CHECK-NEXT:    sbcs r0, r3
118; CHECK-NEXT:    vmov q4[2], q4[0], r1, lr
119; CHECK-NEXT:    vmov q4[3], q4[1], r0, r12
120; CHECK-NEXT:    vmov r0, r1, d6
121; CHECK-NEXT:    vmov r2, r3, d11
122; CHECK-NEXT:    vmov.f32 s0, s16
123; CHECK-NEXT:    vmov.f32 s4, s18
124; CHECK-NEXT:    vmov.f32 s1, s17
125; CHECK-NEXT:    vmov.f32 s5, s19
126; CHECK-NEXT:    adds.w lr, r2, r0
127; CHECK-NEXT:    adc.w r12, r3, r1
128; CHECK-NEXT:    add r1, sp, #88
129; CHECK-NEXT:    vldrw.u32 q6, [r1]
130; CHECK-NEXT:    vmov r2, r3, d4
131; CHECK-NEXT:    vmov r1, r0, d13
132; CHECK-NEXT:    adds r1, r1, r2
133; CHECK-NEXT:    adcs r0, r3
134; CHECK-NEXT:    vmov q4[2], q4[0], r1, lr
135; CHECK-NEXT:    vmov q4[3], q4[1], r0, r12
136; CHECK-NEXT:    vmov r0, r1, d7
137; CHECK-NEXT:    vmov r2, r3, d10
138; CHECK-NEXT:    subs.w lr, r2, r0
139; CHECK-NEXT:    sbc.w r12, r3, r1
140; CHECK-NEXT:    vmov r2, r3, d5
141; CHECK-NEXT:    vmov r1, r0, d12
142; CHECK-NEXT:    vmov.f32 s10, s16
143; CHECK-NEXT:    vmov.f32 s11, s17
144; CHECK-NEXT:    subs r1, r1, r2
145; CHECK-NEXT:    vmov q3[2], q3[0], r1, lr
146; CHECK-NEXT:    sbcs r0, r3
147; CHECK-NEXT:    vmov q3[3], q3[1], r0, r12
148; CHECK-NEXT:    vmov.f32 s16, s14
149; CHECK-NEXT:    vmov.f32 s8, s12
150; CHECK-NEXT:    vmov.f32 s17, s15
151; CHECK-NEXT:    vmov.f32 s9, s13
152; CHECK-NEXT:    vmov q3, q4
153; CHECK-NEXT:    vpop {d8, d9, d10, d11, d12, d13}
154; CHECK-NEXT:    pop {r7, pc}
155entry:
156  %a.real = shufflevector <8 x i64> %a, <8 x i64> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
157  %a.imag = shufflevector <8 x i64> %a, <8 x i64> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
158  %b.real = shufflevector <8 x i64> %b, <8 x i64> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
159  %b.imag = shufflevector <8 x i64> %b, <8 x i64> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
160  %0 = sub <4 x i64> %b.real, %a.imag
161  %1 = add <4 x i64> %b.imag, %a.real
162  %interleaved.vec = shufflevector <4 x i64> %0, <4 x i64> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
163  ret <8 x i64> %interleaved.vec
164}
165