xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-i32-add.ll (revision a3dc5b534a80c1b6d2a22c4bb8710f89d034d63d) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s --mattr=+mve -o - | FileCheck %s
3
4target triple = "thumbv8.1m.main-none-none-eabi"
5
6
7; Expected to not transform
8define arm_aapcs_vfpcc <2 x i32> @complex_add_v2i32(<2 x i32> %a, <2 x i32> %b) {
9; CHECK-LABEL: complex_add_v2i32:
10; CHECK:       @ %bb.0: @ %entry
11; CHECK-NEXT:    vmov r0, s0
12; CHECK-NEXT:    vmov r1, s6
13; CHECK-NEXT:    vmov r2, s4
14; CHECK-NEXT:    add r0, r1
15; CHECK-NEXT:    vmov r1, s2
16; CHECK-NEXT:    subs r1, r2, r1
17; CHECK-NEXT:    vmov q0[2], q0[0], r1, r0
18; CHECK-NEXT:    bx lr
19entry:
20  %a.real = shufflevector <2 x i32> %a, <2 x i32> zeroinitializer, <1 x i32> <i32 0>
21  %a.imag = shufflevector <2 x i32> %a, <2 x i32> zeroinitializer, <1 x i32> <i32 1>
22  %b.real = shufflevector <2 x i32> %b, <2 x i32> zeroinitializer, <1 x i32> <i32 0>
23  %b.imag = shufflevector <2 x i32> %b, <2 x i32> zeroinitializer, <1 x i32> <i32 1>
24  %0 = sub <1 x i32> %b.real, %a.imag
25  %1 = add <1 x i32> %b.imag, %a.real
26  %interleaved.vec = shufflevector <1 x i32> %0, <1 x i32> %1, <2 x i32> <i32 0, i32 1>
27  ret <2 x i32> %interleaved.vec
28}
29
30; Expected to transform
31define arm_aapcs_vfpcc <4 x i32> @complex_add_v4i32(<4 x i32> %a, <4 x i32> %b) {
32; CHECK-LABEL: complex_add_v4i32:
33; CHECK:       @ %bb.0: @ %entry
34; CHECK-NEXT:    vcadd.i32 q2, q1, q0, #90
35; CHECK-NEXT:    vmov q0, q2
36; CHECK-NEXT:    bx lr
37entry:
38  %a.real = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <2 x i32> <i32 0, i32 2>
39  %a.imag = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <2 x i32> <i32 1, i32 3>
40  %b.real = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <2 x i32> <i32 0, i32 2>
41  %b.imag = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <2 x i32> <i32 1, i32 3>
42  %0 = sub <2 x i32> %b.real, %a.imag
43  %1 = add <2 x i32> %b.imag, %a.real
44  %interleaved.vec = shufflevector <2 x i32> %0, <2 x i32> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
45  ret <4 x i32> %interleaved.vec
46}
47
48; Expected to transform
49define arm_aapcs_vfpcc <8 x i32> @complex_add_v8i32(<8 x i32> %a, <8 x i32> %b) {
50; CHECK-LABEL: complex_add_v8i32:
51; CHECK:       @ %bb.0: @ %entry
52; CHECK-NEXT:    .vsave {d8, d9}
53; CHECK-NEXT:    vpush {d8, d9}
54; CHECK-NEXT:    vcadd.i32 q4, q2, q0, #90
55; CHECK-NEXT:    vcadd.i32 q2, q3, q1, #90
56; CHECK-NEXT:    vmov q0, q4
57; CHECK-NEXT:    vmov q1, q2
58; CHECK-NEXT:    vpop {d8, d9}
59; CHECK-NEXT:    bx lr
60entry:
61  %a.real = shufflevector <8 x i32> %a, <8 x i32> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
62  %a.imag = shufflevector <8 x i32> %a, <8 x i32> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
63  %b.real = shufflevector <8 x i32> %b, <8 x i32> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
64  %b.imag = shufflevector <8 x i32> %b, <8 x i32> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
65  %0 = sub <4 x i32> %b.real, %a.imag
66  %1 = add <4 x i32> %b.imag, %a.real
67  %interleaved.vec = shufflevector <4 x i32> %0, <4 x i32> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
68  ret <8 x i32> %interleaved.vec
69}
70
71; Expected to transform
72define arm_aapcs_vfpcc <16 x i32> @complex_add_v16i32(<16 x i32> %a, <16 x i32> %b) {
73; CHECK-LABEL: complex_add_v16i32:
74; CHECK:       @ %bb.0: @ %entry
75; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
76; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}
77; CHECK-NEXT:    add r0, sp, #64
78; CHECK-NEXT:    vldrw.u32 q5, [r0]
79; CHECK-NEXT:    add r0, sp, #80
80; CHECK-NEXT:    vcadd.i32 q4, q5, q0, #90
81; CHECK-NEXT:    vldrw.u32 q0, [r0]
82; CHECK-NEXT:    add r0, sp, #96
83; CHECK-NEXT:    vcadd.i32 q5, q0, q1, #90
84; CHECK-NEXT:    vldrw.u32 q0, [r0]
85; CHECK-NEXT:    add r0, sp, #112
86; CHECK-NEXT:    vmov q1, q5
87; CHECK-NEXT:    vcadd.i32 q6, q0, q2, #90
88; CHECK-NEXT:    vldrw.u32 q0, [r0]
89; CHECK-NEXT:    vmov q2, q6
90; CHECK-NEXT:    vcadd.i32 q7, q0, q3, #90
91; CHECK-NEXT:    vmov q0, q4
92; CHECK-NEXT:    vmov q3, q7
93; CHECK-NEXT:    vpop {d8, d9, d10, d11, d12, d13, d14, d15}
94; CHECK-NEXT:    bx lr
95entry:
96  %a.real = shufflevector <16 x i32> %a, <16 x i32> zeroinitializer, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
97  %a.imag = shufflevector <16 x i32> %a, <16 x i32> zeroinitializer, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
98  %b.real = shufflevector <16 x i32> %b, <16 x i32> zeroinitializer, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
99  %b.imag = shufflevector <16 x i32> %b, <16 x i32> zeroinitializer, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
100  %0 = sub <8 x i32> %b.real, %a.imag
101  %1 = add <8 x i32> %b.imag, %a.real
102  %interleaved.vec = shufflevector <8 x i32> %0, <8 x i32> %1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
103  ret <16 x i32> %interleaved.vec
104}
105
106; Expected to transform
107define arm_aapcs_vfpcc <32 x i32> @complex_add_v32i32(<32 x i32> %a, <32 x i32> %b) {
108; CHECK-LABEL: complex_add_v32i32:
109; CHECK:       @ %bb.0: @ %entry
110; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}
111; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13}
112; CHECK-NEXT:    add r1, sp, #96
113; CHECK-NEXT:    vldrw.u32 q4, [r1]
114; CHECK-NEXT:    add r1, sp, #224
115; CHECK-NEXT:    vldrw.u32 q5, [r1]
116; CHECK-NEXT:    add r1, sp, #80
117; CHECK-NEXT:    vcadd.i32 q6, q5, q4, #90
118; CHECK-NEXT:    vldrw.u32 q4, [r1]
119; CHECK-NEXT:    add r1, sp, #208
120; CHECK-NEXT:    vstrw.32 q6, [r0, #112]
121; CHECK-NEXT:    vldrw.u32 q5, [r1]
122; CHECK-NEXT:    add r1, sp, #64
123; CHECK-NEXT:    vcadd.i32 q6, q5, q4, #90
124; CHECK-NEXT:    vldrw.u32 q4, [r1]
125; CHECK-NEXT:    add r1, sp, #192
126; CHECK-NEXT:    vstrw.32 q6, [r0, #96]
127; CHECK-NEXT:    vldrw.u32 q5, [r1]
128; CHECK-NEXT:    add r1, sp, #48
129; CHECK-NEXT:    vcadd.i32 q6, q5, q4, #90
130; CHECK-NEXT:    vldrw.u32 q4, [r1]
131; CHECK-NEXT:    add r1, sp, #176
132; CHECK-NEXT:    vstrw.32 q6, [r0, #80]
133; CHECK-NEXT:    vldrw.u32 q5, [r1]
134; CHECK-NEXT:    add r1, sp, #160
135; CHECK-NEXT:    vcadd.i32 q6, q5, q4, #90
136; CHECK-NEXT:    vldrw.u32 q4, [r1]
137; CHECK-NEXT:    add r1, sp, #144
138; CHECK-NEXT:    vstrw.32 q6, [r0, #64]
139; CHECK-NEXT:    vcadd.i32 q5, q4, q3, #90
140; CHECK-NEXT:    vldrw.u32 q3, [r1]
141; CHECK-NEXT:    add r1, sp, #128
142; CHECK-NEXT:    vstrw.32 q5, [r0, #48]
143; CHECK-NEXT:    vcadd.i32 q4, q3, q2, #90
144; CHECK-NEXT:    vldrw.u32 q2, [r1]
145; CHECK-NEXT:    add r1, sp, #112
146; CHECK-NEXT:    vstrw.32 q4, [r0, #32]
147; CHECK-NEXT:    vcadd.i32 q3, q2, q1, #90
148; CHECK-NEXT:    vldrw.u32 q1, [r1]
149; CHECK-NEXT:    vstrw.32 q3, [r0, #16]
150; CHECK-NEXT:    vcadd.i32 q2, q1, q0, #90
151; CHECK-NEXT:    vstrw.32 q2, [r0]
152; CHECK-NEXT:    vpop {d8, d9, d10, d11, d12, d13}
153; CHECK-NEXT:    bx lr
154entry:
155  %a.real = shufflevector <32 x i32> %a, <32 x i32> zeroinitializer, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
156  %a.imag = shufflevector <32 x i32> %a, <32 x i32> zeroinitializer, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
157  %b.real = shufflevector <32 x i32> %b, <32 x i32> zeroinitializer, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
158  %b.imag = shufflevector <32 x i32> %b, <32 x i32> zeroinitializer, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
159  %0 = sub <16 x i32> %b.real, %a.imag
160  %1 = add <16 x i32> %b.imag, %a.real
161  %interleaved.vec = shufflevector <16 x i32> %0, <16 x i32> %1, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
162  ret <32 x i32> %interleaved.vec
163}
164