xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f32-add.ll (revision d52e2839f3b1a21d4a6090ccff6f4b7f1f89a1b3) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s --mattr=+mve.fp -o - | FileCheck %s
3
4target triple = "thumbv8.1m.main-none-none-eabi"
5
6
7; Expected to not transform
8define arm_aapcs_vfpcc <2 x float> @complex_add_v2f32(<2 x float> %a, <2 x float> %b) {
9; CHECK-LABEL: complex_add_v2f32:
10; CHECK:       @ %bb.0: @ %entry
11; CHECK-NEXT:    vadd.f32 s5, s5, s0
12; CHECK-NEXT:    vsub.f32 s4, s4, s1
13; CHECK-NEXT:    vmov q0, q1
14; CHECK-NEXT:    bx lr
15entry:
16  %a.real = shufflevector <2 x float> %a, <2 x float> zeroinitializer, <1 x i32> <i32 0>
17  %a.imag = shufflevector <2 x float> %a, <2 x float> zeroinitializer, <1 x i32> <i32 1>
18  %b.real = shufflevector <2 x float> %b, <2 x float> zeroinitializer, <1 x i32> <i32 0>
19  %b.imag = shufflevector <2 x float> %b, <2 x float> zeroinitializer, <1 x i32> <i32 1>
20  %0 = fsub fast <1 x float> %b.real, %a.imag
21  %1 = fadd fast <1 x float> %b.imag, %a.real
22  %interleaved.vec = shufflevector <1 x float> %0, <1 x float> %1, <2 x i32> <i32 0, i32 1>
23  ret <2 x float> %interleaved.vec
24}
25
26; Expected to transform
27define arm_aapcs_vfpcc <4 x float> @complex_add_v4f32(<4 x float> %a, <4 x float> %b) {
28; CHECK-LABEL: complex_add_v4f32:
29; CHECK:       @ %bb.0: @ %entry
30; CHECK-NEXT:    vcadd.f32 q2, q1, q0, #90
31; CHECK-NEXT:    vmov q0, q2
32; CHECK-NEXT:    bx lr
33entry:
34  %a.real = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <2 x i32> <i32 0, i32 2>
35  %a.imag = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <2 x i32> <i32 1, i32 3>
36  %b.real = shufflevector <4 x float> %b, <4 x float> zeroinitializer, <2 x i32> <i32 0, i32 2>
37  %b.imag = shufflevector <4 x float> %b, <4 x float> zeroinitializer, <2 x i32> <i32 1, i32 3>
38  %0 = fsub fast <2 x float> %b.real, %a.imag
39  %1 = fadd fast <2 x float> %b.imag, %a.real
40  %interleaved.vec = shufflevector <2 x float> %0, <2 x float> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
41  ret <4 x float> %interleaved.vec
42}
43
44; Expected to transform
45define arm_aapcs_vfpcc <8 x float> @complex_add_v8f32(<8 x float> %a, <8 x float> %b) {
46; CHECK-LABEL: complex_add_v8f32:
47; CHECK:       @ %bb.0: @ %entry
48; CHECK-NEXT:    .vsave {d8, d9}
49; CHECK-NEXT:    vpush {d8, d9}
50; CHECK-NEXT:    vcadd.f32 q4, q2, q0, #90
51; CHECK-NEXT:    vcadd.f32 q2, q3, q1, #90
52; CHECK-NEXT:    vmov q0, q4
53; CHECK-NEXT:    vmov q1, q2
54; CHECK-NEXT:    vpop {d8, d9}
55; CHECK-NEXT:    bx lr
56entry:
57  %a.real = shufflevector <8 x float> %a, <8 x float> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
58  %a.imag = shufflevector <8 x float> %a, <8 x float> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
59  %b.real = shufflevector <8 x float> %b, <8 x float> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
60  %b.imag = shufflevector <8 x float> %b, <8 x float> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
61  %0 = fsub fast <4 x float> %b.real, %a.imag
62  %1 = fadd fast <4 x float> %b.imag, %a.real
63  %interleaved.vec = shufflevector <4 x float> %0, <4 x float> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
64  ret <8 x float> %interleaved.vec
65}
66
67; Expected to transform
68define arm_aapcs_vfpcc <16 x float> @complex_add_v16f32(<16 x float> %a, <16 x float> %b) {
69; CHECK-LABEL: complex_add_v16f32:
70; CHECK:       @ %bb.0: @ %entry
71; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
72; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}
73; CHECK-NEXT:    add r3, sp, #64
74; CHECK-NEXT:    add r2, sp, #80
75; CHECK-NEXT:    vldrw.u32 q5, [r3]
76; CHECK-NEXT:    add r1, sp, #96
77; CHECK-NEXT:    add r0, sp, #112
78; CHECK-NEXT:    vcadd.f32 q4, q5, q0, #90
79; CHECK-NEXT:    vldrw.u32 q0, [r2]
80; CHECK-NEXT:    vcadd.f32 q5, q0, q1, #90
81; CHECK-NEXT:    vldrw.u32 q0, [r1]
82; CHECK-NEXT:    vmov q1, q5
83; CHECK-NEXT:    vcadd.f32 q6, q0, q2, #90
84; CHECK-NEXT:    vldrw.u32 q0, [r0]
85; CHECK-NEXT:    vmov q2, q6
86; CHECK-NEXT:    vcadd.f32 q7, q0, q3, #90
87; CHECK-NEXT:    vmov q0, q4
88; CHECK-NEXT:    vmov q3, q7
89; CHECK-NEXT:    vpop {d8, d9, d10, d11, d12, d13, d14, d15}
90; CHECK-NEXT:    bx lr
91entry:
92  %a.real = shufflevector <16 x float> %a, <16 x float> zeroinitializer, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
93  %a.imag = shufflevector <16 x float> %a, <16 x float> zeroinitializer, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
94  %b.real = shufflevector <16 x float> %b, <16 x float> zeroinitializer, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
95  %b.imag = shufflevector <16 x float> %b, <16 x float> zeroinitializer, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
96  %0 = fsub fast <8 x float> %b.real, %a.imag
97  %1 = fadd fast <8 x float> %b.imag, %a.real
98  %interleaved.vec = shufflevector <8 x float> %0, <8 x float> %1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
99  ret <16 x float> %interleaved.vec
100}
101