1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s 3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s 4 5define arm_aapcs_vfpcc <2 x i64> @bitcast_i64_i64(<2 x i64> %src) { 6; CHECK-LABEL: bitcast_i64_i64: 7; CHECK: @ %bb.0: @ %entry 8; CHECK-NEXT: bx lr 9entry: 10 %r = bitcast <2 x i64> %src to <2 x i64> 11 ret <2 x i64> %r 12} 13 14define arm_aapcs_vfpcc <2 x i64> @bitcast_i64_i32(<4 x i32> %src) { 15; CHECK-LABEL: bitcast_i64_i32: 16; CHECK: @ %bb.0: @ %entry 17; CHECK-NEXT: bx lr 18entry: 19 %r = bitcast <4 x i32> %src to <2 x i64> 20 ret <2 x i64> %r 21} 22 23define arm_aapcs_vfpcc <2 x i64> @bitcast_i64_i16(<8 x i16> %src) { 24; CHECK-LABEL: bitcast_i64_i16: 25; CHECK: @ %bb.0: @ %entry 26; CHECK-NEXT: bx lr 27entry: 28 %r = bitcast <8 x i16> %src to <2 x i64> 29 ret <2 x i64> %r 30} 31 32define arm_aapcs_vfpcc <2 x i64> @bitcast_i64_i8(<16 x i8> %src) { 33; CHECK-LABEL: bitcast_i64_i8: 34; CHECK: @ %bb.0: @ %entry 35; CHECK-NEXT: bx lr 36entry: 37 %r = bitcast <16 x i8> %src to <2 x i64> 38 ret <2 x i64> %r 39} 40 41define arm_aapcs_vfpcc <2 x i64> @bitcast_i64_f64(<2 x double> %src) { 42; CHECK-LABEL: bitcast_i64_f64: 43; CHECK: @ %bb.0: @ %entry 44; CHECK-NEXT: bx lr 45entry: 46 %r = bitcast <2 x double> %src to <2 x i64> 47 ret <2 x i64> %r 48} 49 50define arm_aapcs_vfpcc <2 x i64> @bitcast_i64_f32(<4 x float> %src) { 51; CHECK-LABEL: bitcast_i64_f32: 52; CHECK: @ %bb.0: @ %entry 53; CHECK-NEXT: bx lr 54entry: 55 %r = bitcast <4 x float> %src to <2 x i64> 56 ret <2 x i64> %r 57} 58 59define arm_aapcs_vfpcc <2 x i64> @bitcast_i64_f16(<8 x half> %src) { 60; CHECK-LABEL: bitcast_i64_f16: 61; CHECK: @ %bb.0: @ %entry 62; CHECK-NEXT: bx lr 63entry: 64 %r = bitcast <8 x half> %src to <2 x i64> 65 ret <2 x i64> %r 66} 67 68 69define arm_aapcs_vfpcc <4 x i32> @bitcast_i32_i64(<2 x i64> %src) { 70; CHECK-LABEL: bitcast_i32_i64: 71; CHECK: @ %bb.0: @ %entry 72; CHECK-NEXT: bx lr 73entry: 74 %r = bitcast <2 x i64> %src to <4 x i32> 75 ret <4 x i32> %r 76} 77 78define arm_aapcs_vfpcc <4 x i32> @bitcast_i32_i32(<4 x i32> %src) { 79; CHECK-LABEL: bitcast_i32_i32: 80; CHECK: @ %bb.0: @ %entry 81; CHECK-NEXT: bx lr 82entry: 83 %r = bitcast <4 x i32> %src to <4 x i32> 84 ret <4 x i32> %r 85} 86 87define arm_aapcs_vfpcc <4 x i32> @bitcast_i32_i16(<8 x i16> %src) { 88; CHECK-LABEL: bitcast_i32_i16: 89; CHECK: @ %bb.0: @ %entry 90; CHECK-NEXT: bx lr 91entry: 92 %r = bitcast <8 x i16> %src to <4 x i32> 93 ret <4 x i32> %r 94} 95 96define arm_aapcs_vfpcc <4 x i32> @bitcast_i32_i8(<16 x i8> %src) { 97; CHECK-LABEL: bitcast_i32_i8: 98; CHECK: @ %bb.0: @ %entry 99; CHECK-NEXT: bx lr 100entry: 101 %r = bitcast <16 x i8> %src to <4 x i32> 102 ret <4 x i32> %r 103} 104 105define arm_aapcs_vfpcc <4 x i32> @bitcast_i32_f64(<2 x double> %src) { 106; CHECK-LABEL: bitcast_i32_f64: 107; CHECK: @ %bb.0: @ %entry 108; CHECK-NEXT: bx lr 109entry: 110 %r = bitcast <2 x double> %src to <4 x i32> 111 ret <4 x i32> %r 112} 113 114define arm_aapcs_vfpcc <4 x i32> @bitcast_i32_f32(<4 x float> %src) { 115; CHECK-LABEL: bitcast_i32_f32: 116; CHECK: @ %bb.0: @ %entry 117; CHECK-NEXT: bx lr 118entry: 119 %r = bitcast <4 x float> %src to <4 x i32> 120 ret <4 x i32> %r 121} 122 123define arm_aapcs_vfpcc <4 x i32> @bitcast_i32_f16(<8 x half> %src) { 124; CHECK-LABEL: bitcast_i32_f16: 125; CHECK: @ %bb.0: @ %entry 126; CHECK-NEXT: bx lr 127entry: 128 %r = bitcast <8 x half> %src to <4 x i32> 129 ret <4 x i32> %r 130} 131 132 133define arm_aapcs_vfpcc <8 x i16> @bitcast_i16_i64(<2 x i64> %src) { 134; CHECK-LABEL: bitcast_i16_i64: 135; CHECK: @ %bb.0: @ %entry 136; CHECK-NEXT: bx lr 137entry: 138 %r = bitcast <2 x i64> %src to <8 x i16> 139 ret <8 x i16> %r 140} 141 142define arm_aapcs_vfpcc <8 x i16> @bitcast_i16_i32(<4 x i32> %src) { 143; CHECK-LABEL: bitcast_i16_i32: 144; CHECK: @ %bb.0: @ %entry 145; CHECK-NEXT: bx lr 146entry: 147 %r = bitcast <4 x i32> %src to <8 x i16> 148 ret <8 x i16> %r 149} 150 151define arm_aapcs_vfpcc <8 x i16> @bitcast_i16_i16(<8 x i16> %src) { 152; CHECK-LABEL: bitcast_i16_i16: 153; CHECK: @ %bb.0: @ %entry 154; CHECK-NEXT: bx lr 155entry: 156 %r = bitcast <8 x i16> %src to <8 x i16> 157 ret <8 x i16> %r 158} 159 160define arm_aapcs_vfpcc <8 x i16> @bitcast_i16_i8(<16 x i8> %src) { 161; CHECK-LABEL: bitcast_i16_i8: 162; CHECK: @ %bb.0: @ %entry 163; CHECK-NEXT: bx lr 164entry: 165 %r = bitcast <16 x i8> %src to <8 x i16> 166 ret <8 x i16> %r 167} 168 169define arm_aapcs_vfpcc <8 x i16> @bitcast_i16_f64(<2 x double> %src) { 170; CHECK-LABEL: bitcast_i16_f64: 171; CHECK: @ %bb.0: @ %entry 172; CHECK-NEXT: bx lr 173entry: 174 %r = bitcast <2 x double> %src to <8 x i16> 175 ret <8 x i16> %r 176} 177 178define arm_aapcs_vfpcc <8 x i16> @bitcast_i16_f32(<4 x float> %src) { 179; CHECK-LABEL: bitcast_i16_f32: 180; CHECK: @ %bb.0: @ %entry 181; CHECK-NEXT: bx lr 182entry: 183 %r = bitcast <4 x float> %src to <8 x i16> 184 ret <8 x i16> %r 185} 186 187define arm_aapcs_vfpcc <8 x i16> @bitcast_i16_f16(<8 x half> %src) { 188; CHECK-LABEL: bitcast_i16_f16: 189; CHECK: @ %bb.0: @ %entry 190; CHECK-NEXT: bx lr 191entry: 192 %r = bitcast <8 x half> %src to <8 x i16> 193 ret <8 x i16> %r 194} 195 196 197define arm_aapcs_vfpcc <16 x i8> @bitcast_i8_i64(<2 x i64> %src) { 198; CHECK-LABEL: bitcast_i8_i64: 199; CHECK: @ %bb.0: @ %entry 200; CHECK-NEXT: bx lr 201entry: 202 %r = bitcast <2 x i64> %src to <16 x i8> 203 ret <16 x i8> %r 204} 205 206define arm_aapcs_vfpcc <16 x i8> @bitcast_i8_i32(<4 x i32> %src) { 207; CHECK-LABEL: bitcast_i8_i32: 208; CHECK: @ %bb.0: @ %entry 209; CHECK-NEXT: bx lr 210entry: 211 %r = bitcast <4 x i32> %src to <16 x i8> 212 ret <16 x i8> %r 213} 214 215define arm_aapcs_vfpcc <16 x i8> @bitcast_i8_i16(<8 x i16> %src) { 216; CHECK-LABEL: bitcast_i8_i16: 217; CHECK: @ %bb.0: @ %entry 218; CHECK-NEXT: bx lr 219entry: 220 %r = bitcast <8 x i16> %src to <16 x i8> 221 ret <16 x i8> %r 222} 223 224define arm_aapcs_vfpcc <16 x i8> @bitcast_i8_i8(<16 x i8> %src) { 225; CHECK-LABEL: bitcast_i8_i8: 226; CHECK: @ %bb.0: @ %entry 227; CHECK-NEXT: bx lr 228entry: 229 %r = bitcast <16 x i8> %src to <16 x i8> 230 ret <16 x i8> %r 231} 232 233define arm_aapcs_vfpcc <16 x i8> @bitcast_i8_f64(<2 x double> %src) { 234; CHECK-LABEL: bitcast_i8_f64: 235; CHECK: @ %bb.0: @ %entry 236; CHECK-NEXT: bx lr 237entry: 238 %r = bitcast <2 x double> %src to <16 x i8> 239 ret <16 x i8> %r 240} 241 242define arm_aapcs_vfpcc <16 x i8> @bitcast_i8_f32(<4 x float> %src) { 243; CHECK-LABEL: bitcast_i8_f32: 244; CHECK: @ %bb.0: @ %entry 245; CHECK-NEXT: bx lr 246entry: 247 %r = bitcast <4 x float> %src to <16 x i8> 248 ret <16 x i8> %r 249} 250 251define arm_aapcs_vfpcc <16 x i8> @bitcast_i8_f16(<8 x half> %src) { 252; CHECK-LABEL: bitcast_i8_f16: 253; CHECK: @ %bb.0: @ %entry 254; CHECK-NEXT: bx lr 255entry: 256 %r = bitcast <8 x half> %src to <16 x i8> 257 ret <16 x i8> %r 258} 259 260 261define arm_aapcs_vfpcc <2 x double> @bitcast_f64_i64(<2 x i64> %src) { 262; CHECK-LABEL: bitcast_f64_i64: 263; CHECK: @ %bb.0: @ %entry 264; CHECK-NEXT: bx lr 265entry: 266 %r = bitcast <2 x i64> %src to <2 x double> 267 ret <2 x double> %r 268} 269 270define arm_aapcs_vfpcc <2 x double> @bitcast_f64_i32(<4 x i32> %src) { 271; CHECK-LABEL: bitcast_f64_i32: 272; CHECK: @ %bb.0: @ %entry 273; CHECK-NEXT: bx lr 274entry: 275 %r = bitcast <4 x i32> %src to <2 x double> 276 ret <2 x double> %r 277} 278 279define arm_aapcs_vfpcc <2 x double> @bitcast_f64_i16(<8 x i16> %src) { 280; CHECK-LABEL: bitcast_f64_i16: 281; CHECK: @ %bb.0: @ %entry 282; CHECK-NEXT: bx lr 283entry: 284 %r = bitcast <8 x i16> %src to <2 x double> 285 ret <2 x double> %r 286} 287 288define arm_aapcs_vfpcc <2 x double> @bitcast_f64_i8(<16 x i8> %src) { 289; CHECK-LABEL: bitcast_f64_i8: 290; CHECK: @ %bb.0: @ %entry 291; CHECK-NEXT: bx lr 292entry: 293 %r = bitcast <16 x i8> %src to <2 x double> 294 ret <2 x double> %r 295} 296 297define arm_aapcs_vfpcc <2 x double> @bitcast_f64_f64(<2 x double> %src) { 298; CHECK-LABEL: bitcast_f64_f64: 299; CHECK: @ %bb.0: @ %entry 300; CHECK-NEXT: bx lr 301entry: 302 %r = bitcast <2 x double> %src to <2 x double> 303 ret <2 x double> %r 304} 305 306define arm_aapcs_vfpcc <2 x double> @bitcast_f64_f32(<4 x float> %src) { 307; CHECK-LABEL: bitcast_f64_f32: 308; CHECK: @ %bb.0: @ %entry 309; CHECK-NEXT: bx lr 310entry: 311 %r = bitcast <4 x float> %src to <2 x double> 312 ret <2 x double> %r 313} 314 315define arm_aapcs_vfpcc <2 x double> @bitcast_f64_f16(<8 x half> %src) { 316; CHECK-LABEL: bitcast_f64_f16: 317; CHECK: @ %bb.0: @ %entry 318; CHECK-NEXT: bx lr 319entry: 320 %r = bitcast <8 x half> %src to <2 x double> 321 ret <2 x double> %r 322} 323 324 325define arm_aapcs_vfpcc <4 x float> @bitcast_f32_i64(<2 x i64> %src) { 326; CHECK-LABEL: bitcast_f32_i64: 327; CHECK: @ %bb.0: @ %entry 328; CHECK-NEXT: bx lr 329entry: 330 %r = bitcast <2 x i64> %src to <4 x float> 331 ret <4 x float> %r 332} 333 334define arm_aapcs_vfpcc <4 x float> @bitcast_f32_i32(<4 x i32> %src) { 335; CHECK-LABEL: bitcast_f32_i32: 336; CHECK: @ %bb.0: @ %entry 337; CHECK-NEXT: bx lr 338entry: 339 %r = bitcast <4 x i32> %src to <4 x float> 340 ret <4 x float> %r 341} 342 343define arm_aapcs_vfpcc <4 x float> @bitcast_f32_i16(<8 x i16> %src) { 344; CHECK-LABEL: bitcast_f32_i16: 345; CHECK: @ %bb.0: @ %entry 346; CHECK-NEXT: bx lr 347entry: 348 %r = bitcast <8 x i16> %src to <4 x float> 349 ret <4 x float> %r 350} 351 352define arm_aapcs_vfpcc <4 x float> @bitcast_f32_i8(<16 x i8> %src) { 353; CHECK-LABEL: bitcast_f32_i8: 354; CHECK: @ %bb.0: @ %entry 355; CHECK-NEXT: bx lr 356entry: 357 %r = bitcast <16 x i8> %src to <4 x float> 358 ret <4 x float> %r 359} 360 361define arm_aapcs_vfpcc <4 x float> @bitcast_f32_f64(<2 x double> %src) { 362; CHECK-LABEL: bitcast_f32_f64: 363; CHECK: @ %bb.0: @ %entry 364; CHECK-NEXT: bx lr 365entry: 366 %r = bitcast <2 x double> %src to <4 x float> 367 ret <4 x float> %r 368} 369 370define arm_aapcs_vfpcc <4 x float> @bitcast_f32_f32(<4 x float> %src) { 371; CHECK-LABEL: bitcast_f32_f32: 372; CHECK: @ %bb.0: @ %entry 373; CHECK-NEXT: bx lr 374entry: 375 %r = bitcast <4 x float> %src to <4 x float> 376 ret <4 x float> %r 377} 378 379define arm_aapcs_vfpcc <4 x float> @bitcast_f32_f16(<8 x half> %src) { 380; CHECK-LABEL: bitcast_f32_f16: 381; CHECK: @ %bb.0: @ %entry 382; CHECK-NEXT: bx lr 383entry: 384 %r = bitcast <8 x half> %src to <4 x float> 385 ret <4 x float> %r 386} 387 388 389define arm_aapcs_vfpcc <8 x half> @bitcast_f16_i64(<2 x i64> %src) { 390; CHECK-LABEL: bitcast_f16_i64: 391; CHECK: @ %bb.0: @ %entry 392; CHECK-NEXT: bx lr 393entry: 394 %r = bitcast <2 x i64> %src to <8 x half> 395 ret <8 x half> %r 396} 397 398define arm_aapcs_vfpcc <8 x half> @bitcast_f16_i32(<4 x i32> %src) { 399; CHECK-LABEL: bitcast_f16_i32: 400; CHECK: @ %bb.0: @ %entry 401; CHECK-NEXT: bx lr 402entry: 403 %r = bitcast <4 x i32> %src to <8 x half> 404 ret <8 x half> %r 405} 406 407define arm_aapcs_vfpcc <8 x half> @bitcast_f16_i16(<8 x i16> %src) { 408; CHECK-LABEL: bitcast_f16_i16: 409; CHECK: @ %bb.0: @ %entry 410; CHECK-NEXT: bx lr 411entry: 412 %r = bitcast <8 x i16> %src to <8 x half> 413 ret <8 x half> %r 414} 415 416define arm_aapcs_vfpcc <8 x half> @bitcast_f16_i8(<16 x i8> %src) { 417; CHECK-LABEL: bitcast_f16_i8: 418; CHECK: @ %bb.0: @ %entry 419; CHECK-NEXT: bx lr 420entry: 421 %r = bitcast <16 x i8> %src to <8 x half> 422 ret <8 x half> %r 423} 424 425define arm_aapcs_vfpcc <8 x half> @bitcast_f16_f64(<2 x double> %src) { 426; CHECK-LABEL: bitcast_f16_f64: 427; CHECK: @ %bb.0: @ %entry 428; CHECK-NEXT: bx lr 429entry: 430 %r = bitcast <2 x double> %src to <8 x half> 431 ret <8 x half> %r 432} 433 434define arm_aapcs_vfpcc <8 x half> @bitcast_f16_f32(<4 x float> %src) { 435; CHECK-LABEL: bitcast_f16_f32: 436; CHECK: @ %bb.0: @ %entry 437; CHECK-NEXT: bx lr 438entry: 439 %r = bitcast <4 x float> %src to <8 x half> 440 ret <8 x half> %r 441} 442 443define arm_aapcs_vfpcc <8 x half> @bitcast_f16_f16(<8 x half> %src) { 444; CHECK-LABEL: bitcast_f16_f16: 445; CHECK: @ %bb.0: @ %entry 446; CHECK-NEXT: bx lr 447entry: 448 %r = bitcast <8 x half> %src to <8 x half> 449 ret <8 x half> %r 450} 451