1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc %s -o - | FileCheck %s 3 4target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 5target triple = "thumbv7em-arm-none-eabi" 6 7%struct.a = type { i32, ptr, i8, i8, i8, i8, ptr, ptr, i16, i16, i16, i16, i16, i16, i16, i16, i32, i32, i32, i32, i32, i32, i32 } 8%struct.b = type { i8, i8, i8, i8, i32, i16, i16, i32, i32, i32, i32, [16 x i8], [64 x i8], [128 x i8], i32, [68 x i8] } 9 10define void @test(ptr nocapture %dhcp, i16 zeroext %value) #0 { 11; CHECK-LABEL: test: 12; CHECK: @ %bb.0: @ %entry 13; CHECK-NEXT: ldrh r2, [r0, #20] 14; CHECK-NEXT: adds r3, r2, #1 15; CHECK-NEXT: strh r3, [r0, #20] 16; CHECK-NEXT: ldr r3, [r0, #16] 17; CHECK-NEXT: add r2, r3 18; CHECK-NEXT: lsrs r3, r1, #8 19; CHECK-NEXT: strb.w r3, [r2, #240] 20; CHECK-NEXT: ldrh r2, [r0, #20] 21; CHECK-NEXT: adds r3, r2, #1 22; CHECK-NEXT: strh r3, [r0, #20] 23; CHECK-NEXT: ldr r0, [r0, #16] 24; CHECK-NEXT: add r0, r2 25; CHECK-NEXT: strb.w r1, [r0, #240] 26; CHECK-NEXT: bx lr 27entry: 28 %shr = lshr i16 %value, 8 29 %conv1 = trunc i16 %shr to i8 30 %msg_out = getelementptr inbounds %struct.a, ptr %dhcp, i32 0, i32 7 31 %0 = load ptr, ptr %msg_out, align 4 32 %options_out_len = getelementptr inbounds %struct.a, ptr %dhcp, i32 0, i32 8 33 %1 = load i16, ptr %options_out_len, align 4 34 %inc = add i16 %1, 1 35 store i16 %inc, ptr %options_out_len, align 4 36 %idxprom = zext i16 %1 to i32 37 %arrayidx = getelementptr inbounds %struct.b, ptr %0, i32 0, i32 15, i32 %idxprom 38 store i8 %conv1, ptr %arrayidx, align 1 39 %conv4 = trunc i16 %value to i8 40 %2 = load ptr, ptr %msg_out, align 4 41 %3 = load i16, ptr %options_out_len, align 4 42 %inc8 = add i16 %3, 1 43 store i16 %inc8, ptr %options_out_len, align 4 44 %idxprom9 = zext i16 %3 to i32 45 %arrayidx10 = getelementptr inbounds %struct.b, ptr %2, i32 0, i32 15, i32 %idxprom9 46 store i8 %conv4, ptr %arrayidx10, align 1 47 ret void 48} 49 50attributes #0 = { minsize optsize "target-cpu"="cortex-m4" } 51