1; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE 2; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP 3; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP -check-prefix=FP-ARMv8 4; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 -mattr=-fp64 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP 5; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=VFP4 6; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a57 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=FP-ARMv8 7 8declare double @llvm.sqrt.f64(double %Val) 9define double @sqrt_d(double %a) { 10; CHECK-LABEL: sqrt_d: 11; SOFT: {{(bl|b)}} sqrt 12; HARD: vsqrt.f64 d0, d0 13 %1 = call double @llvm.sqrt.f64(double %a) 14 ret double %1 15} 16 17declare double @llvm.powi.f64.i32(double %Val, i32 %power) 18define double @powi_d(double %a, i32 %b) { 19; CHECK-LABEL: powi_d: 20; SOFT: {{(bl|b)}} __powidf2 21; HARD: b __powidf2 22 %1 = call double @llvm.powi.f64.i32(double %a, i32 %b) 23 ret double %1 24} 25 26declare double @llvm.sin.f64(double %Val) 27define double @sin_d(double %a) { 28; CHECK-LABEL: sin_d: 29; SOFT: {{(bl|b)}} sin 30; HARD: b sin 31 %1 = call double @llvm.sin.f64(double %a) 32 ret double %1 33} 34 35declare double @llvm.cos.f64(double %Val) 36define double @cos_d(double %a) { 37; CHECK-LABEL: cos_d: 38; SOFT: {{(bl|b)}} cos 39; HARD: b cos 40 %1 = call double @llvm.cos.f64(double %a) 41 ret double %1 42} 43 44declare double @llvm.tan.f64(double %Val) 45define double @tan_d(double %a) { 46; CHECK-LABEL: tan_d: 47; SOFT: {{(bl|b)}} tan 48; HARD: b tan 49 %1 = call double @llvm.tan.f64(double %a) 50 ret double %1 51} 52 53declare double @llvm.pow.f64(double %Val, double %power) 54define double @pow_d(double %a, double %b) { 55; CHECK-LABEL: pow_d: 56; SOFT: {{(bl|b)}} pow 57; HARD: b pow 58 %1 = call double @llvm.pow.f64(double %a, double %b) 59 ret double %1 60} 61 62declare double @llvm.exp.f64(double %Val) 63define double @exp_d(double %a) { 64; CHECK-LABEL: exp_d: 65; SOFT: {{(bl|b)}} exp 66; HARD: b exp 67 %1 = call double @llvm.exp.f64(double %a) 68 ret double %1 69} 70 71declare double @llvm.exp2.f64(double %Val) 72define double @exp2_d(double %a) { 73; CHECK-LABEL: exp2_d: 74; SOFT: {{(bl|b)}} exp2 75; HARD: b exp2 76 %1 = call double @llvm.exp2.f64(double %a) 77 ret double %1 78} 79 80declare double @llvm.log.f64(double %Val) 81define double @log_d(double %a) { 82; CHECK-LABEL: log_d: 83; SOFT: {{(bl|b)}} log 84; HARD: b log 85 %1 = call double @llvm.log.f64(double %a) 86 ret double %1 87} 88 89declare double @llvm.log10.f64(double %Val) 90define double @log10_d(double %a) { 91; CHECK-LABEL: log10_d: 92; SOFT: {{(bl|b)}} log10 93; HARD: b log10 94 %1 = call double @llvm.log10.f64(double %a) 95 ret double %1 96} 97 98declare double @llvm.log2.f64(double %Val) 99define double @log2_d(double %a) { 100; CHECK-LABEL: log2_d: 101; SOFT: {{(bl|b)}} log2 102; HARD: b log2 103 %1 = call double @llvm.log2.f64(double %a) 104 ret double %1 105} 106 107declare double @llvm.fma.f64(double %a, double %b, double %c) 108define double @fma_d(double %a, double %b, double %c) { 109; CHECK-LABEL: fma_d: 110; SOFT: {{(bl|b)}} fma 111; HARD: vfma.f64 112 %1 = call double @llvm.fma.f64(double %a, double %b, double %c) 113 ret double %1 114} 115 116; FIXME: the FPv4-SP version is less efficient than the no-FPU version 117declare double @llvm.fabs.f64(double %Val) 118define double @abs_d(double %a) { 119; CHECK-LABEL: abs_d: 120; NONE: bic r1, r1, #-2147483648 121; SP: vldr [[D1:d[0-9]+]], .LCPI{{.*}} 122; SP-DAG: vmov [[R2:r[0-9]+]], [[R3:r[0-9]+]], [[D1]] 123; SP-DAG: vmov [[R0:r[0-9]+]], [[R1:r[0-9]+]], [[D0:d[0-9]+]] 124; SP: lsrs [[R4:r[0-9]+]], [[R3]], #31 125; SP: bfi [[R5:r[0-9]+]], [[R4]], #31, #1 126; SP: vmov [[D0]], [[R0]], [[R5]] 127; DP: vabs.f64 d0, d0 128 %1 = call double @llvm.fabs.f64(double %a) 129 ret double %1 130} 131 132declare double @llvm.copysign.f64(double %Mag, double %Sgn) 133define double @copysign_d(double %a, double %b) { 134; CHECK-LABEL: copysign_d: 135; SOFT: lsrs [[REG:r[0-9]+]], {{r[0-9]+}}, #31 136; SOFT: bfi {{r[0-9]+}}, [[REG]], #31, #1 137; VFP: lsrs [[REG:r[0-9]+]], {{r[0-9]+}}, #31 138; VFP: bfi {{r[0-9]+}}, [[REG]], #31, #1 139; NEON: vmov.i32 d16, #0x80000000 140; NEON-NEXT: vshl.i64 d16, d16, #32 141; NEON-NEXT: vbit d0, d1, d16 142; NEON-NEXT: bx lr 143 %1 = call double @llvm.copysign.f64(double %a, double %b) 144 ret double %1 145} 146 147declare double @llvm.floor.f64(double %Val) 148define double @floor_d(double %a) { 149; CHECK-LABEL: floor_d: 150; SOFT: {{(bl|b)}} floor 151; VFP4: b floor 152; FP-ARMv8: vrintm.f64 153 %1 = call double @llvm.floor.f64(double %a) 154 ret double %1 155} 156 157declare double @llvm.ceil.f64(double %Val) 158define double @ceil_d(double %a) { 159; CHECK-LABEL: ceil_d: 160; SOFT: {{(bl|b)}} ceil 161; VFP4: b ceil 162; FP-ARMv8: vrintp.f64 163 %1 = call double @llvm.ceil.f64(double %a) 164 ret double %1 165} 166 167declare double @llvm.trunc.f64(double %Val) 168define double @trunc_d(double %a) { 169; CHECK-LABEL: trunc_d: 170; SOFT: {{(bl|b)}} trunc 171; FFP4: b trunc 172; FP-ARMv8: vrintz.f64 173 %1 = call double @llvm.trunc.f64(double %a) 174 ret double %1 175} 176 177declare double @llvm.rint.f64(double %Val) 178define double @rint_d(double %a) { 179; CHECK-LABEL: rint_d: 180; SOFT: {{(bl|b)}} rint 181; VFP4: b rint 182; FP-ARMv8: vrintx.f64 183 %1 = call double @llvm.rint.f64(double %a) 184 ret double %1 185} 186 187declare double @llvm.nearbyint.f64(double %Val) 188define double @nearbyint_d(double %a) { 189; CHECK-LABEL: nearbyint_d: 190; SOFT: {{(bl|b)}} nearbyint 191; VFP4: b nearbyint 192; FP-ARMv8: vrintr.f64 193 %1 = call double @llvm.nearbyint.f64(double %a) 194 ret double %1 195} 196 197declare double @llvm.round.f64(double %Val) 198define double @round_d(double %a) { 199; CHECK-LABEL: round_d: 200; SOFT: {{(bl|b)}} round 201; VFP4: b round 202; FP-ARMv8: vrinta.f64 203 %1 = call double @llvm.round.f64(double %a) 204 ret double %1 205} 206 207declare double @llvm.fmuladd.f64(double %a, double %b, double %c) 208define double @fmuladd_d(double %a, double %b, double %c) { 209; CHECK-LABEL: fmuladd_d: 210; SOFT: bl __aeabi_dmul 211; SOFT: bl __aeabi_dadd 212; VFP4: vmul.f64 213; VFP4: vadd.f64 214; FP-ARMv8: vfma.f64 215 %1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c) 216 ret double %1 217} 218 219declare i16 @llvm.convert.to.fp16.f64(double %a) 220define i16 @d_to_h(double %a) { 221; CHECK-LABEL: d_to_h: 222; SOFT: bl __aeabi_d2h 223; VFP4: bl __aeabi_d2h 224; FP-ARMv8: vcvt{{[bt]}}.f16.f64 225 %1 = call i16 @llvm.convert.to.fp16.f64(double %a) 226 ret i16 %1 227} 228 229declare double @llvm.convert.from.fp16.f64(i16 %a) 230define double @h_to_d(i16 %a) { 231; CHECK-LABEL: h_to_d: 232; NONE: bl __aeabi_h2f 233; NONE: bl __aeabi_f2d 234; SP: vcvt{{[bt]}}.f32.f16 235; SP: bl __aeabi_f2d 236; VFPv4: vcvt{{[bt]}}.f32.f16 237; VFPv4: vcvt.f64.f32 238; FP-ARMv8: vcvt{{[bt]}}.f64.f16 239 %1 = call double @llvm.convert.from.fp16.f64(i16 %a) 240 ret double %1 241} 242