xref: /llvm-project/llvm/test/CodeGen/Thumb2/fir.ll (revision b5b663aac17415625340eb29c8010832bfc4c21c)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve %s -o - | FileCheck %s -check-prefix=CHECK
3; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK
4
5define void @test1(ptr %p0, ptr %p1, ptr %p2, ptr %pDst) {
6; CHECK-LABEL: test1:
7; CHECK:       @ %bb.0: @ %entry
8; CHECK-NEXT:    ldr r1, [r1]
9; CHECK-NEXT:    ldr r2, [r2]
10; CHECK-NEXT:    ldr r0, [r0]
11; CHECK-NEXT:    smmul r1, r2, r1
12; CHECK-NEXT:    add.w r0, r0, r1, lsl #1
13; CHECK-NEXT:    str r0, [r3]
14; CHECK-NEXT:    bx lr
15entry:
16  %l3 = load i32, ptr %p0, align 4
17  %l4 = load i32, ptr %p1, align 4
18  %conv5.us = sext i32 %l4 to i64
19  %l5 = load i32, ptr %p2, align 4
20  %conv6.us = sext i32 %l5 to i64
21  %mul.us = mul nsw i64 %conv6.us, %conv5.us
22  %l6 = lshr i64 %mul.us, 31
23  %l7 = trunc i64 %l6 to i32
24  %shl.us = and i32 %l7, -2
25  %add.us = add nsw i32 %shl.us, %l3
26  store i32 %add.us, ptr %pDst, align 4
27  ret void
28}
29
30define void @test2(ptr %p0, ptr %p1, ptr %p2, ptr %pDst) {
31; CHECK-LABEL: test2:
32; CHECK:       @ %bb.0: @ %entry
33; CHECK-NEXT:    ldr r1, [r1]
34; CHECK-NEXT:    ldr r2, [r2]
35; CHECK-NEXT:    ldr r0, [r0]
36; CHECK-NEXT:    smmul r1, r2, r1
37; CHECK-NEXT:    add.w r0, r0, r1, lsl #1
38; CHECK-NEXT:    str r0, [r3]
39; CHECK-NEXT:    bx lr
40entry:
41  %l3 = load i32, ptr %p0, align 4
42  %l4 = load i32, ptr %p1, align 4
43  %conv5.us = sext i32 %l4 to i64
44  %l5 = load i32, ptr %p2, align 4
45  %conv6.us = sext i32 %l5 to i64
46  %mul.us = mul nsw i64 %conv6.us, %conv5.us
47  %l6 = lshr i64 %mul.us, 32
48  %shl74.us = shl nuw nsw i64 %l6, 1
49  %shl.us = trunc i64 %shl74.us to i32
50  %add.us = add nsw i32 %l3, %shl.us
51  store i32 %add.us, ptr %pDst, align 4
52  ret void
53}
54