xref: /llvm-project/llvm/test/CodeGen/Thumb2/cde-vfp.ll (revision d22e66171251cd3dd07507912189aa814a419678) 
1; RUN: llc -mtriple=thumbv8.1m.main -mattr=+cdecp0 -mattr=+cdecp1 -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s
2; RUN: llc -mtriple=thumbv8m.main -mattr=+cdecp0 -mattr=+cdecp1 -mattr=+fp-armv8d16sp -verify-machineinstrs -o - %s | FileCheck %s
3
4declare float @llvm.arm.cde.vcx1.f32(i32 immarg, i32 immarg)
5declare float @llvm.arm.cde.vcx1a.f32(i32 immarg, float, i32 immarg)
6declare float @llvm.arm.cde.vcx2.f32(i32 immarg, float, i32 immarg)
7declare float @llvm.arm.cde.vcx2a.f32(i32 immarg, float, float, i32 immarg)
8declare float @llvm.arm.cde.vcx3.f32(i32 immarg, float, float, i32 immarg)
9declare float @llvm.arm.cde.vcx3a.f32(i32 immarg, float, float, float, i32 immarg)
10
11declare double @llvm.arm.cde.vcx1.f64(i32 immarg, i32 immarg)
12declare double @llvm.arm.cde.vcx1a.f64(i32 immarg, double, i32 immarg)
13declare double @llvm.arm.cde.vcx2.f64(i32 immarg, double, i32 immarg)
14declare double @llvm.arm.cde.vcx2a.f64(i32 immarg, double, double, i32 immarg)
15declare double @llvm.arm.cde.vcx3.f64(i32 immarg, double, double, i32 immarg)
16declare double @llvm.arm.cde.vcx3a.f64(i32 immarg, double, double, double, i32 immarg)
17
18define arm_aapcs_vfpcc i32 @test_vcx1_u32() {
19; CHECK-LABEL: test_vcx1_u32:
20; CHECK:       @ %bb.0: @ %entry
21; CHECK-NEXT:    vcx1 p0, s0, #11
22; CHECK-NEXT:    vmov r0, s0
23; CHECK-NEXT:    bx lr
24entry:
25  %0 = call float @llvm.arm.cde.vcx1.f32(i32 0, i32 11)
26  %1 = bitcast float %0 to i32
27  ret i32 %1
28}
29
30define arm_aapcs_vfpcc i32 @test_vcx1a_u32(i32 %acc) {
31; CHECK-LABEL: test_vcx1a_u32:
32; CHECK:       @ %bb.0: @ %entry
33; CHECK-NEXT:    vmov s0, r0
34; CHECK-NEXT:    vcx1a p1, s0, #12
35; CHECK-NEXT:    vmov r0, s0
36; CHECK-NEXT:    bx lr
37entry:
38  %0 = bitcast i32 %acc to float
39  %1 = call float @llvm.arm.cde.vcx1a.f32(i32 1, float %0, i32 12)
40  %2 = bitcast float %1 to i32
41  ret i32 %2
42}
43
44define arm_aapcs_vfpcc i32 @test_vcx2_u32(i32 %n) {
45; CHECK-LABEL: test_vcx2_u32:
46; CHECK:       @ %bb.0: @ %entry
47; CHECK-NEXT:    vmov s0, r0
48; CHECK-NEXT:    vcx2 p0, s0, s0, #21
49; CHECK-NEXT:    vmov r0, s0
50; CHECK-NEXT:    bx lr
51entry:
52  %0 = bitcast i32 %n to float
53  %1 = call float @llvm.arm.cde.vcx2.f32(i32 0, float %0, i32 21)
54  %2 = bitcast float %1 to i32
55  ret i32 %2
56}
57
58define arm_aapcs_vfpcc i32 @test_vcx2a_u32(i32 %acc, i32 %n) {
59; CHECK-LABEL: test_vcx2a_u32:
60; CHECK:       @ %bb.0: @ %entry
61; CHECK-NEXT:    vmov s0, r1
62; CHECK-NEXT:    vmov s2, r0
63; CHECK-NEXT:    vcx2a p0, s2, s0, #22
64; CHECK-NEXT:    vmov r0, s2
65; CHECK-NEXT:    bx lr
66entry:
67  %0 = bitcast i32 %acc to float
68  %1 = bitcast i32 %n to float
69  %2 = call float @llvm.arm.cde.vcx2a.f32(i32 0, float %0, float %1, i32 22)
70  %3 = bitcast float %2 to i32
71  ret i32 %3
72}
73
74define arm_aapcs_vfpcc i32 @test_vcx3_u32(i32 %n, i32 %m) {
75; CHECK-LABEL: test_vcx3_u32:
76; CHECK:       @ %bb.0: @ %entry
77; CHECK-NEXT:    vmov s0, r1
78; CHECK-NEXT:    vmov s2, r0
79; CHECK-NEXT:    vcx3 p1, s0, s2, s0, #3
80; CHECK-NEXT:    vmov r0, s0
81; CHECK-NEXT:    bx lr
82entry:
83  %0 = bitcast i32 %n to float
84  %1 = bitcast i32 %m to float
85  %2 = call float @llvm.arm.cde.vcx3.f32(i32 1, float %0, float %1, i32 3)
86  %3 = bitcast float %2 to i32
87  ret i32 %3
88}
89
90define arm_aapcs_vfpcc i32 @test_vcx3a_u32(i32 %acc, i32 %n, i32 %m) {
91; CHECK-LABEL: test_vcx3a_u32:
92; CHECK:       @ %bb.0: @ %entry
93; CHECK-NEXT:    vmov s0, r2
94; CHECK-NEXT:    vmov s2, r1
95; CHECK-NEXT:    vmov s4, r0
96; CHECK-NEXT:    vcx3a p0, s4, s2, s0, #5
97; CHECK-NEXT:    vmov r0, s4
98; CHECK-NEXT:    bx lr
99entry:
100  %0 = bitcast i32 %acc to float
101  %1 = bitcast i32 %n to float
102  %2 = bitcast i32 %m to float
103  %3 = call float @llvm.arm.cde.vcx3a.f32(i32 0, float %0, float %1, float %2, i32 5)
104  %4 = bitcast float %3 to i32
105  ret i32 %4
106}
107
108define arm_aapcs_vfpcc i64 @test_vcx1d_u64() {
109; CHECK-LABEL: test_vcx1d_u64:
110; CHECK:       @ %bb.0: @ %entry
111; CHECK-NEXT:    vcx1 p0, d0, #11
112; CHECK-NEXT:    vmov r0, r1, d0
113; CHECK-NEXT:    bx lr
114entry:
115  %0 = call double @llvm.arm.cde.vcx1.f64(i32 0, i32 11)
116  %1 = bitcast double %0 to i64
117  ret i64 %1
118}
119
120define arm_aapcs_vfpcc i64 @test_vcx1da_u64(i64 %acc) {
121; CHECK-LABEL: test_vcx1da_u64:
122; CHECK:       @ %bb.0: @ %entry
123; CHECK-NEXT:    vmov d0, r0, r1
124; CHECK-NEXT:    vcx1a p1, d0, #12
125; CHECK-NEXT:    vmov r0, r1, d0
126; CHECK-NEXT:    bx lr
127entry:
128  %0 = bitcast i64 %acc to double
129  %1 = call double @llvm.arm.cde.vcx1a.f64(i32 1, double %0, i32 12)
130  %2 = bitcast double %1 to i64
131  ret i64 %2
132}
133
134define arm_aapcs_vfpcc i64 @test_vcx2d_u64(i64 %n) {
135; CHECK-LABEL: test_vcx2d_u64:
136; CHECK:       @ %bb.0: @ %entry
137; CHECK-NEXT:    vmov d0, r0, r1
138; CHECK-NEXT:    vcx2 p0, d0, d0, #21
139; CHECK-NEXT:    vmov r0, r1, d0
140; CHECK-NEXT:    bx lr
141entry:
142  %0 = bitcast i64 %n to double
143  %1 = call double @llvm.arm.cde.vcx2.f64(i32 0, double %0, i32 21)
144  %2 = bitcast double %1 to i64
145  ret i64 %2
146}
147
148define arm_aapcs_vfpcc i64 @test_vcx2da_u64(i64 %acc, i64 %n) {
149; CHECK-LABEL: test_vcx2da_u64:
150; CHECK:       @ %bb.0: @ %entry
151; CHECK-NEXT:    vmov d0, r2, r3
152; CHECK-NEXT:    vmov d1, r0, r1
153; CHECK-NEXT:    vcx2a p0, d1, d0, #22
154; CHECK-NEXT:    vmov r0, r1, d1
155; CHECK-NEXT:    bx lr
156entry:
157  %0 = bitcast i64 %acc to double
158  %1 = bitcast i64 %n to double
159  %2 = call double @llvm.arm.cde.vcx2a.f64(i32 0, double %0, double %1, i32 22)
160  %3 = bitcast double %2 to i64
161  ret i64 %3
162}
163
164define arm_aapcs_vfpcc i64 @test_vcx3d_u64(i64 %n, i64 %m) {
165; CHECK-LABEL: test_vcx3d_u64:
166; CHECK:       @ %bb.0: @ %entry
167; CHECK-NEXT:    vmov d0, r2, r3
168; CHECK-NEXT:    vmov d1, r0, r1
169; CHECK-NEXT:    vcx3 p1, d0, d1, d0, #3
170; CHECK-NEXT:    vmov r0, r1, d0
171; CHECK-NEXT:    bx lr
172entry:
173  %0 = bitcast i64 %n to double
174  %1 = bitcast i64 %m to double
175  %2 = call double @llvm.arm.cde.vcx3.f64(i32 1, double %0, double %1, i32 3)
176  %3 = bitcast double %2 to i64
177  ret i64 %3
178}
179
180define arm_aapcs_vfpcc i64 @test_vcx3da_u64(i64 %acc, i64 %n, i64 %m) {
181; CHECK-LABEL: test_vcx3da_u64:
182; CHECK:       @ %bb.0: @ %entry
183; CHECK-NEXT:    push {r7, lr}
184; CHECK-NEXT:    ldrd lr, r12, [sp, #8]
185; CHECK-DAG:     vmov [[D0:d.*]], r0, r1
186; CHECK-DAG:     vmov [[D1:d.*]], r2, r3
187; CHECK-DAG:     vmov [[D2:d.*]], lr, r12
188; CHECK-NEXT:    vcx3a p0, [[D0]], [[D1]], [[D2]], #5
189; CHECK-NEXT:    vmov r0, r1, [[D0]]
190; CHECK-NEXT:    pop {r7, pc}
191entry:
192  %0 = bitcast i64 %acc to double
193  %1 = bitcast i64 %n to double
194  %2 = bitcast i64 %m to double
195  %3 = call double @llvm.arm.cde.vcx3a.f64(i32 0, double %0, double %1, double %2, i32 5)
196  %4 = bitcast double %3 to i64
197  ret i64 %4
198}
199