xref: /llvm-project/llvm/test/CodeGen/Thumb2/bti-jump-table.mir (revision bb0403ae2e8f872369b1ce6f88d42d8bf02b922e)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc < %s -x mir -mtriple=thumbv7m-arm-none-eabi -run-pass=arm-branch-targets | FileCheck %s
3--- |
4  define internal i32 @table_switch(i32 %x) {
5  entry:
6    switch i32 %x, label %sw.epilog [
7      i32 1, label %return
8      i32 2, label %bb2
9      i32 3, label %bb3
10      i32 4, label %bb4
11    ]
12
13  bb2:
14    br label %return
15
16  bb3:
17    br label %return
18
19  bb4:
20    br label %return
21
22  sw.epilog:
23    br label %return
24
25  return:
26    %ret = phi i32 [ 0, %sw.epilog ], [ 2, %bb2 ], [ 3, %bb3 ], [ 4, %bb4 ], [ 1, %entry ]
27    ret i32 %ret
28  }
29
30  !llvm.module.flags = !{!0}
31  !0 = !{i32 8, !"branch-target-enforcement", i32 1}
32
33...
34---
35name:            table_switch
36alignment:       4
37tracksRegLiveness: true
38liveins:
39  - { reg: '$r0' }
40frameInfo:
41  maxAlignment:    1
42  maxCallFrameSize: 0
43machineFunctionInfo: {}
44jumpTable:
45  kind:            inline
46  entries:
47    - id:              0
48      blocks:          [ '%bb.6', '%bb.2', '%bb.3', '%bb.4' ]
49body:             |
50  ; CHECK-LABEL: name: table_switch
51  ; CHECK: bb.0.entry:
52  ; CHECK:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
53  ; CHECK:   liveins: $r0
54  ; CHECK:   renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 1, 14 /* CC::al */, $noreg
55  ; CHECK:   tCMPi8 renamable $r1, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
56  ; CHECK:   t2Bcc %bb.3, 8 /* CC::hi */, killed $cpsr
57  ; CHECK: bb.1.entry:
58  ; CHECK:   successors: %bb.4(0x20000000), %bb.2(0x20000000), %bb.5(0x20000000), %bb.6(0x20000000)
59  ; CHECK:   liveins: $r1
60  ; CHECK:   renamable $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
61  ; CHECK:   renamable $r2 = t2LEApcrelJT %jump-table.0, 14 /* CC::al */, $noreg
62  ; CHECK:   renamable $r2 = t2ADDrs killed renamable $r2, renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg
63  ; CHECK:   t2BR_JT killed renamable $r2, killed renamable $r1, %jump-table.0
64  ; CHECK: bb.2.bb2:
65  ; CHECK:   renamable $r0, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
66  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg, implicit $r0
67  ; CHECK: bb.3.sw.epilog:
68  ; CHECK:   successors: %bb.4(0x80000000)
69  ; CHECK:   renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
70  ; CHECK: bb.4.return:
71  ; CHECK:   liveins: $r0
72  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg, implicit $r0
73  ; CHECK: bb.5.bb3:
74  ; CHECK:   renamable $r0, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
75  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg, implicit $r0
76  ; CHECK: bb.6.bb4:
77  ; CHECK:   renamable $r0, dead $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
78  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg, implicit $r0
79  bb.0.entry:
80    successors: %bb.5, %bb.1
81    liveins: $r0
82
83    renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 1, 14 /* CC::al */, $noreg
84    tCMPi8 renamable $r1, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
85    t2Bcc %bb.5, 8 /* CC::hi */, killed $cpsr
86
87  bb.1.entry:
88    successors: %bb.6, %bb.2, %bb.3, %bb.4
89    liveins: $r1
90
91    renamable $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
92    renamable $r2 = t2LEApcrelJT %jump-table.0, 14 /* CC::al */, $noreg
93    renamable $r2 = t2ADDrs killed renamable $r2, renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg
94    t2BR_JT killed renamable $r2, killed renamable $r1, %jump-table.0
95
96  bb.2.bb2:
97    renamable $r0, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
98    tBX_RET 14 /* CC::al */, $noreg, implicit $r0
99
100  bb.5.sw.epilog:
101    renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
102
103  bb.6.return:
104    liveins: $r0
105
106    tBX_RET 14 /* CC::al */, $noreg, implicit $r0
107
108  bb.3.bb3:
109    renamable $r0, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
110    tBX_RET 14 /* CC::al */, $noreg, implicit $r0
111
112  bb.4.bb4:
113    renamable $r0, dead $cpsr = tMOVi8 4, 14 /* CC::al */, $noreg
114    tBX_RET 14 /* CC::al */, $noreg, implicit $r0
115
116...
117