1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s 3 4--- | 5 define dso_local arm_aapcs_vfpcc signext i16 @wrong_liveout_shift(ptr nocapture readonly %b, ptr nocapture readonly %c, i32 %N) { 6 entry: 7 %cmp11 = icmp eq i32 %N, 0 8 %0 = add i32 %N, 7 9 %1 = lshr i32 %0, 3 10 %2 = shl nuw i32 %1, 3 11 %3 = add i32 %2, -8 12 %4 = lshr i32 %3, 2 13 %5 = add nuw nsw i32 %4, 1 14 br i1 %cmp11, label %for.cond.cleanup, label %vector.ph 15 16 vector.ph: ; preds = %entry 17 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 18 %6 = shl i32 %4, 3 19 %7 = sub i32 %N, %6 20 br label %vector.body 21 22 vector.body: ; preds = %vector.body, %vector.ph 23 %lsr.iv20 = phi ptr [ %scevgep21, %vector.body ], [ %c, %vector.ph ] 24 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %b, %vector.ph ] 25 %vec.phi = phi <8 x i16> [ <i16 32767, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %vector.ph ], [ %15, %vector.body ] 26 %8 = phi i32 [ %start, %vector.ph ], [ %16, %vector.body ] 27 %9 = phi i32 [ %N, %vector.ph ], [ %11, %vector.body ] 28 %lsr.iv2022 = bitcast ptr %lsr.iv20 to ptr 29 %lsr.iv19 = bitcast ptr %lsr.iv to ptr 30 %10 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %9) 31 %11 = sub i32 %9, 8 32 %wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %lsr.iv19, i32 1, <8 x i1> %10, <8 x i8> undef) 33 %12 = zext <8 x i8> %wide.masked.load to <8 x i16> 34 %wide.masked.load16 = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %lsr.iv2022, i32 1, <8 x i1> %10, <8 x i8> undef) 35 %13 = zext <8 x i8> %wide.masked.load16 to <8 x i16> 36 %14 = mul nuw <8 x i16> %13, %12 37 %15 = sub <8 x i16> %vec.phi, %14 38 %scevgep = getelementptr i8, ptr %lsr.iv, i32 8 39 %scevgep21 = getelementptr i8, ptr %lsr.iv20, i32 8 40 %16 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %8, i32 1) 41 %17 = icmp ne i32 %16, 0 42 br i1 %17, label %vector.body, label %middle.block 43 44 middle.block: ; preds = %vector.body 45 %vec.phi.lcssa = phi <8 x i16> [ %vec.phi, %vector.body ] 46 %.lcssa = phi <8 x i16> [ %15, %vector.body ] 47 %18 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %7) 48 %19 = select <8 x i1> %18, <8 x i16> %.lcssa, <8 x i16> %vec.phi.lcssa 49 %20 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %19) 50 br label %for.cond.cleanup 51 52 for.cond.cleanup: ; preds = %middle.block, %entry 53 %a.0.lcssa = phi i16 [ 32767, %entry ], [ %20, %middle.block ] 54 ret i16 %a.0.lcssa 55 } 56 declare <8 x i8> @llvm.masked.load.v8i8.p0(ptr, i32 immarg, <8 x i1>, <8 x i8>) 57 declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>) 58 declare i32 @llvm.start.loop.iterations.i32(i32) 59 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 60 declare <8 x i1> @llvm.arm.mve.vctp16(i32) 61 62... 63--- 64name: wrong_liveout_shift 65alignment: 16 66exposesReturnsTwice: false 67legalized: false 68regBankSelected: false 69selected: false 70failedISel: false 71tracksRegLiveness: true 72hasWinCFI: false 73registers: [] 74liveins: 75 - { reg: '$r0', virtual-reg: '' } 76 - { reg: '$r1', virtual-reg: '' } 77 - { reg: '$r2', virtual-reg: '' } 78frameInfo: 79 isFrameAddressTaken: false 80 isReturnAddressTaken: false 81 hasStackMap: false 82 hasPatchPoint: false 83 stackSize: 8 84 offsetAdjustment: 0 85 maxAlignment: 4 86 adjustsStack: false 87 hasCalls: false 88 stackProtector: '' 89 maxCallFrameSize: 0 90 cvBytesOfCalleeSavedRegisters: 0 91 hasOpaqueSPAdjustment: false 92 hasVAStart: false 93 hasMustTailInVarArgFunc: false 94 localFrameSize: 0 95 savePoint: '' 96 restorePoint: '' 97fixedStack: [] 98stack: 99 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 100 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true, 101 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 102 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 103 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 104 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 105callSites: [] 106constants: 107 - id: 0 108 value: '<8 x i16> <i16 32767, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>' 109 alignment: 16 110 isTargetSpecific: false 111machineFunctionInfo: {} 112body: | 113 ; CHECK-LABEL: name: wrong_liveout_shift 114 ; CHECK: bb.0.entry: 115 ; CHECK: successors: %bb.1(0x80000000) 116 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 117 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 118 ; CHECK: t2IT 0, 2, implicit-def $itstate 119 ; CHECK: renamable $r0 = t2MOVi16 32767, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate 120 ; CHECK: renamable $r0 = tSXTH killed renamable $r0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate 121 ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate 122 ; CHECK: bb.1.vector.ph: 123 ; CHECK: successors: %bb.2(0x80000000) 124 ; CHECK: liveins: $lr, $r0, $r1, $r2 125 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 126 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 127 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 128 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 129 ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 130 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 131 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg 132 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 133 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 8, 14 /* CC::al */, $noreg, $noreg 134 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 135 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 136 ; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg 137 ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 2, 14 /* CC::al */, $noreg, $noreg 138 ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool) 139 ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14 /* CC::al */, $noreg, $noreg 140 ; CHECK: bb.2.vector.body: 141 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 142 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 143 ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg 144 ; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, $noreg, undef $q1 145 ; CHECK: MVE_VPST 4, implicit $vpr 146 ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv19, align 1) 147 ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv2022, align 1) 148 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg 149 ; CHECK: renamable $q0 = nuw MVE_VMULi16 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 150 ; CHECK: renamable $q0 = MVE_VSUBi16 renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 151 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 152 ; CHECK: bb.3.middle.block: 153 ; CHECK: liveins: $q0, $q1, $r3 154 ; CHECK: renamable $vpr = MVE_VCTP16 killed renamable $r3, 0, $noreg, $noreg 155 ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg 156 ; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg 157 ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr 158 ; CHECK: renamable $r0 = tSXTH killed renamable $r0, 14 /* CC::al */, $noreg 159 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0 160 ; CHECK: bb.4 (align 16): 161 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 162 bb.0.entry: 163 successors: %bb.1(0x80000000) 164 liveins: $r0, $r1, $r2, $lr 165 166 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr 167 t2IT 0, 2, implicit-def $itstate 168 renamable $r0 = t2MOVi16 32767, 0, $cpsr, implicit killed $r0, implicit $itstate 169 renamable $r0 = tSXTH killed renamable $r0, 0, $cpsr, implicit killed $r0, implicit $itstate 170 tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate 171 172 bb.1.vector.ph: 173 successors: %bb.2(0x80000000) 174 liveins: $r0, $r1, $r2, $lr 175 176 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp 177 frame-setup CFI_INSTRUCTION def_cfa_offset 8 178 frame-setup CFI_INSTRUCTION offset $lr, -4 179 frame-setup CFI_INSTRUCTION offset $r7, -8 180 $r7 = frame-setup tMOVr $sp, 14, $noreg 181 frame-setup CFI_INSTRUCTION def_cfa_register $r7 182 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14, $noreg 183 renamable $r3 = t2BICri killed renamable $r3, 7, 14, $noreg, $noreg 184 renamable $r12 = t2SUBri killed renamable $r3, 8, 14, $noreg, $noreg 185 renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg 186 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14, $noreg, $noreg 187 renamable $r3 = tLEApcrel %const.0, 14, $noreg 188 renamable $r12 = t2LSRri killed renamable $r12, 2, 14, $noreg, $noreg 189 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool) 190 renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14, $noreg, $noreg 191 $lr = t2DoLoopStart renamable $lr 192 193 bb.2.vector.body: 194 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 195 liveins: $lr, $q0, $r0, $r1, $r2, $r3 196 197 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg 198 $q1 = MVE_VORR killed $q0, $q0, 0, $noreg, $noreg, undef $q1 199 MVE_VPST 4, implicit $vpr 200 renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv19, align 1) 201 renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv2022, align 1) 202 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14, $noreg 203 renamable $q0 = nuw MVE_VMULi16 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 204 renamable $lr = t2LoopDec killed renamable $lr, 1 205 renamable $q0 = MVE_VSUBi16 renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 206 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 207 tB %bb.3, 14, $noreg 208 209 bb.3.middle.block: 210 liveins: $q0, $q1, $r3 211 212 renamable $vpr = MVE_VCTP16 killed renamable $r3, 0, $noreg, $noreg 213 renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg 214 renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg 215 $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr 216 renamable $r0 = tSXTH killed renamable $r0, 14, $noreg 217 tBX_RET 14, $noreg, implicit killed $r0 218 219 bb.4 (align 16): 220 CONSTPOOL_ENTRY 0, %const.0, 16 221 222... 223