1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob,+mve %s -start-before=arm-block-placement --verify-machineinstrs -o - | FileCheck %s 3 4# This is a large test for block placement, including reverting WLS to DLS. It 5# should not crash or leave any VCTP instructions. 6# CHECK-LABEL: test 7# CHECK-NOT: vctp 8 9--- | 10 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 11 target triple = "thumbv8.1m.main-arm-none-eabi" 12 13 @var_76 = external dso_local local_unnamed_addr global i64, align 8 14 @var_77 = external dso_local local_unnamed_addr global i8, align 1 15 @arr_163 = external dso_local local_unnamed_addr global [12 x [12 x i8]], align 1 16 @var_81 = external dso_local local_unnamed_addr global i32, align 4 17 @arr_239 = external dso_local local_unnamed_addr global [22 x i8], align 1 18 19 define i32 @test(i8 zeroext %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p, i32 %q) { 20 entry: 21 %tobool7.not = icmp eq i32 %i, 0 22 %cond11 = select i1 %tobool7.not, i32 %l, i32 %i 23 %tobool13 = icmp ne i32 %m, 0 24 %frombool = zext i1 %tobool13 to i8 25 %tobool23.not = icmp eq i8 %g, 0 26 %cond24 = select i1 %tobool23.not, i32 5, i32 0 27 %cmp27 = icmp sgt i32 %cond24, %m 28 %conv29 = zext i1 %cmp27 to i8 29 %conv36 = zext i8 %g to i32 30 %tobool38 = icmp ne i32 %n, 0 31 %tobool39 = icmp ne i32 %o, 0 32 %0 = select i1 %tobool38, i1 true, i1 %tobool39 33 %lor.ext = zext i1 %0 to i32 34 %cmp84 = icmp sgt i32 %k, 0 35 br i1 %cmp84, label %for.body.lr.ph, label %for.cond45.preheader 36 37 for.body.lr.ph: ; preds = %entry 38 %cmp2 = icmp slt i32 %n, 0 39 %cond = select i1 %cmp2, i32 %o, i32 0 40 %cmp1782.not = icmp eq i32 %i, -1514690832 41 %rem = srem i32 9, %p 42 br i1 %cmp1782.not, label %for.body.lr.ph.split, label %for.body.lr.ph.split.us 43 44 for.body.lr.ph.split.us: ; preds = %for.body.lr.ph 45 %1 = icmp slt i32 %rem, %cond 46 br i1 %1, label %for.body.lr.ph.split.us.split.us, label %for.body.lr.ph.split.us.split 47 48 for.body.lr.ph.split.us.split.us: ; preds = %for.body.lr.ph.split.us 49 %2 = sext i32 %cond11 to i64 50 %const19 = bitcast i32 1514690832 to i32 51 store i64 %2, ptr @var_76, align 8 52 store i8 %frombool, ptr @var_77, align 1 53 %3 = add i32 %i, %const19 54 %4 = add nsw i32 %k, -1 55 %xtraiter154 = and i32 %k, 3 56 %5 = icmp ult i32 %4, 3 57 br i1 %5, label %for.cond.for.cond45.preheader_crit_edge.loopexit135.unr-lcssa, label %for.body.lr.ph.split.us.split.us.new 58 59 for.body.lr.ph.split.us.split.us.new: ; preds = %for.body.lr.ph.split.us.split.us 60 %unroll_iter158 = and i32 %k, -4 61 br label %for.body.us.us 62 63 for.body.us.us: ; preds = %for.body.us.us, %for.body.lr.ph.split.us.split.us.new 64 %lsr.iv = phi ptr [ %6, %for.body.us.us ], [ getelementptr inbounds ([12 x [12 x i8]], ptr @arr_163, i32 0, i32 2, i32 0), %for.body.lr.ph.split.us.split.us.new ] 65 %ac.085.us.us = phi i32 [ 0, %for.body.lr.ph.split.us.split.us.new ], [ %add43.us.us.3, %for.body.us.us ] 66 %lsr.iv3 = bitcast ptr %lsr.iv to ptr 67 %scevgep6 = getelementptr i8, ptr %lsr.iv3, i32 -24 68 call void @llvm.memset.p0.i32(ptr align 1 %scevgep6, i8 %conv29, i32 %3, i1 false) 69 %scevgep5 = getelementptr i8, ptr %lsr.iv3, i32 -12 70 call void @llvm.memset.p0.i32(ptr align 1 %scevgep5, i8 %conv29, i32 %3, i1 false) 71 call void @llvm.memset.p0.i32(ptr align 1 %lsr.iv3, i8 %conv29, i32 %3, i1 false) 72 %scevgep4 = getelementptr i8, ptr %lsr.iv3, i32 12 73 call void @llvm.memset.p0.i32(ptr align 1 %scevgep4, i8 %conv29, i32 %3, i1 false) 74 %add43.us.us.3 = add nuw i32 %ac.085.us.us, 4 75 %scevgep2 = getelementptr [12 x [12 x i8]], ptr %lsr.iv, i32 0, i32 4, i32 0 76 %6 = bitcast ptr %scevgep2 to ptr 77 %niter159.ncmp.3 = icmp eq i32 %unroll_iter158, %add43.us.us.3 78 br i1 %niter159.ncmp.3, label %for.cond.for.cond45.preheader_crit_edge.loopexit135.unr-lcssa, label %for.body.us.us 79 80 for.body.lr.ph.split.us.split: ; preds = %for.body.lr.ph.split.us 81 %7 = icmp eq i32 %m, 0 82 %const = bitcast i32 1514690832 to i32 83 %8 = add i32 %i, %const 84 %9 = add nsw i32 %k, -1 85 %xtraiter148 = and i32 %k, 3 86 br i1 %7, label %for.body.us.us115.preheader, label %for.body.us.preheader 87 88 for.body.us.preheader: ; preds = %for.body.lr.ph.split.us.split 89 %10 = icmp ult i32 %9, 3 90 br i1 %10, label %for.cond.for.cond45.preheader_crit_edge.loopexit147.unr-lcssa, label %for.body.us.preheader.new 91 92 for.body.us.preheader.new: ; preds = %for.body.us.preheader 93 %unroll_iter = and i32 %k, -4 94 br label %for.body.us 95 96 for.body.us.us115.preheader: ; preds = %for.body.lr.ph.split.us.split 97 %11 = icmp ult i32 %9, 3 98 br i1 %11, label %for.cond.for.cond45.preheader_crit_edge.loopexit.unr-lcssa, label %for.body.us.us115.preheader.new 99 100 for.body.us.us115.preheader.new: ; preds = %for.body.us.us115.preheader 101 %unroll_iter152 = and i32 %k, -4 102 br label %for.body.us.us115 103 104 for.body.us.us115: ; preds = %for.body.us.us115, %for.body.us.us115.preheader.new 105 %lsr.iv7 = phi ptr [ %12, %for.body.us.us115 ], [ getelementptr inbounds ([12 x [12 x i8]], ptr @arr_163, i32 0, i32 2, i32 0), %for.body.us.us115.preheader.new ] 106 %ac.085.us.us116 = phi i32 [ 0, %for.body.us.us115.preheader.new ], [ %add43.us.us120.3, %for.body.us.us115 ] 107 %lsr.iv79 = bitcast ptr %lsr.iv7 to ptr 108 %scevgep12 = getelementptr i8, ptr %lsr.iv79, i32 -24 109 call void @llvm.memset.p0.i32(ptr align 1 %scevgep12, i8 %conv29, i32 %8, i1 false) 110 %scevgep11 = getelementptr i8, ptr %lsr.iv79, i32 -12 111 call void @llvm.memset.p0.i32(ptr align 1 %scevgep11, i8 %conv29, i32 %8, i1 false) 112 call void @llvm.memset.p0.i32(ptr align 1 %lsr.iv79, i8 %conv29, i32 %8, i1 false) 113 %scevgep10 = getelementptr i8, ptr %lsr.iv79, i32 12 114 call void @llvm.memset.p0.i32(ptr align 1 %scevgep10, i8 %conv29, i32 %8, i1 false) 115 %add43.us.us120.3 = add nuw i32 %ac.085.us.us116, 4 116 %scevgep8 = getelementptr [12 x [12 x i8]], ptr %lsr.iv7, i32 0, i32 4, i32 0 117 %12 = bitcast ptr %scevgep8 to ptr 118 %niter153.ncmp.3 = icmp eq i32 %unroll_iter152, %add43.us.us120.3 119 br i1 %niter153.ncmp.3, label %for.cond.for.cond45.preheader_crit_edge.loopexit.unr-lcssa, label %for.body.us.us115 120 121 for.body.us: ; preds = %for.body.us, %for.body.us.preheader.new 122 %lsr.iv13 = phi ptr [ %13, %for.body.us ], [ getelementptr inbounds ([12 x [12 x i8]], ptr @arr_163, i32 0, i32 2, i32 0), %for.body.us.preheader.new ] 123 %ac.085.us = phi i32 [ 0, %for.body.us.preheader.new ], [ %add43.us.3, %for.body.us ] 124 %lsr.iv1315 = bitcast ptr %lsr.iv13 to ptr 125 %scevgep18 = getelementptr i8, ptr %lsr.iv1315, i32 -24 126 call void @llvm.memset.p0.i32(ptr align 1 %scevgep18, i8 %conv29, i32 %8, i1 false) 127 %scevgep17 = getelementptr i8, ptr %lsr.iv1315, i32 -12 128 call void @llvm.memset.p0.i32(ptr align 1 %scevgep17, i8 %conv29, i32 %8, i1 false) 129 call void @llvm.memset.p0.i32(ptr align 1 %lsr.iv1315, i8 %conv29, i32 %8, i1 false) 130 %scevgep16 = getelementptr i8, ptr %lsr.iv1315, i32 12 131 call void @llvm.memset.p0.i32(ptr align 1 %scevgep16, i8 %conv29, i32 %8, i1 false) 132 %add43.us.3 = add nuw i32 %ac.085.us, 4 133 %scevgep14 = getelementptr [12 x [12 x i8]], ptr %lsr.iv13, i32 0, i32 4, i32 0 134 %13 = bitcast ptr %scevgep14 to ptr 135 %niter.ncmp.3 = icmp eq i32 %unroll_iter, %add43.us.3 136 br i1 %niter.ncmp.3, label %for.cond.for.cond45.preheader_crit_edge.loopexit147.unr-lcssa, label %for.body.us 137 138 for.body.lr.ph.split: ; preds = %for.body.lr.ph 139 %14 = icmp slt i32 %rem, %cond 140 br i1 %14, label %for.body.lr.ph.split.split.us, label %for.body.lr.ph.split.split 141 142 for.body.lr.ph.split.split.us: ; preds = %for.body.lr.ph.split 143 %15 = icmp eq i32 %m, 0 144 %16 = sext i32 %cond11 to i64 145 store i64 %16, ptr @var_76, align 8 146 store i8 %frombool, ptr @var_77, align 1 147 %spec.select = select i1 %15, i32 %lor.ext, i32 %conv36 148 br label %for.cond.for.cond45.preheader_crit_edge 149 150 for.body.lr.ph.split.split: ; preds = %for.body.lr.ph.split 151 %17 = icmp eq i32 %m, 0 152 %spec.select143 = select i1 %17, i32 %lor.ext, i32 %conv36 153 br label %for.cond.for.cond45.preheader_crit_edge 154 155 for.cond.for.cond45.preheader_crit_edge.loopexit135.unr-lcssa: ; preds = %for.body.us.us, %for.body.lr.ph.split.us.split.us 156 %ac.085.us.us.unr = phi i32 [ 0, %for.body.lr.ph.split.us.split.us ], [ %add43.us.us.3, %for.body.us.us ] 157 %lcmp.mod157.not = icmp eq i32 %xtraiter154, 0 158 br i1 %lcmp.mod157.not, label %for.cond.for.cond45.preheader_crit_edge.loopexit135, label %for.body.us.us.epil 159 160 for.body.us.us.epil: ; preds = %for.cond.for.cond45.preheader_crit_edge.loopexit135.unr-lcssa 161 %scevgep140.epil = getelementptr [12 x [12 x i8]], ptr @arr_163, i32 0, i32 %ac.085.us.us.unr, i32 0 162 call void @llvm.memset.p0.i32(ptr align 1 %scevgep140.epil, i8 %conv29, i32 %3, i1 false) 163 %epil.iter.cmp156.not = icmp eq i32 %xtraiter154, 1 164 br i1 %epil.iter.cmp156.not, label %for.cond.for.cond45.preheader_crit_edge.loopexit135, label %for.body.us.us.epil.1 165 166 for.cond.for.cond45.preheader_crit_edge.loopexit135: ; preds = %for.body.us.us.epil.2, %for.body.us.us.epil.1, %for.body.us.us.epil, %for.cond.for.cond45.preheader_crit_edge.loopexit135.unr-lcssa 167 %18 = icmp eq i32 %m, 0 168 %cond41.us.us = select i1 %18, i32 %lor.ext, i32 %conv36 169 br label %for.cond.for.cond45.preheader_crit_edge 170 171 for.cond.for.cond45.preheader_crit_edge.loopexit.unr-lcssa: ; preds = %for.body.us.us115, %for.body.us.us115.preheader 172 %ac.085.us.us116.unr = phi i32 [ 0, %for.body.us.us115.preheader ], [ %add43.us.us120.3, %for.body.us.us115 ] 173 %lcmp.mod151.not = icmp eq i32 %xtraiter148, 0 174 br i1 %lcmp.mod151.not, label %for.cond.for.cond45.preheader_crit_edge, label %for.body.us.us115.epil 175 176 for.body.us.us115.epil: ; preds = %for.cond.for.cond45.preheader_crit_edge.loopexit.unr-lcssa 177 %scevgep138.epil = getelementptr [12 x [12 x i8]], ptr @arr_163, i32 0, i32 %ac.085.us.us116.unr, i32 0 178 call void @llvm.memset.p0.i32(ptr align 1 %scevgep138.epil, i8 %conv29, i32 %8, i1 false) 179 %epil.iter.cmp150.not = icmp eq i32 %xtraiter148, 1 180 br i1 %epil.iter.cmp150.not, label %for.cond.for.cond45.preheader_crit_edge, label %for.body.us.us115.epil.1 181 182 for.cond.for.cond45.preheader_crit_edge.loopexit147.unr-lcssa: ; preds = %for.body.us, %for.body.us.preheader 183 %ac.085.us.unr = phi i32 [ 0, %for.body.us.preheader ], [ %add43.us.3, %for.body.us ] 184 %lcmp.mod.not = icmp eq i32 %xtraiter148, 0 185 br i1 %lcmp.mod.not, label %for.cond.for.cond45.preheader_crit_edge, label %for.body.us.epil 186 187 for.body.us.epil: ; preds = %for.cond.for.cond45.preheader_crit_edge.loopexit147.unr-lcssa 188 %scevgep.epil = getelementptr [12 x [12 x i8]], ptr @arr_163, i32 0, i32 %ac.085.us.unr, i32 0 189 call void @llvm.memset.p0.i32(ptr align 1 %scevgep.epil, i8 %conv29, i32 %8, i1 false) 190 %epil.iter.cmp.not = icmp eq i32 %xtraiter148, 1 191 br i1 %epil.iter.cmp.not, label %for.cond.for.cond45.preheader_crit_edge, label %for.body.us.epil.1 192 193 for.cond.for.cond45.preheader_crit_edge: ; preds = %for.body.us.us115.epil.2, %for.body.us.us115.epil.1, %for.body.us.epil.2, %for.body.us.epil.1, %for.body.us.epil, %for.cond.for.cond45.preheader_crit_edge.loopexit147.unr-lcssa, %for.body.us.us115.epil, %for.cond.for.cond45.preheader_crit_edge.loopexit.unr-lcssa, %for.cond.for.cond45.preheader_crit_edge.loopexit135, %for.body.lr.ph.split.split, %for.body.lr.ph.split.split.us 194 %.us-phi = phi i32 [ %cond41.us.us, %for.cond.for.cond45.preheader_crit_edge.loopexit135 ], [ %spec.select, %for.body.lr.ph.split.split.us ], [ %spec.select143, %for.body.lr.ph.split.split ], [ %lor.ext, %for.body.us.us115.epil ], [ %lor.ext, %for.body.us.us115.epil.1 ], [ %lor.ext, %for.body.us.us115.epil.2 ], [ %lor.ext, %for.cond.for.cond45.preheader_crit_edge.loopexit.unr-lcssa ], [ %conv36, %for.body.us.epil ], [ %conv36, %for.body.us.epil.1 ], [ %conv36, %for.body.us.epil.2 ], [ %conv36, %for.cond.for.cond45.preheader_crit_edge.loopexit147.unr-lcssa ] 195 store i32 %.us-phi, ptr @var_81, align 4 196 br label %for.cond45.preheader 197 198 for.cond45.preheader: ; preds = %for.cond.for.cond45.preheader_crit_edge, %entry 199 %tobool54.not = icmp eq i32 %q, 0 200 %tobool56.not = icmp eq i32 %j, 0 201 %conv58 = select i1 %tobool56.not, i8 22, i8 0 202 br i1 %tobool54.not, label %for.cond45.us.preheader, label %for.cond45.preheader1 203 204 for.cond45.preheader1: ; preds = %for.cond45.preheader 205 br label %for.cond45 206 207 for.cond45.us.preheader: ; preds = %for.cond45.preheader 208 br label %for.cond45.us 209 210 for.cond45.us: ; preds = %for.cond45.us.preheader, %for.cond45.us 211 br label %for.cond45.us 212 213 for.cond45: ; preds = %for.cond45.preheader1, %for.cond45 214 %ag.0 = phi i32 [ %cond51.3, %for.cond45 ], [ 0, %for.cond45.preheader1 ] 215 %conv46 = and i32 %ag.0, 255 216 %tobool47.not = icmp eq i32 %conv46, 0 217 %cond51 = select i1 %tobool47.not, i32 %l, i32 %h 218 %idxprom = and i32 %cond51, 255 219 %arrayidx59 = getelementptr inbounds [22 x i8], ptr @arr_239, i32 0, i32 %idxprom 220 store i8 %conv58, ptr %arrayidx59, align 1 221 %conv46.1 = and i32 %cond51, 255 222 %tobool47.not.1 = icmp eq i32 %conv46.1, 0 223 %cond51.1 = select i1 %tobool47.not.1, i32 %l, i32 %h 224 %idxprom.1 = and i32 %cond51.1, 255 225 %arrayidx59.1 = getelementptr inbounds [22 x i8], ptr @arr_239, i32 0, i32 %idxprom.1 226 store i8 %conv58, ptr %arrayidx59.1, align 1 227 %conv46.2 = and i32 %cond51.1, 255 228 %tobool47.not.2 = icmp eq i32 %conv46.2, 0 229 %cond51.2 = select i1 %tobool47.not.2, i32 %l, i32 %h 230 %idxprom.2 = and i32 %cond51.2, 255 231 %arrayidx59.2 = getelementptr inbounds [22 x i8], ptr @arr_239, i32 0, i32 %idxprom.2 232 store i8 %conv58, ptr %arrayidx59.2, align 1 233 %conv46.3 = and i32 %cond51.2, 255 234 %tobool47.not.3 = icmp eq i32 %conv46.3, 0 235 %cond51.3 = select i1 %tobool47.not.3, i32 %l, i32 %h 236 %idxprom.3 = and i32 %cond51.3, 255 237 %arrayidx59.3 = getelementptr inbounds [22 x i8], ptr @arr_239, i32 0, i32 %idxprom.3 238 store i8 %conv58, ptr %arrayidx59.3, align 1 239 br label %for.cond45 240 241 for.body.us.epil.1: ; preds = %for.body.us.epil 242 %add43.us.epil = add nuw nsw i32 %ac.085.us.unr, 1 243 %scevgep.epil.1 = getelementptr [12 x [12 x i8]], ptr @arr_163, i32 0, i32 %add43.us.epil, i32 0 244 call void @llvm.memset.p0.i32(ptr align 1 %scevgep.epil.1, i8 %conv29, i32 %8, i1 false) 245 %epil.iter.cmp.1.not = icmp eq i32 %xtraiter148, 2 246 br i1 %epil.iter.cmp.1.not, label %for.cond.for.cond45.preheader_crit_edge, label %for.body.us.epil.2 247 248 for.body.us.epil.2: ; preds = %for.body.us.epil.1 249 %add43.us.epil.1 = add nuw nsw i32 %ac.085.us.unr, 2 250 %scevgep.epil.2 = getelementptr [12 x [12 x i8]], ptr @arr_163, i32 0, i32 %add43.us.epil.1, i32 0 251 call void @llvm.memset.p0.i32(ptr align 1 %scevgep.epil.2, i8 %conv29, i32 %8, i1 false) 252 br label %for.cond.for.cond45.preheader_crit_edge 253 254 for.body.us.us115.epil.1: ; preds = %for.body.us.us115.epil 255 %add43.us.us120.epil = add nuw nsw i32 %ac.085.us.us116.unr, 1 256 %scevgep138.epil.1 = getelementptr [12 x [12 x i8]], ptr @arr_163, i32 0, i32 %add43.us.us120.epil, i32 0 257 call void @llvm.memset.p0.i32(ptr align 1 %scevgep138.epil.1, i8 %conv29, i32 %8, i1 false) 258 %epil.iter.cmp150.1.not = icmp eq i32 %xtraiter148, 2 259 br i1 %epil.iter.cmp150.1.not, label %for.cond.for.cond45.preheader_crit_edge, label %for.body.us.us115.epil.2 260 261 for.body.us.us115.epil.2: ; preds = %for.body.us.us115.epil.1 262 %add43.us.us120.epil.1 = add nuw nsw i32 %ac.085.us.us116.unr, 2 263 %scevgep138.epil.2 = getelementptr [12 x [12 x i8]], ptr @arr_163, i32 0, i32 %add43.us.us120.epil.1, i32 0 264 call void @llvm.memset.p0.i32(ptr align 1 %scevgep138.epil.2, i8 %conv29, i32 %8, i1 false) 265 br label %for.cond.for.cond45.preheader_crit_edge 266 267 for.body.us.us.epil.1: ; preds = %for.body.us.us.epil 268 %add43.us.us.epil = add nuw nsw i32 %ac.085.us.us.unr, 1 269 %scevgep140.epil.1 = getelementptr [12 x [12 x i8]], ptr @arr_163, i32 0, i32 %add43.us.us.epil, i32 0 270 call void @llvm.memset.p0.i32(ptr align 1 %scevgep140.epil.1, i8 %conv29, i32 %3, i1 false) 271 %epil.iter.cmp156.1.not = icmp eq i32 %xtraiter154, 2 272 br i1 %epil.iter.cmp156.1.not, label %for.cond.for.cond45.preheader_crit_edge.loopexit135, label %for.body.us.us.epil.2 273 274 for.body.us.us.epil.2: ; preds = %for.body.us.us.epil.1 275 %add43.us.us.epil.1 = add nuw nsw i32 %ac.085.us.us.unr, 2 276 %scevgep140.epil.2 = getelementptr [12 x [12 x i8]], ptr @arr_163, i32 0, i32 %add43.us.us.epil.1, i32 0 277 call void @llvm.memset.p0.i32(ptr align 1 %scevgep140.epil.2, i8 %conv29, i32 %3, i1 false) 278 br label %for.cond.for.cond45.preheader_crit_edge.loopexit135 279 } 280 281 declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg) 282 283... 284--- 285name: test 286tracksRegLiveness: true 287liveins: 288 - { reg: '$r0', virtual-reg: '' } 289 - { reg: '$r1', virtual-reg: '' } 290 - { reg: '$r2', virtual-reg: '' } 291 - { reg: '$r3', virtual-reg: '' } 292fixedStack: 293 - { id: 0, type: default, offset: 24, size: 4, alignment: 8, stack-id: default, 294 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 295 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 296 - { id: 1, type: default, offset: 20, size: 4, alignment: 4, stack-id: default, 297 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 298 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 299 - { id: 2, type: default, offset: 16, size: 4, alignment: 8, stack-id: default, 300 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 301 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 302 - { id: 3, type: default, offset: 12, size: 4, alignment: 4, stack-id: default, 303 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 304 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 305 - { id: 4, type: default, offset: 8, size: 4, alignment: 8, stack-id: default, 306 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 307 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 308 - { id: 5, type: default, offset: 4, size: 4, alignment: 4, stack-id: default, 309 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 310 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 311 - { id: 6, type: default, offset: 0, size: 4, alignment: 8, stack-id: default, 312 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 313 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 314stack: 315 - { id: 0, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4, 316 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 317 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 318 - { id: 1, name: '', type: spill-slot, offset: -44, size: 4, alignment: 4, 319 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 320 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 321 - { id: 2, name: '', type: spill-slot, offset: -48, size: 4, alignment: 4, 322 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 323 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 324 - { id: 3, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 325 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true, 326 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 327 - { id: 4, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 328 stack-id: default, callee-saved-register: '$r11', callee-saved-restored: true, 329 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 330 - { id: 5, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 331 stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true, 332 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 333 - { id: 6, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 334 stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true, 335 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 336 - { id: 7, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, 337 stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true, 338 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 339 - { id: 8, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, 340 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 341 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 342 - { id: 9, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4, 343 stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true, 344 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 345 - { id: 10, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4, 346 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 347 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 348 - { id: 11, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4, 349 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 350 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 351body: | 352 bb.0.entry: 353 successors: %bb.1(0x50000000), %bb.61(0x30000000) 354 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr 355 356 $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr 357 frame-setup CFI_INSTRUCTION def_cfa_offset 36 358 frame-setup CFI_INSTRUCTION offset $lr, -4 359 frame-setup CFI_INSTRUCTION offset $r11, -8 360 frame-setup CFI_INSTRUCTION offset $r10, -12 361 frame-setup CFI_INSTRUCTION offset $r9, -16 362 frame-setup CFI_INSTRUCTION offset $r8, -20 363 frame-setup CFI_INSTRUCTION offset $r7, -24 364 frame-setup CFI_INSTRUCTION offset $r6, -28 365 frame-setup CFI_INSTRUCTION offset $r5, -32 366 frame-setup CFI_INSTRUCTION offset $r4, -36 367 $sp = frame-setup tSUBspi $sp, 3, 14 /* CC::al */, $noreg 368 frame-setup CFI_INSTRUCTION def_cfa_offset 48 369 $r9, $r6 = t2LDRDi8 $sp, 56, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.4, align 8), (load (s32) from %fixed-stack.3) 370 $r8, $r12 = t2LDRDi8 $sp, 48, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.6, align 8), (load (s32) from %fixed-stack.5) 371 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 372 renamable $r11 = t2CSEL renamable $r12, renamable $r2, 0, implicit killed $cpsr 373 t2CMPri renamable $r9, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 374 renamable $lr = t2CSINC $zr, $zr, 0, implicit killed $cpsr 375 tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 376 renamable $r4 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 377 renamable $r7 = tLDRspi $sp, 16, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.2, align 8) 378 t2IT 0, 8, implicit-def $itstate 379 $r4 = tMOVi8 $noreg, 5, 0 /* CC::eq */, killed $cpsr, implicit killed renamable $r4, implicit killed $itstate 380 tCMPhir killed renamable $r4, renamable $r9, 14 /* CC::al */, $noreg, implicit-def $cpsr 381 renamable $r4 = t2CSINC $zr, $zr, 13, implicit killed $cpsr 382 renamable $r5 = tLDRspi $sp, 18, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) 383 tSTRspi killed renamable $r4, $sp, 2, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) 384 dead renamable $r4 = t2ORRrr renamable $r6, renamable $r7, 14 /* CC::al */, $noreg, def $cpsr 385 renamable $r4 = t2CSINC $zr, $zr, 0, implicit killed $cpsr 386 t2CMPri renamable $r8, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 387 renamable $r10 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 388 t2Bcc %bb.61, 11 /* CC::lt */, killed $cpsr 389 390 bb.1.for.body.lr.ph: 391 successors: %bb.37(0x40000000), %bb.2(0x40000000) 392 liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r6, $r7, $r8, $r9, $r10, $r11, $r12 393 394 renamable $r5 = tLDRspi $sp, 17, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.1) 395 tSTRspi killed renamable $r4, $sp, 1, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1) 396 renamable $r4, dead $cpsr = tMOVi8 9, 14 /* CC::al */, $noreg 397 renamable $r4 = t2SDIV killed renamable $r4, renamable $r5, 14 /* CC::al */, $noreg 398 renamable $r7 = t2ANDrs killed renamable $r7, killed renamable $r6, 249, 14 /* CC::al */, $noreg, $noreg 399 renamable $r5, dead $cpsr = tMUL killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg 400 $r4 = t2MOVi16 42736, 14 /* CC::al */, $noreg 401 $r4 = t2MOVTi16 killed $r4, 42423, 14 /* CC::al */, $noreg 402 tCMPr renamable $r2, killed renamable $r4, 14 /* CC::al */, $noreg, implicit-def $cpsr 403 renamable $r6 = t2RSBri killed renamable $r5, 9, 14 /* CC::al */, $noreg, $noreg 404 t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr 405 406 bb.37.for.body.lr.ph.split: 407 successors: %bb.38(0x40000000), %bb.39(0x40000000) 408 liveins: $lr, $r0, $r1, $r3, $r6, $r7, $r9, $r10, $r11, $r12 409 410 tCMPr killed renamable $r6, killed renamable $r7, 14 /* CC::al */, $noreg, implicit-def $cpsr 411 t2Bcc %bb.39, 10 /* CC::ge */, killed $cpsr 412 413 bb.38.for.body.lr.ph.split.split.us: 414 successors: %bb.39(0x80000000) 415 liveins: $lr, $r0, $r1, $r3, $r9, $r10, $r11, $r12 416 417 $r4 = t2MOVi16 target-flags(arm-lo16) @var_76, 14 /* CC::al */, $noreg 418 renamable $r2 = t2ASRri renamable $r11, 31, 14 /* CC::al */, $noreg, $noreg 419 $r4 = t2MOVTi16 killed $r4, target-flags(arm-hi16) @var_76, 14 /* CC::al */, $noreg 420 t2STRDi8 killed $r11, killed $r2, killed $r4, 0, 14 /* CC::al */, $noreg :: (store (s32) into @var_76, align 8), (store (s32) into @var_76 + 4, basealign 8) 421 $r2 = t2MOVi16 target-flags(arm-lo16) @var_77, 14 /* CC::al */, $noreg 422 $r2 = t2MOVTi16 killed $r2, target-flags(arm-hi16) @var_77, 14 /* CC::al */, $noreg 423 t2STRBi12 killed renamable $lr, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s8) into @var_77) 424 425 bb.39.for.body.lr.ph.split.split: 426 successors: %bb.59(0x80000000) 427 liveins: $r1, $r3, $r12, $r10, $r0, $r9 428 429 renamable $r2 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1) 430 t2CMPri killed renamable $r9, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 431 renamable $r0 = t2CSEL killed renamable $r2, killed renamable $r0, 0, implicit killed $cpsr 432 t2B %bb.59, 14 /* CC::al */, $noreg 433 434 bb.2.for.body.lr.ph.split.us: 435 successors: %bb.3(0x40000000), %bb.14(0x40000000) 436 liveins: $lr, $r0, $r1, $r2, $r3, $r6, $r7, $r8, $r9, $r10, $r11, $r12 437 438 tCMPr killed renamable $r6, killed renamable $r7, 14 /* CC::al */, $noreg, implicit-def $cpsr 439 tSTRspi killed renamable $r3, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2) 440 t2Bcc %bb.14, 10 /* CC::ge */, killed $cpsr 441 442 bb.3.for.body.lr.ph.split.us.split.us: 443 successors: %bb.4(0x40000000), %bb.5(0x40000000) 444 liveins: $lr, $r0, $r1, $r2, $r8, $r9, $r10, $r11, $r12 445 446 $r4 = t2MOVi16 target-flags(arm-lo16) @var_76, 14 /* CC::al */, $noreg 447 renamable $r3 = t2ASRri renamable $r11, 31, 14 /* CC::al */, $noreg, $noreg 448 $r4 = t2MOVTi16 killed $r4, target-flags(arm-hi16) @var_76, 14 /* CC::al */, $noreg 449 t2STRDi8 killed $r11, killed $r3, killed $r4, 0, 14 /* CC::al */, $noreg :: (store (s32) into @var_76, align 8), (store (s32) into @var_76 + 4, basealign 8) 450 $r3 = t2MOVi16 target-flags(arm-lo16) @var_77, 14 /* CC::al */, $noreg 451 $r3 = t2MOVTi16 killed $r3, target-flags(arm-hi16) @var_77, 14 /* CC::al */, $noreg 452 t2STRBi12 killed renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s8) into @var_77) 453 $r3 = t2MOVi16 22800, 14 /* CC::al */, $noreg 454 $r3 = t2MOVTi16 killed $r3, 23112, 14 /* CC::al */, $noreg 455 renamable $r11 = t2ADDrr killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg 456 renamable $r2 = nsw t2SUBri renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg 457 tCMPi8 killed renamable $r2, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr 458 renamable $r3 = t2ANDri renamable $r8, 3, 14 /* CC::al */, $noreg, $noreg 459 t2Bcc %bb.5, 2 /* CC::hs */, killed $cpsr 460 461 bb.4: 462 successors: %bb.41(0x80000000) 463 liveins: $r0, $r1, $r3, $r9, $r10, $r11, $r12 464 465 renamable $r4, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 466 467 bb.41.for.cond.for.cond45.preheader_crit_edge.loopexit135.unr-lcssa: 468 successors: %bb.45(0x30000000), %bb.42(0x50000000) 469 liveins: $r0, $r1, $r3, $r4, $r9, $r10, $r11, $r12 470 471 renamable $r7 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 472 tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 473 t2Bcc %bb.45, 0 /* CC::eq */, killed $cpsr 474 475 bb.42.for.body.us.us.epil: 476 successors: %bb.44(0x40000000), %bb.43(0x40000000) 477 liveins: $r0, $r1, $r3, $r4, $r7, $r9, $r10, $r11, $r12 478 479 $r8 = t2MOVi16 target-flags(arm-lo16) @arr_163, 14 /* CC::al */, $noreg 480 renamable $r5 = t2ADDrs killed renamable $r4, renamable $r4, 10, 14 /* CC::al */, $noreg, $noreg 481 $r8 = t2MOVTi16 killed $r8, target-flags(arm-hi16) @arr_163, 14 /* CC::al */, $noreg 482 renamable $r2 = t2ADDri renamable $r11, 15, 14 /* CC::al */, $noreg, $noreg 483 renamable $r6 = t2ADDrs renamable $r8, renamable $r5, 18, 14 /* CC::al */, $noreg, $noreg 484 renamable $q0 = MVE_VDUP8 renamable $r7, 0, $noreg, $noreg, undef renamable $q0 485 renamable $r4, dead $cpsr = tLSRri killed renamable $r2, 4, 14 /* CC::al */, $noreg 486 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 487 renamable $lr = t2WhileLoopStartTP renamable $r4, renamable $r11, %bb.44, implicit-def dead $cpsr 488 t2B %bb.43, 14 /* CC::al */, $noreg 489 490 bb.43: 491 successors: %bb.43(0x40000000), %bb.44(0x40000000) 492 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 493 494 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 495 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 496 MVE_VPST 8, implicit $vpr 497 renamable $r6 = MVE_VSTRBU8_post renamable $q0, killed renamable $r6, 16, 1, killed renamable $vpr, renamable $lr 498 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.43, implicit-def dead $cpsr 499 t2B %bb.44, 14 /* CC::al */, $noreg 500 501 bb.44.for.body.us.us.epil: 502 successors: %bb.45(0x40000000), %bb.74(0x40000000) 503 liveins: $r0, $r1, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r11, $r12 504 505 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 506 t2Bcc %bb.45, 0 /* CC::eq */, killed $cpsr 507 508 bb.74.for.body.us.us.epil.1: 509 successors: %bb.76(0x40000000), %bb.75(0x40000000) 510 liveins: $r0, $r1, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r11, $r12 511 512 renamable $r5 = t2ADDrs killed renamable $r8, killed renamable $r5, 18, 14 /* CC::al */, $noreg, $noreg 513 renamable $r6 = t2ADDri renamable $r5, 12, 14 /* CC::al */, $noreg, $noreg 514 renamable $q0 = MVE_VDUP8 renamable $r7, 0, $noreg, $noreg, undef renamable $q0 515 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 516 renamable $lr = t2WhileLoopStartTP renamable $r4, renamable $r11, %bb.76, implicit-def dead $cpsr 517 t2B %bb.75, 14 /* CC::al */, $noreg 518 519 bb.75: 520 successors: %bb.75(0x40000000), %bb.76(0x40000000) 521 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r9, $r10, $r11, $r12 522 523 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 524 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 525 MVE_VPST 8, implicit $vpr 526 renamable $r6 = MVE_VSTRBU8_post renamable $q0, killed renamable $r6, 16, 1, killed renamable $vpr, renamable $lr 527 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.75, implicit-def dead $cpsr 528 t2B %bb.76, 14 /* CC::al */, $noreg 529 530 bb.76.for.body.us.us.epil.1: 531 successors: %bb.45(0x40000000), %bb.77(0x40000000) 532 liveins: $r0, $r1, $r3, $r4, $r5, $r7, $r9, $r10, $r11, $r12 533 534 tCMPi8 killed renamable $r3, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr 535 t2Bcc %bb.45, 0 /* CC::eq */, killed $cpsr 536 537 bb.77.for.body.us.us.epil.2: 538 successors: %bb.45(0x40000000), %bb.78(0x40000000) 539 liveins: $r0, $r1, $r4, $r5, $r7, $r9, $r10, $r11, $r12 540 541 renamable $r5, dead $cpsr = tADDi8 killed renamable $r5, 24, 14 /* CC::al */, $noreg 542 renamable $q0 = MVE_VDUP8 killed renamable $r7, 0, $noreg, $noreg, undef renamable $q0 543 renamable $lr = t2WhileLoopStartTP killed renamable $r4, renamable $r11, %bb.45, implicit-def dead $cpsr 544 t2B %bb.78, 14 /* CC::al */, $noreg 545 546 bb.78: 547 successors: %bb.78(0x40000000), %bb.45(0x40000000) 548 liveins: $lr, $q0, $r0, $r1, $r5, $r9, $r10, $r11, $r12 549 550 renamable $vpr = MVE_VCTP8 renamable $r11, 0, $noreg, $noreg 551 renamable $r11 = t2SUBri killed renamable $r11, 16, 14 /* CC::al */, $noreg, $noreg 552 MVE_VPST 8, implicit $vpr 553 renamable $r5 = MVE_VSTRBU8_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr, renamable $lr 554 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.78, implicit-def dead $cpsr 555 t2B %bb.45, 14 /* CC::al */, $noreg 556 557 bb.45.for.cond.for.cond45.preheader_crit_edge.loopexit135: 558 successors: %bb.58(0x80000000) 559 liveins: $r0, $r1, $r9, $r10, $r12 560 561 renamable $r2 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1) 562 t2CMPri killed renamable $r9, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 563 renamable $r0 = t2CSEL killed renamable $r2, killed renamable $r0, 0, implicit killed $cpsr 564 t2B %bb.58, 14 /* CC::al */, $noreg 565 566 bb.14.for.body.lr.ph.split.us.split: 567 successors: %bb.17(0x30000000), %bb.15(0x50000000) 568 liveins: $r0, $r1, $r2, $r8, $r9, $r10, $r12 569 570 $r3 = t2MOVi16 22800, 14 /* CC::al */, $noreg 571 $r3 = t2MOVTi16 killed $r3, 23112, 14 /* CC::al */, $noreg 572 renamable $r11 = t2ADDrr killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg 573 renamable $r2 = nsw t2SUBri renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg 574 t2CMPri killed renamable $r9, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 575 renamable $r9 = t2ANDri renamable $r8, 3, 14 /* CC::al */, $noreg, $noreg 576 t2Bcc %bb.17, 0 /* CC::eq */, killed $cpsr 577 578 bb.15.for.body.us.preheader: 579 successors: %bb.16(0x40000000), %bb.28(0x40000000) 580 liveins: $r0, $r1, $r2, $r8, $r9, $r10, $r11, $r12 581 582 $r3 = t2MOVi16 target-flags(arm-lo16) @arr_163, 14 /* CC::al */, $noreg 583 tCMPi8 killed renamable $r2, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr 584 $r3 = t2MOVTi16 killed $r3, target-flags(arm-hi16) @arr_163, 14 /* CC::al */, $noreg 585 t2Bcc %bb.28, 2 /* CC::hs */, killed $cpsr 586 587 bb.16: 588 successors: %bb.54(0x80000000) 589 liveins: $r0, $r1, $r3, $r9, $r10, $r11, $r12 590 591 renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 592 593 bb.54.for.cond.for.cond45.preheader_crit_edge.loopexit147.unr-lcssa: 594 successors: %bb.58(0x30000000), %bb.55(0x50000000) 595 liveins: $r0, $r1, $r3, $r6, $r9, $r10, $r11, $r12 596 597 t2CMPri renamable $r9, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 598 t2Bcc %bb.58, 0 /* CC::eq */, killed $cpsr 599 600 bb.55.for.body.us.epil: 601 successors: %bb.57(0x40000000), %bb.56(0x40000000) 602 liveins: $r0, $r1, $r3, $r6, $r9, $r10, $r11, $r12 603 604 renamable $r2 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 605 renamable $r5 = t2ADDrs killed renamable $r6, renamable $r6, 10, 14 /* CC::al */, $noreg, $noreg 606 renamable $q0 = MVE_VDUP8 killed renamable $r2, 0, $noreg, $noreg, undef renamable $q0 607 renamable $r2 = t2ADDri renamable $r11, 15, 14 /* CC::al */, $noreg, $noreg 608 renamable $r6 = t2ADDrs renamable $r3, renamable $r5, 18, 14 /* CC::al */, $noreg, $noreg 609 renamable $r4, dead $cpsr = tLSRri killed renamable $r2, 4, 14 /* CC::al */, $noreg 610 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 611 renamable $lr = t2WhileLoopStartTP renamable $r4, renamable $r11, %bb.57, implicit-def dead $cpsr 612 t2B %bb.56, 14 /* CC::al */, $noreg 613 614 bb.56: 615 successors: %bb.56(0x40000000), %bb.57(0x40000000) 616 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r9, $r10, $r11, $r12 617 618 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 619 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 620 MVE_VPST 8, implicit $vpr 621 renamable $r6 = MVE_VSTRBU8_post renamable $q0, killed renamable $r6, 16, 1, killed renamable $vpr, renamable $lr 622 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.56, implicit-def dead $cpsr 623 t2B %bb.57, 14 /* CC::al */, $noreg 624 625 bb.57.for.body.us.epil: 626 successors: %bb.58(0x40000000), %bb.64(0x40000000) 627 liveins: $r0, $r1, $r3, $r4, $r5, $r9, $r10, $r11, $r12 628 629 t2CMPri renamable $r9, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 630 t2Bcc %bb.58, 0 /* CC::eq */, killed $cpsr 631 632 bb.64.for.body.us.epil.1: 633 successors: %bb.66(0x40000000), %bb.65(0x40000000) 634 liveins: $r0, $r1, $r3, $r4, $r5, $r9, $r10, $r11, $r12 635 636 renamable $r5 = t2ADDrs killed renamable $r3, killed renamable $r5, 18, 14 /* CC::al */, $noreg, $noreg 637 renamable $r3 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 638 renamable $r6 = t2ADDri renamable $r5, 12, 14 /* CC::al */, $noreg, $noreg 639 renamable $q0 = MVE_VDUP8 renamable $r3, 0, $noreg, $noreg, undef renamable $q0 640 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 641 renamable $lr = t2WhileLoopStartTP renamable $r4, renamable $r11, %bb.66, implicit-def dead $cpsr 642 t2B %bb.65, 14 /* CC::al */, $noreg 643 644 bb.65: 645 successors: %bb.65(0x40000000), %bb.66(0x40000000) 646 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r9, $r10, $r11, $r12 647 648 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 649 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 650 MVE_VPST 8, implicit $vpr 651 renamable $r6 = MVE_VSTRBU8_post renamable $q0, killed renamable $r6, 16, 1, killed renamable $vpr, renamable $lr 652 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.65, implicit-def dead $cpsr 653 t2B %bb.66, 14 /* CC::al */, $noreg 654 655 bb.66.for.body.us.epil.1: 656 successors: %bb.58(0x40000000), %bb.67(0x40000000) 657 liveins: $r0, $r1, $r3, $r4, $r5, $r9, $r10, $r11, $r12 658 659 t2CMPri killed renamable $r9, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr 660 t2Bcc %bb.58, 0 /* CC::eq */, killed $cpsr 661 662 bb.67.for.body.us.epil.2: 663 successors: %bb.58(0x40000000), %bb.68(0x40000000) 664 liveins: $r0, $r1, $r3, $r4, $r5, $r10, $r11, $r12 665 666 renamable $r5, dead $cpsr = tADDi8 killed renamable $r5, 24, 14 /* CC::al */, $noreg 667 renamable $q0 = MVE_VDUP8 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q0 668 renamable $lr = t2WhileLoopStartTP killed renamable $r4, renamable $r11, %bb.58, implicit-def dead $cpsr 669 t2B %bb.68, 14 /* CC::al */, $noreg 670 671 bb.68: 672 successors: %bb.68(0x40000000), %bb.58(0x40000000) 673 liveins: $lr, $q0, $r0, $r1, $r5, $r10, $r11, $r12 674 675 renamable $vpr = MVE_VCTP8 renamable $r11, 0, $noreg, $noreg 676 renamable $r11 = t2SUBri killed renamable $r11, 16, 14 /* CC::al */, $noreg, $noreg 677 MVE_VPST 8, implicit $vpr 678 renamable $r5 = MVE_VSTRBU8_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr, renamable $lr 679 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.68, implicit-def dead $cpsr 680 t2B %bb.58, 14 /* CC::al */, $noreg 681 682 bb.5.for.body.lr.ph.split.us.split.us.new: 683 successors: %bb.6(0x80000000) 684 liveins: $r0, $r1, $r3, $r8, $r9, $r10, $r11, $r12 685 686 $r2 = t2MOVi16 target-flags(arm-lo16) @arr_163, 14 /* CC::al */, $noreg 687 $r2 = t2MOVTi16 killed $r2, target-flags(arm-hi16) @arr_163, 14 /* CC::al */, $noreg 688 renamable $r5 = nuw t2ADDri killed renamable $r2, 24, 14 /* CC::al */, $noreg, $noreg 689 renamable $r2 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 690 renamable $r6 = t2BICri killed renamable $r8, 3, 14 /* CC::al */, $noreg, $noreg 691 renamable $q0 = MVE_VDUP8 killed renamable $r2, 0, $noreg, $noreg, undef renamable $q0 692 renamable $r2 = t2ADDri renamable $r11, 15, 14 /* CC::al */, $noreg, $noreg 693 renamable $r4, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 694 renamable $r8 = t2LSRri killed renamable $r2, 4, 14 /* CC::al */, $noreg, $noreg 695 t2B %bb.6, 14 /* CC::al */, $noreg 696 697 bb.40.for.body.us.us (align 4): 698 successors: %bb.41(0x04000000), %bb.6(0x7c000000) 699 liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12 700 701 renamable $r4, dead $cpsr = nuw tADDi8 killed renamable $r4, 4, 14 /* CC::al */, $noreg 702 tCMPr renamable $r6, renamable $r4, 14 /* CC::al */, $noreg, implicit-def $cpsr 703 renamable $r5 = t2ADDri killed renamable $r5, 48, 14 /* CC::al */, $noreg, $noreg 704 t2Bcc %bb.41, 0 /* CC::eq */, killed $cpsr 705 706 bb.6.for.body.us.us: 707 successors: %bb.8(0x40000000), %bb.7(0x40000000) 708 liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12 709 710 renamable $r7 = t2SUBri renamable $r5, 24, 14 /* CC::al */, $noreg, $noreg 711 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 712 renamable $lr = t2WhileLoopStartTP renamable $r8, renamable $r11, %bb.8, implicit-def dead $cpsr 713 t2B %bb.7, 14 /* CC::al */, $noreg 714 715 bb.7: 716 successors: %bb.7(0x40000000), %bb.8(0x40000000) 717 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 718 719 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 720 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 721 MVE_VPST 8, implicit $vpr 722 renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr 723 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.7, implicit-def dead $cpsr 724 t2B %bb.8, 14 /* CC::al */, $noreg 725 726 bb.8.for.body.us.us: 727 successors: %bb.10(0x40000000), %bb.9(0x40000000) 728 liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12 729 730 renamable $r7 = t2SUBri renamable $r5, 12, 14 /* CC::al */, $noreg, $noreg 731 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 732 renamable $lr = t2WhileLoopStartTP renamable $r8, renamable $r11, %bb.10, implicit-def dead $cpsr 733 t2B %bb.9, 14 /* CC::al */, $noreg 734 735 bb.9: 736 successors: %bb.9(0x40000000), %bb.10(0x40000000) 737 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 738 739 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 740 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 741 MVE_VPST 8, implicit $vpr 742 renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr 743 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.9, implicit-def dead $cpsr 744 t2B %bb.10, 14 /* CC::al */, $noreg 745 746 bb.10.for.body.us.us: 747 successors: %bb.12(0x40000000), %bb.11(0x40000000) 748 liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12 749 750 $r7 = tMOVr $r5, 14 /* CC::al */, $noreg 751 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 752 renamable $lr = t2WhileLoopStartTP renamable $r8, renamable $r11, %bb.12, implicit-def dead $cpsr 753 t2B %bb.11, 14 /* CC::al */, $noreg 754 755 bb.11: 756 successors: %bb.11(0x40000000), %bb.12(0x40000000) 757 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 758 759 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 760 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 761 MVE_VPST 8, implicit $vpr 762 renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr 763 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.11, implicit-def dead $cpsr 764 t2B %bb.12, 14 /* CC::al */, $noreg 765 766 bb.12.for.body.us.us: 767 successors: %bb.40(0x40000000), %bb.13(0x40000000) 768 liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12 769 770 renamable $r7 = t2ADDri renamable $r5, 12, 14 /* CC::al */, $noreg, $noreg 771 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 772 renamable $lr = t2WhileLoopStartTP renamable $r8, renamable $r11, %bb.40, implicit-def dead $cpsr 773 t2B %bb.13, 14 /* CC::al */, $noreg 774 775 bb.13: 776 successors: %bb.13(0x40000000), %bb.40(0x40000000) 777 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 778 779 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 780 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 781 MVE_VPST 8, implicit $vpr 782 renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr 783 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.13, implicit-def dead $cpsr 784 t2B %bb.40, 14 /* CC::al */, $noreg 785 786 bb.17.for.body.us.us115.preheader: 787 successors: %bb.18(0x40000000), %bb.19(0x40000000) 788 liveins: $r1, $r2, $r8, $r9, $r10, $r11, $r12 789 790 tCMPi8 killed renamable $r2, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr 791 t2Bcc %bb.19, 2 /* CC::hs */, killed $cpsr 792 793 bb.18: 794 successors: %bb.47(0x80000000) 795 liveins: $r1, $r9, $r10, $r11, $r12 796 797 renamable $r3 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 798 renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 799 800 bb.47.for.cond.for.cond45.preheader_crit_edge.loopexit.unr-lcssa: 801 successors: %bb.48(0x30000000), %bb.49(0x50000000) 802 liveins: $r0, $r1, $r3, $r9, $r10, $r11, $r12 803 804 t2CMPri renamable $r9, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 805 t2Bcc %bb.48, 0 /* CC::eq */, killed $cpsr 806 807 bb.49.for.body.us.us115.epil: 808 successors: %bb.51(0x40000000), %bb.50(0x40000000) 809 liveins: $r0, $r1, $r3, $r9, $r10, $r11, $r12 810 811 $r5 = t2MOVi16 target-flags(arm-lo16) @arr_163, 14 /* CC::al */, $noreg 812 renamable $r4 = t2ADDrs killed renamable $r0, renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg 813 $r5 = t2MOVTi16 killed $r5, target-flags(arm-hi16) @arr_163, 14 /* CC::al */, $noreg 814 renamable $r0 = t2ADDri renamable $r11, 15, 14 /* CC::al */, $noreg, $noreg 815 renamable $r6 = t2ADDrs renamable $r5, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg 816 renamable $q0 = MVE_VDUP8 renamable $r3, 0, $noreg, $noreg, undef renamable $q0 817 renamable $r0, dead $cpsr = tLSRri killed renamable $r0, 4, 14 /* CC::al */, $noreg 818 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 819 renamable $lr = t2WhileLoopStartTP renamable $r0, renamable $r11, %bb.51, implicit-def dead $cpsr 820 t2B %bb.50, 14 /* CC::al */, $noreg 821 822 bb.50: 823 successors: %bb.50(0x40000000), %bb.51(0x40000000) 824 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r9, $r10, $r11, $r12 825 826 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 827 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 828 MVE_VPST 8, implicit $vpr 829 renamable $r6 = MVE_VSTRBU8_post renamable $q0, killed renamable $r6, 16, 1, killed renamable $vpr, renamable $lr 830 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.50, implicit-def dead $cpsr 831 t2B %bb.51, 14 /* CC::al */, $noreg 832 833 bb.51.for.body.us.us115.epil: 834 successors: %bb.48(0x40000000), %bb.52(0x40000000) 835 liveins: $r0, $r1, $r3, $r4, $r5, $r9, $r10, $r11, $r12 836 837 t2CMPri renamable $r9, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 838 t2Bcc %bb.52, 1 /* CC::ne */, killed $cpsr 839 840 bb.48: 841 successors: %bb.58(0x80000000) 842 liveins: $r10, $r1, $r12 843 844 renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1) 845 846 bb.58: 847 successors: %bb.59(0x80000000) 848 liveins: $r0, $r1, $r12, $r10 849 850 renamable $r3 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2) 851 852 bb.59.for.cond.for.cond45.preheader_crit_edge: 853 successors: %bb.60(0x80000000) 854 liveins: $r0, $r1, $r3, $r12, $r10 855 856 renamable $r5 = tLDRspi $sp, 18, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) 857 858 bb.60.for.cond.for.cond45.preheader_crit_edge: 859 successors: %bb.61(0x80000000) 860 liveins: $r0, $r1, $r3, $r5, $r10, $r12 861 862 $r2 = t2MOVi16 target-flags(arm-lo16) @var_81, 14 /* CC::al */, $noreg 863 $r2 = t2MOVTi16 killed $r2, target-flags(arm-hi16) @var_81, 14 /* CC::al */, $noreg 864 tSTRi killed renamable $r0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into @var_81) 865 866 bb.61.for.cond45.preheader: 867 successors: %bb.79(0x30000000), %bb.62(0x50000000) 868 liveins: $r1, $r3, $r5, $r10, $r12 869 870 tCMPi8 killed renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 871 t2IT 0, 8, implicit-def $itstate 872 $r10 = t2MOVi 22, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed renamable $r10, implicit killed $itstate 873 tCMPi8 killed renamable $r5, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 874 t2Bcc %bb.79, 0 /* CC::eq */, killed $cpsr 875 876 bb.62.for.cond45.preheader1: 877 successors: %bb.63(0x80000000) 878 liveins: $r1, $r10, $r12 879 880 $r0 = t2MOVi16 target-flags(arm-lo16) @arr_239, 14 /* CC::al */, $noreg 881 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 882 $r0 = t2MOVTi16 killed $r0, target-flags(arm-hi16) @arr_239, 14 /* CC::al */, $noreg 883 884 bb.63.for.cond45 (align 4): 885 successors: %bb.63(0x80000000) 886 liveins: $r0, $r1, $r2, $r10, $r12 887 888 dead renamable $r2, $cpsr = tLSLri killed renamable $r2, 24, 14 /* CC::al */, $noreg 889 renamable $r2 = t2CSEL renamable $r12, renamable $r1, 0, implicit killed $cpsr 890 renamable $r2 = tUXTB killed renamable $r2, 14 /* CC::al */, $noreg 891 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 892 t2STRBs renamable $r10, renamable $r0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx59) 893 renamable $r2 = t2CSEL renamable $r12, renamable $r1, 0, implicit killed $cpsr 894 renamable $r2 = tUXTB killed renamable $r2, 14 /* CC::al */, $noreg 895 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 896 t2STRBs renamable $r10, renamable $r0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx59.1) 897 renamable $r2 = t2CSEL renamable $r12, renamable $r1, 0, implicit killed $cpsr 898 renamable $r2 = tUXTB killed renamable $r2, 14 /* CC::al */, $noreg 899 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 900 t2STRBs renamable $r10, renamable $r0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx59.2) 901 renamable $r2 = t2CSEL renamable $r12, renamable $r1, 0, implicit killed $cpsr 902 renamable $r3 = tUXTB renamable $r2, 14 /* CC::al */, $noreg 903 t2STRBs renamable $r10, renamable $r0, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx59.3) 904 t2B %bb.63, 14 /* CC::al */, $noreg 905 906 bb.79.for.cond45.us (align 4): 907 successors: %bb.79(0x80000000) 908 909 t2B %bb.79, 14 /* CC::al */, $noreg 910 911 bb.28.for.body.us.preheader.new: 912 successors: %bb.29(0x80000000) 913 liveins: $r0, $r1, $r3, $r8, $r9, $r10, $r11, $r12 914 915 renamable $r2 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 916 renamable $r4 = nuw t2ADDri renamable $r3, 24, 14 /* CC::al */, $noreg, $noreg 917 renamable $q0 = MVE_VDUP8 killed renamable $r2, 0, $noreg, $noreg, undef renamable $q0 918 renamable $r2 = t2ADDri renamable $r11, 15, 14 /* CC::al */, $noreg, $noreg 919 renamable $r8 = t2BICri killed renamable $r8, 3, 14 /* CC::al */, $noreg, $noreg 920 renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 921 renamable $r5, dead $cpsr = tLSRri killed renamable $r2, 4, 14 /* CC::al */, $noreg 922 t2B %bb.29, 14 /* CC::al */, $noreg 923 924 bb.53.for.body.us (align 4): 925 successors: %bb.54(0x04000000), %bb.29(0x7c000000) 926 liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12 927 928 renamable $r6, dead $cpsr = nuw tADDi8 killed renamable $r6, 4, 14 /* CC::al */, $noreg 929 tCMPhir renamable $r8, renamable $r6, 14 /* CC::al */, $noreg, implicit-def $cpsr 930 renamable $r4 = t2ADDri killed renamable $r4, 48, 14 /* CC::al */, $noreg, $noreg 931 t2Bcc %bb.54, 0 /* CC::eq */, killed $cpsr 932 933 bb.29.for.body.us: 934 successors: %bb.31(0x40000000), %bb.30(0x40000000) 935 liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12 936 937 renamable $r7 = t2SUBri renamable $r4, 24, 14 /* CC::al */, $noreg, $noreg 938 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 939 renamable $lr = t2WhileLoopStartTP renamable $r5, renamable $r11, %bb.31, implicit-def dead $cpsr 940 t2B %bb.30, 14 /* CC::al */, $noreg 941 942 bb.30: 943 successors: %bb.30(0x40000000), %bb.31(0x40000000) 944 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 945 946 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 947 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 948 MVE_VPST 8, implicit $vpr 949 renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr 950 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.30, implicit-def dead $cpsr 951 t2B %bb.31, 14 /* CC::al */, $noreg 952 953 bb.31.for.body.us: 954 successors: %bb.33(0x40000000), %bb.32(0x40000000) 955 liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12 956 957 renamable $r7 = t2SUBri renamable $r4, 12, 14 /* CC::al */, $noreg, $noreg 958 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 959 renamable $lr = t2WhileLoopStartTP renamable $r5, renamable $r11, %bb.33, implicit-def dead $cpsr 960 t2B %bb.32, 14 /* CC::al */, $noreg 961 962 bb.32: 963 successors: %bb.32(0x40000000), %bb.33(0x40000000) 964 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 965 966 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 967 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 968 MVE_VPST 8, implicit $vpr 969 renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr 970 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.32, implicit-def dead $cpsr 971 t2B %bb.33, 14 /* CC::al */, $noreg 972 973 bb.33.for.body.us: 974 successors: %bb.35(0x40000000), %bb.34(0x40000000) 975 liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12 976 977 $r7 = tMOVr $r4, 14 /* CC::al */, $noreg 978 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 979 renamable $lr = t2WhileLoopStartTP renamable $r5, renamable $r11, %bb.35, implicit-def dead $cpsr 980 t2B %bb.34, 14 /* CC::al */, $noreg 981 982 bb.34: 983 successors: %bb.34(0x40000000), %bb.35(0x40000000) 984 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 985 986 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 987 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 988 MVE_VPST 8, implicit $vpr 989 renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr 990 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.34, implicit-def dead $cpsr 991 t2B %bb.35, 14 /* CC::al */, $noreg 992 993 bb.35.for.body.us: 994 successors: %bb.53(0x40000000), %bb.36(0x40000000) 995 liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12 996 997 renamable $r7 = t2ADDri renamable $r4, 12, 14 /* CC::al */, $noreg, $noreg 998 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 999 renamable $lr = t2WhileLoopStartTP renamable $r5, renamable $r11, %bb.53, implicit-def dead $cpsr 1000 t2B %bb.36, 14 /* CC::al */, $noreg 1001 1002 bb.36: 1003 successors: %bb.36(0x40000000), %bb.53(0x40000000) 1004 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 1005 1006 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 1007 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 1008 MVE_VPST 8, implicit $vpr 1009 renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr 1010 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.36, implicit-def dead $cpsr 1011 t2B %bb.53, 14 /* CC::al */, $noreg 1012 1013 bb.19.for.body.us.us115.preheader.new: 1014 successors: %bb.20(0x80000000) 1015 liveins: $r1, $r8, $r9, $r10, $r11, $r12 1016 1017 $r0 = t2MOVi16 target-flags(arm-lo16) @arr_163, 14 /* CC::al */, $noreg 1018 renamable $r3 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 1019 $r0 = t2MOVTi16 killed $r0, target-flags(arm-hi16) @arr_163, 14 /* CC::al */, $noreg 1020 renamable $r2 = t2ADDri renamable $r11, 15, 14 /* CC::al */, $noreg, $noreg 1021 renamable $r4 = nuw t2ADDri killed renamable $r0, 24, 14 /* CC::al */, $noreg, $noreg 1022 renamable $r5 = t2BICri killed renamable $r8, 3, 14 /* CC::al */, $noreg, $noreg 1023 renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1024 renamable $q0 = MVE_VDUP8 renamable $r3, 0, $noreg, $noreg, undef renamable $q0 1025 renamable $r6, dead $cpsr = tLSRri killed renamable $r2, 4, 14 /* CC::al */, $noreg 1026 t2B %bb.20, 14 /* CC::al */, $noreg 1027 1028 bb.46.for.body.us.us115 (align 4): 1029 successors: %bb.47(0x04000000), %bb.20(0x7c000000) 1030 liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r9, $r10, $r11, $r12 1031 1032 renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg 1033 tCMPr renamable $r5, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1034 renamable $r4 = t2ADDri killed renamable $r4, 48, 14 /* CC::al */, $noreg, $noreg 1035 t2Bcc %bb.47, 0 /* CC::eq */, killed $cpsr 1036 1037 bb.20.for.body.us.us115: 1038 successors: %bb.22(0x40000000), %bb.21(0x40000000) 1039 liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r9, $r10, $r11, $r12 1040 1041 renamable $r7 = t2SUBri renamable $r4, 24, 14 /* CC::al */, $noreg, $noreg 1042 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 1043 renamable $lr = t2WhileLoopStartTP renamable $r6, renamable $r11, %bb.22, implicit-def dead $cpsr 1044 t2B %bb.21, 14 /* CC::al */, $noreg 1045 1046 bb.21: 1047 successors: %bb.21(0x40000000), %bb.22(0x40000000) 1048 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r9, $r10, $r11, $r12 1049 1050 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 1051 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 1052 MVE_VPST 8, implicit $vpr 1053 renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr 1054 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.21, implicit-def dead $cpsr 1055 t2B %bb.22, 14 /* CC::al */, $noreg 1056 1057 bb.22.for.body.us.us115: 1058 successors: %bb.24(0x40000000), %bb.23(0x40000000) 1059 liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r9, $r10, $r11, $r12 1060 1061 renamable $r7 = t2SUBri renamable $r4, 12, 14 /* CC::al */, $noreg, $noreg 1062 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 1063 renamable $lr = t2WhileLoopStartTP renamable $r6, renamable $r11, %bb.24, implicit-def dead $cpsr 1064 t2B %bb.23, 14 /* CC::al */, $noreg 1065 1066 bb.23: 1067 successors: %bb.23(0x40000000), %bb.24(0x40000000) 1068 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r9, $r10, $r11, $r12 1069 1070 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 1071 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 1072 MVE_VPST 8, implicit $vpr 1073 renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr 1074 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.23, implicit-def dead $cpsr 1075 t2B %bb.24, 14 /* CC::al */, $noreg 1076 1077 bb.24.for.body.us.us115: 1078 successors: %bb.26(0x40000000), %bb.25(0x40000000) 1079 liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r9, $r10, $r11, $r12 1080 1081 $r7 = tMOVr $r4, 14 /* CC::al */, $noreg 1082 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 1083 renamable $lr = t2WhileLoopStartTP renamable $r6, renamable $r11, %bb.26, implicit-def dead $cpsr 1084 t2B %bb.25, 14 /* CC::al */, $noreg 1085 1086 bb.25: 1087 successors: %bb.25(0x40000000), %bb.26(0x40000000) 1088 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r9, $r10, $r11, $r12 1089 1090 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 1091 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 1092 MVE_VPST 8, implicit $vpr 1093 renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr 1094 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.25, implicit-def dead $cpsr 1095 t2B %bb.26, 14 /* CC::al */, $noreg 1096 1097 bb.26.for.body.us.us115: 1098 successors: %bb.46(0x40000000), %bb.27(0x40000000) 1099 liveins: $q0, $r0, $r1, $r3, $r4, $r5, $r6, $r9, $r10, $r11, $r12 1100 1101 renamable $r7 = t2ADDri renamable $r4, 12, 14 /* CC::al */, $noreg, $noreg 1102 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 1103 renamable $lr = t2WhileLoopStartTP renamable $r6, renamable $r11, %bb.46, implicit-def dead $cpsr 1104 t2B %bb.27, 14 /* CC::al */, $noreg 1105 1106 bb.27: 1107 successors: %bb.27(0x40000000), %bb.46(0x40000000) 1108 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r9, $r10, $r11, $r12 1109 1110 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 1111 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 1112 MVE_VPST 8, implicit $vpr 1113 renamable $r7 = MVE_VSTRBU8_post renamable $q0, killed renamable $r7, 16, 1, killed renamable $vpr, renamable $lr 1114 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.27, implicit-def dead $cpsr 1115 t2B %bb.46, 14 /* CC::al */, $noreg 1116 1117 bb.52.for.body.us.us115.epil.1: 1118 successors: %bb.70(0x40000000), %bb.69(0x40000000) 1119 liveins: $r0, $r1, $r3, $r4, $r5, $r9, $r10, $r11, $r12 1120 1121 renamable $r4 = t2ADDrs killed renamable $r5, killed renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg 1122 renamable $r5 = t2ADDri renamable $r4, 12, 14 /* CC::al */, $noreg, $noreg 1123 renamable $q0 = MVE_VDUP8 renamable $r3, 0, $noreg, $noreg, undef renamable $q0 1124 $r2 = tMOVr $r11, 14 /* CC::al */, $noreg 1125 renamable $lr = t2WhileLoopStartTP renamable $r0, renamable $r11, %bb.70, implicit-def dead $cpsr 1126 t2B %bb.69, 14 /* CC::al */, $noreg 1127 1128 bb.69: 1129 successors: %bb.69(0x40000000), %bb.70(0x40000000) 1130 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r9, $r10, $r11, $r12 1131 1132 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 1133 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 1134 MVE_VPST 8, implicit $vpr 1135 renamable $r5 = MVE_VSTRBU8_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr, renamable $lr 1136 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.69, implicit-def dead $cpsr 1137 t2B %bb.70, 14 /* CC::al */, $noreg 1138 1139 bb.70.for.body.us.us115.epil.1: 1140 successors: %bb.73(0x40000000), %bb.71(0x40000000) 1141 liveins: $r0, $r1, $r3, $r4, $r9, $r10, $r11, $r12 1142 1143 renamable $r5 = tLDRspi $sp, 18, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) 1144 t2CMPri killed renamable $r9, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr 1145 t2Bcc %bb.73, 0 /* CC::eq */, killed $cpsr 1146 1147 bb.71.for.body.us.us115.epil.2: 1148 successors: %bb.73(0x40000000), %bb.72(0x40000000) 1149 liveins: $r0, $r1, $r3, $r4, $r5, $r10, $r11, $r12 1150 1151 renamable $r4, dead $cpsr = tADDi8 killed renamable $r4, 24, 14 /* CC::al */, $noreg 1152 renamable $q0 = MVE_VDUP8 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q0 1153 renamable $lr = t2WhileLoopStartTP killed renamable $r0, renamable $r11, %bb.73, implicit-def dead $cpsr 1154 t2B %bb.72, 14 /* CC::al */, $noreg 1155 1156 bb.72: 1157 successors: %bb.72(0x40000000), %bb.73(0x40000000) 1158 liveins: $lr, $q0, $r1, $r4, $r5, $r10, $r11, $r12 1159 1160 renamable $vpr = MVE_VCTP8 renamable $r11, 0, $noreg, $noreg 1161 renamable $r11 = t2SUBri killed renamable $r11, 16, 14 /* CC::al */, $noreg, $noreg 1162 MVE_VPST 8, implicit $vpr 1163 renamable $r4 = MVE_VSTRBU8_post renamable $q0, killed renamable $r4, 16, 1, killed renamable $vpr, renamable $lr 1164 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.72, implicit-def dead $cpsr 1165 t2B %bb.73, 14 /* CC::al */, $noreg 1166 1167 bb.73.for.body.us.us115.epil.2: 1168 successors: %bb.60(0x80000000) 1169 liveins: $r1, $r12, $r5, $r10 1170 1171 $r3, $r0 = t2LDRDi8 $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2), (load (s32) from %stack.1) 1172 t2B %bb.60, 14 /* CC::al */, $noreg 1173 1174... 1175