1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s 3 4# TODO: Remove the lr = tMOVr which actually makes the WLS def dead! 5 6--- | 7 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 8 target triple = "thumbv8.1m.main" 9 10 define dso_local arm_aapcscc void @copy(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) { 11 entry: 12 %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N) 13 br i1 %0, label %while.body.preheader, label %while.end 14 15 while.body.preheader: ; preds = %entry 16 %scevgep = getelementptr i16, ptr %a, i32 -1 17 %scevgep3 = getelementptr i16, ptr %b, i32 -1 18 br label %while.body 19 20 while.body: ; preds = %while.body, %while.body.preheader 21 %lsr.iv4 = phi ptr [ %scevgep3, %while.body.preheader ], [ %scevgep5, %while.body ] 22 %lsr.iv = phi ptr [ %scevgep, %while.body.preheader ], [ %scevgep1, %while.body ] 23 %1 = phi i32 [ %3, %while.body ], [ %N, %while.body.preheader ] 24 %scevgep7 = getelementptr i16, ptr %lsr.iv, i32 1 25 %scevgep4 = getelementptr i16, ptr %lsr.iv4, i32 1 26 %2 = load i16, ptr %scevgep4, align 2 27 store i16 %2, ptr %scevgep7, align 2 28 %3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1) 29 %4 = icmp ne i32 %3, 0 30 %scevgep1 = getelementptr i16, ptr %lsr.iv, i32 1 31 %scevgep5 = getelementptr i16, ptr %lsr.iv4, i32 1 32 br i1 %4, label %while.body, label %while.end 33 34 while.end: ; preds = %while.body, %entry 35 ret void 36 } 37 38 declare i1 @llvm.test.set.loop.iterations.i32(i32) #0 39 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0 40 41 attributes #0 = { noduplicate nounwind } 42 attributes #1 = { nounwind } 43 44... 45--- 46name: copy 47alignment: 2 48exposesReturnsTwice: false 49legalized: false 50regBankSelected: false 51selected: false 52failedISel: false 53tracksRegLiveness: true 54hasWinCFI: false 55registers: [] 56liveins: 57 - { reg: '$r0', virtual-reg: '' } 58 - { reg: '$r1', virtual-reg: '' } 59 - { reg: '$r2', virtual-reg: '' } 60frameInfo: 61 isFrameAddressTaken: false 62 isReturnAddressTaken: false 63 hasStackMap: false 64 hasPatchPoint: false 65 stackSize: 8 66 offsetAdjustment: 0 67 maxAlignment: 4 68 adjustsStack: false 69 hasCalls: false 70 stackProtector: '' 71 maxCallFrameSize: 0 72 cvBytesOfCalleeSavedRegisters: 0 73 hasOpaqueSPAdjustment: false 74 hasVAStart: false 75 hasMustTailInVarArgFunc: false 76 localFrameSize: 0 77 savePoint: '' 78 restorePoint: '' 79fixedStack: [] 80stack: 81 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 82 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 83 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 84 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 85 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 86 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 87callSites: [] 88constants: [] 89machineFunctionInfo: {} 90body: | 91 ; CHECK-LABEL: name: copy 92 ; CHECK: bb.0.entry: 93 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000) 94 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 95 ; CHECK-NEXT: {{ $}} 96 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 97 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 98 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 99 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 100 ; CHECK-NEXT: dead $lr = t2WLS $r2, %bb.3 101 ; CHECK-NEXT: {{ $}} 102 ; CHECK-NEXT: bb.1.while.body.preheader: 103 ; CHECK-NEXT: successors: %bb.2(0x80000000) 104 ; CHECK-NEXT: liveins: $r0, $r1, $r2 105 ; CHECK-NEXT: {{ $}} 106 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14 /* CC::al */, $noreg 107 ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14 /* CC::al */, $noreg 108 ; CHECK-NEXT: $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg 109 ; CHECK-NEXT: {{ $}} 110 ; CHECK-NEXT: bb.2.while.body: 111 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 112 ; CHECK-NEXT: liveins: $lr, $r0, $r1 113 ; CHECK-NEXT: {{ $}} 114 ; CHECK-NEXT: renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14 /* CC::al */, $noreg :: (load (s16) from %ir.scevgep4) 115 ; CHECK-NEXT: early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14 /* CC::al */, $noreg :: (store (s16) into %ir.scevgep7) 116 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 117 ; CHECK-NEXT: {{ $}} 118 ; CHECK-NEXT: bb.3.while.end: 119 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 120 bb.0.entry: 121 successors: %bb.1(0x40000000), %bb.3(0x40000000) 122 liveins: $r0, $r1, $r2, $r7, $lr 123 124 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 125 frame-setup CFI_INSTRUCTION def_cfa_offset 8 126 frame-setup CFI_INSTRUCTION offset $lr, -4 127 frame-setup CFI_INSTRUCTION offset $r7, -8 128 $lr = t2WhileLoopStartLR $r2, %bb.3, implicit-def dead $cpsr 129 tB %bb.1, 14, $noreg 130 131 bb.1.while.body.preheader: 132 successors: %bb.2(0x80000000) 133 liveins: $r0, $r1, $r2 134 135 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg 136 renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg 137 $lr = tMOVr killed $r2, 14, $noreg 138 139 bb.2.while.body: 140 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 141 liveins: $lr, $r0, $r1 142 143 renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load (s16) from %ir.scevgep4) 144 early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store (s16) into %ir.scevgep7) 145 renamable $lr = t2LoopDec killed renamable $lr, 1 146 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 147 tB %bb.3, 14, $noreg 148 149 bb.3.while.end: 150 tPOP_RET 14, $noreg, def $r7, def $pc 151 152... 153