1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s 3 4--- | 5 @_ZL3arr = internal global [10 x i32] [i32 1, i32 2, i32 3, i32 5, i32 5, i32 5, i32 -2, i32 0, i32 -8, i32 -1], align 4 6 @.str = private unnamed_addr constant [5 x i8] c"%d, \00", align 1 7 8 define arm_aapcs_vfpcc void @vpt_block(ptr nocapture %A, i32 %n, i32 %x) { 9 entry: 10 %cmp9 = icmp sgt i32 %n, 0 11 %0 = add i32 %n, 3 12 %1 = lshr i32 %0, 2 13 %2 = shl nuw i32 %1, 2 14 %3 = add i32 %2, -4 15 %4 = lshr i32 %3, 2 16 %5 = add nuw nsw i32 %4, 1 17 br i1 %cmp9, label %vector.ph, label %for.cond.cleanup 18 19 vector.ph: ; preds = %entry 20 %sub = sub nsw i32 0, %x 21 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 22 br label %vector.body 23 24 vector.body: ; preds = %vector.body, %vector.ph 25 %lsr.iv1 = phi ptr [ %scevgep, %vector.body ], [ %A, %vector.ph ] 26 %6 = phi i32 [ %start, %vector.ph ], [ %18, %vector.body ] 27 %7 = phi i32 [ %n, %vector.ph ], [ %9, %vector.body ] 28 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7) 29 %9 = sub i32 %7, 4 30 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv1, i32 4, <4 x i1> %8, <4 x i32> undef) 31 %10 = insertelement <4 x i32> undef, i32 %x, i32 0 32 %11 = shufflevector <4 x i32> %10, <4 x i32> undef, <4 x i32> zeroinitializer 33 %12 = icmp slt <4 x i32> %wide.masked.load, %11 34 %13 = insertelement <4 x i32> undef, i32 %sub, i32 0 35 %14 = shufflevector <4 x i32> %13, <4 x i32> undef, <4 x i32> zeroinitializer 36 %15 = icmp sgt <4 x i32> %wide.masked.load, %14 37 %16 = and <4 x i1> %12, %15 38 %17 = and <4 x i1> %16, %8 39 call void @llvm.masked.store.v4i32.p0(<4 x i32> zeroinitializer, ptr %lsr.iv1, i32 4, <4 x i1> %17) 40 %scevgep = getelementptr i32, ptr %lsr.iv1, i32 4 41 %18 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1) 42 %19 = icmp ne i32 %18, 0 43 br i1 %19, label %vector.body, label %for.cond.cleanup 44 45 for.cond.cleanup: ; preds = %vector.body, %entry 46 ret void 47 } 48 49 define arm_aapcs_vfpcc void @different_vcpt_reaching_def(ptr nocapture %A, i32 %n, i32 %x) { 50 ; Intentionally left blank - see MIR sequence below. 51 entry: 52 unreachable 53 vector.ph: 54 unreachable 55 vector.body: 56 unreachable 57 for.cond.cleanup: 58 unreachable 59 } 60 61 define arm_aapcs_vfpcc void @different_vcpt_operand(ptr nocapture %A, i32 %n, i32 %x) { 62 ; Intentionally left blank - see MIR sequence below. 63 entry: 64 unreachable 65 vector.ph: 66 unreachable 67 vector.body: 68 unreachable 69 for.cond.cleanup: 70 unreachable 71 } 72 73 define arm_aapcs_vfpcc void @else_vcpt(ptr nocapture %data, i32 %N, i32 %T) { 74 entry: 75 %cmp9 = icmp sgt i32 %N, 0 76 %0 = add i32 %N, 3 77 %1 = lshr i32 %0, 2 78 %2 = shl nuw i32 %1, 2 79 %3 = add i32 %2, -4 80 %4 = lshr i32 %3, 2 81 %5 = add nuw nsw i32 %4, 1 82 br i1 %cmp9, label %vector.ph, label %for.cond.cleanup 83 84 vector.ph: ; preds = %entry 85 %sub = sub nsw i32 0, %T 86 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 87 br label %vector.body 88 89 vector.body: ; preds = %vector.body, %vector.ph 90 %lsr.iv1 = phi ptr [ %scevgep, %vector.body ], [ %data, %vector.ph ] 91 %6 = phi i32 [ %start, %vector.ph ], [ %18, %vector.body ] 92 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ] 93 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7) 94 %9 = sub i32 %7, 4 95 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv1, i32 4, <4 x i1> %8, <4 x i32> undef) 96 %10 = insertelement <4 x i32> undef, i32 %T, i32 0 97 %11 = shufflevector <4 x i32> %10, <4 x i32> undef, <4 x i32> zeroinitializer 98 %12 = icmp slt <4 x i32> %wide.masked.load, %11 99 %13 = insertelement <4 x i32> undef, i32 %sub, i32 0 100 %14 = shufflevector <4 x i32> %13, <4 x i32> undef, <4 x i32> zeroinitializer 101 %15 = icmp sgt <4 x i32> %wide.masked.load, %14 102 %16 = or <4 x i1> %12, %15 103 %17 = and <4 x i1> %16, %8 104 call void @llvm.masked.store.v4i32.p0(<4 x i32> zeroinitializer, ptr %lsr.iv1, i32 4, <4 x i1> %17) 105 %scevgep = getelementptr i32, ptr %lsr.iv1, i32 4 106 %18 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1) 107 %19 = icmp ne i32 %18, 0 108 br i1 %19, label %vector.body, label %for.cond.cleanup 109 110 for.cond.cleanup: ; preds = %vector.body, %entry 111 ret void 112 } 113 114 define arm_aapcs_vfpcc void @loop_invariant_vpt_operands(ptr nocapture %A, i32 %n, i32 %x) { 115 ; Intentionally left blank - see MIR sequence below. 116 entry: 117 unreachable 118 vector.ph: 119 unreachable 120 vector.body: 121 unreachable 122 for.cond.cleanup: 123 unreachable 124 } 125 126 define arm_aapcs_vfpcc void @vctp_before_vpt(ptr nocapture %A, i32 %n, i32 %x) { 127 ; Intentionally left blank - see MIR sequence below. 128 entry: 129 unreachable 130 vector.ph: 131 unreachable 132 vector.body: 133 unreachable 134 for.cond.cleanup: 135 unreachable 136 } 137 138 define arm_aapcs_vfpcc void @vpt_load_vctp_store(ptr nocapture %A, i32 %n, i32 %x) { 139 ; Intentionally left blank - see MIR sequence below. 140 entry: 141 unreachable 142 vector.ph: 143 unreachable 144 vector.body: 145 unreachable 146 for.cond.cleanup: 147 unreachable 148 } 149 150 define arm_aapcs_vfpcc void @emptyblock() { 151 unreachable 152 } 153 define arm_aapcs_vfpcc void @predvcmp() { 154 unreachable 155 } 156 define arm_aapcs_vfpcc void @predvpt() { 157 unreachable 158 } 159 160 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) 161 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>) 162 declare i32 @llvm.start.loop.iterations.i32(i32) 163 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 164 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 165... 166--- 167name: vpt_block 168alignment: 2 169exposesReturnsTwice: false 170legalized: false 171regBankSelected: false 172selected: false 173failedISel: false 174tracksRegLiveness: true 175hasWinCFI: false 176registers: [] 177liveins: 178 - { reg: '$r0', virtual-reg: '' } 179 - { reg: '$r1', virtual-reg: '' } 180 - { reg: '$r2', virtual-reg: '' } 181frameInfo: 182 isFrameAddressTaken: false 183 isReturnAddressTaken: false 184 hasStackMap: false 185 hasPatchPoint: false 186 stackSize: 8 187 offsetAdjustment: 0 188 maxAlignment: 4 189 adjustsStack: false 190 hasCalls: false 191 stackProtector: '' 192 maxCallFrameSize: 0 193 cvBytesOfCalleeSavedRegisters: 0 194 hasOpaqueSPAdjustment: false 195 hasVAStart: false 196 hasMustTailInVarArgFunc: false 197 localFrameSize: 0 198 savePoint: '' 199 restorePoint: '' 200fixedStack: [] 201stack: 202 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 203 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 204 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 205 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 206 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 207 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 208callSites: [] 209constants: [] 210machineFunctionInfo: {} 211body: | 212 ; CHECK-LABEL: name: vpt_block 213 ; CHECK: bb.0.entry: 214 ; CHECK-NEXT: successors: %bb.1(0x80000000) 215 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 216 ; CHECK-NEXT: {{ $}} 217 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 218 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 219 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 220 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 221 ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 222 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate 223 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 224 ; CHECK-NEXT: {{ $}} 225 ; CHECK-NEXT: bb.1.vector.ph: 226 ; CHECK-NEXT: successors: %bb.2(0x80000000) 227 ; CHECK-NEXT: liveins: $r0, $r1, $r2 228 ; CHECK-NEXT: {{ $}} 229 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 230 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 231 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r1 232 ; CHECK-NEXT: {{ $}} 233 ; CHECK-NEXT: bb.2.vector.body: 234 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 235 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r2, $r3 236 ; CHECK-NEXT: {{ $}} 237 ; CHECK-NEXT: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg 238 ; CHECK-NEXT: MVE_VPTv4s32r 4, renamable $q1, renamable $r2, 11, implicit-def $vpr 239 ; CHECK-NEXT: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg 240 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg 241 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 242 ; CHECK-NEXT: {{ $}} 243 ; CHECK-NEXT: bb.3.for.cond.cleanup: 244 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 245 bb.0.entry: 246 successors: %bb.1(0x80000000) 247 liveins: $r0, $r1, $r2, $r7, $lr 248 249 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 250 frame-setup CFI_INSTRUCTION def_cfa_offset 8 251 frame-setup CFI_INSTRUCTION offset $lr, -4 252 frame-setup CFI_INSTRUCTION offset $r7, -8 253 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 254 t2IT 11, 8, implicit-def $itstate 255 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 256 257 bb.1.vector.ph: 258 successors: %bb.2(0x80000000) 259 liveins: $r0, $r1, $r2, $r7, $lr 260 261 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 262 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 263 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 264 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 265 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 266 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 267 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 268 $lr = t2DoLoopStart renamable $lr 269 270 bb.2.vector.body: 271 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 272 liveins: $lr, $q0, $r0, $r1, $r2, $r3 273 274 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg 275 MVE_VPST 8, implicit $vpr 276 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg 277 MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr 278 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg 279 renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg 280 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg 281 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 282 renamable $lr = t2LoopDec killed renamable $lr, 1 283 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 284 tB %bb.3, 14 /* CC::al */, $noreg 285 286 bb.3.for.cond.cleanup: 287 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 288... 289# Tests that secondary VCTPs are refused when their operand's reaching definition is not the same as the main 290# VCTP's. 291--- 292name: different_vcpt_reaching_def 293alignment: 2 294exposesReturnsTwice: false 295legalized: false 296regBankSelected: false 297selected: false 298failedISel: false 299tracksRegLiveness: true 300hasWinCFI: false 301registers: [] 302liveins: 303 - { reg: '$r0', virtual-reg: '' } 304 - { reg: '$r1', virtual-reg: '' } 305 - { reg: '$r2', virtual-reg: '' } 306frameInfo: 307 isFrameAddressTaken: false 308 isReturnAddressTaken: false 309 hasStackMap: false 310 hasPatchPoint: false 311 stackSize: 8 312 offsetAdjustment: 0 313 maxAlignment: 4 314 adjustsStack: false 315 hasCalls: false 316 stackProtector: '' 317 maxCallFrameSize: 0 318 cvBytesOfCalleeSavedRegisters: 0 319 hasOpaqueSPAdjustment: false 320 hasVAStart: false 321 hasMustTailInVarArgFunc: false 322 localFrameSize: 0 323 savePoint: '' 324 restorePoint: '' 325fixedStack: [] 326stack: 327 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 328 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 329 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 330 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 331 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 332 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 333callSites: [] 334constants: [] 335machineFunctionInfo: {} 336body: | 337 ; CHECK-LABEL: name: different_vcpt_reaching_def 338 ; CHECK: bb.0.entry: 339 ; CHECK-NEXT: successors: %bb.1(0x80000000) 340 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 341 ; CHECK-NEXT: {{ $}} 342 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 343 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 344 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 345 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 346 ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 347 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate 348 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 349 ; CHECK-NEXT: {{ $}} 350 ; CHECK-NEXT: bb.1.vector.ph: 351 ; CHECK-NEXT: successors: %bb.2(0x80000000) 352 ; CHECK-NEXT: liveins: $r0, $r1, $r2 353 ; CHECK-NEXT: {{ $}} 354 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 355 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 356 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 357 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 358 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 359 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 360 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 361 ; CHECK-NEXT: {{ $}} 362 ; CHECK-NEXT: bb.2.vector.body: 363 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 364 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3 365 ; CHECK-NEXT: {{ $}} 366 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg 367 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 368 ; CHECK-NEXT: renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, renamable $vpr, $noreg 369 ; CHECK-NEXT: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg 370 ; CHECK-NEXT: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr 371 ; CHECK-NEXT: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg 372 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg 373 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg 374 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 375 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 376 ; CHECK-NEXT: {{ $}} 377 ; CHECK-NEXT: bb.3.for.cond.cleanup: 378 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 379 bb.0.entry: 380 successors: %bb.1(0x80000000) 381 liveins: $r0, $r1, $r2, $r7, $lr 382 383 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 384 frame-setup CFI_INSTRUCTION def_cfa_offset 8 385 frame-setup CFI_INSTRUCTION offset $lr, -4 386 frame-setup CFI_INSTRUCTION offset $r7, -8 387 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 388 t2IT 11, 8, implicit-def $itstate 389 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 390 391 bb.1.vector.ph: 392 successors: %bb.2(0x80000000) 393 liveins: $r0, $r1, $r2, $r7, $lr 394 395 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 396 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 397 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 398 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 399 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 400 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 401 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 402 $lr = t2DoLoopStart renamable $lr 403 404 bb.2.vector.body: 405 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 406 liveins: $lr, $q0, $r0, $r1, $r2, $r3 407 408 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg 409 MVE_VPST 8, implicit $vpr 410 renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, renamable $vpr, $noreg 411 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg 412 MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr 413 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg 414 renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg 415 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg 416 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 417 renamable $lr = t2LoopDec killed renamable $lr, 1 418 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 419 tB %bb.3, 14 /* CC::al */, $noreg 420 421 bb.3.for.cond.cleanup: 422 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 423... 424# Tests that secondary VCTPs are refused when their operand is not the same register as the main VCTP's. 425--- 426name: different_vcpt_operand 427alignment: 2 428exposesReturnsTwice: false 429legalized: false 430regBankSelected: false 431selected: false 432failedISel: false 433tracksRegLiveness: true 434hasWinCFI: false 435registers: [] 436liveins: 437 - { reg: '$r0', virtual-reg: '' } 438 - { reg: '$r1', virtual-reg: '' } 439 - { reg: '$r2', virtual-reg: '' } 440frameInfo: 441 isFrameAddressTaken: false 442 isReturnAddressTaken: false 443 hasStackMap: false 444 hasPatchPoint: false 445 stackSize: 8 446 offsetAdjustment: 0 447 maxAlignment: 4 448 adjustsStack: false 449 hasCalls: false 450 stackProtector: '' 451 maxCallFrameSize: 0 452 cvBytesOfCalleeSavedRegisters: 0 453 hasOpaqueSPAdjustment: false 454 hasVAStart: false 455 hasMustTailInVarArgFunc: false 456 localFrameSize: 0 457 savePoint: '' 458 restorePoint: '' 459fixedStack: [] 460stack: 461 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 462 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 463 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 464 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 465 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 466 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 467callSites: [] 468constants: [] 469machineFunctionInfo: {} 470body: | 471 ; CHECK-LABEL: name: different_vcpt_operand 472 ; CHECK: bb.0.entry: 473 ; CHECK-NEXT: successors: %bb.1(0x80000000) 474 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 475 ; CHECK-NEXT: {{ $}} 476 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 477 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 478 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 479 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 480 ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 481 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate 482 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 483 ; CHECK-NEXT: {{ $}} 484 ; CHECK-NEXT: bb.1.vector.ph: 485 ; CHECK-NEXT: successors: %bb.2(0x80000000) 486 ; CHECK-NEXT: liveins: $r0, $r1, $r2 487 ; CHECK-NEXT: {{ $}} 488 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 489 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 490 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 491 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 492 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 493 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 494 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 495 ; CHECK-NEXT: {{ $}} 496 ; CHECK-NEXT: bb.2.vector.body: 497 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 498 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3 499 ; CHECK-NEXT: {{ $}} 500 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg 501 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 502 ; CHECK-NEXT: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg 503 ; CHECK-NEXT: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr 504 ; CHECK-NEXT: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg 505 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg 506 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg 507 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 508 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 509 ; CHECK-NEXT: {{ $}} 510 ; CHECK-NEXT: bb.3.for.cond.cleanup: 511 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 512 bb.0.entry: 513 successors: %bb.1(0x80000000) 514 liveins: $r0, $r1, $r2, $r7, $lr 515 516 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 517 frame-setup CFI_INSTRUCTION def_cfa_offset 8 518 frame-setup CFI_INSTRUCTION offset $lr, -4 519 frame-setup CFI_INSTRUCTION offset $r7, -8 520 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 521 t2IT 11, 8, implicit-def $itstate 522 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 523 524 bb.1.vector.ph: 525 successors: %bb.2(0x80000000) 526 liveins: $r0, $r1, $r2, $r7, $lr 527 528 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 529 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 530 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 531 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 532 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 533 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 534 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 535 $lr = t2DoLoopStart renamable $lr 536 537 bb.2.vector.body: 538 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 539 liveins: $lr, $q0, $r0, $r1, $r2, $r3 540 541 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg 542 MVE_VPST 8, implicit $vpr 543 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg 544 MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr 545 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg 546 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg 547 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg 548 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 549 renamable $lr = t2LoopDec killed renamable $lr, 1 550 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 551 tB %bb.3, 14 /* CC::al */, $noreg 552 553 bb.3.for.cond.cleanup: 554 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 555... 556# Test including a else-predicated VCTP. 557--- 558name: else_vcpt 559alignment: 2 560exposesReturnsTwice: false 561legalized: false 562regBankSelected: false 563selected: false 564failedISel: false 565tracksRegLiveness: true 566hasWinCFI: false 567registers: [] 568liveins: 569 - { reg: '$r0', virtual-reg: '' } 570 - { reg: '$r1', virtual-reg: '' } 571 - { reg: '$r2', virtual-reg: '' } 572frameInfo: 573 isFrameAddressTaken: false 574 isReturnAddressTaken: false 575 hasStackMap: false 576 hasPatchPoint: false 577 stackSize: 8 578 offsetAdjustment: 0 579 maxAlignment: 4 580 adjustsStack: false 581 hasCalls: false 582 stackProtector: '' 583 maxCallFrameSize: 0 584 cvBytesOfCalleeSavedRegisters: 0 585 hasOpaqueSPAdjustment: false 586 hasVAStart: false 587 hasMustTailInVarArgFunc: false 588 localFrameSize: 0 589 savePoint: '' 590 restorePoint: '' 591fixedStack: [] 592stack: 593 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 594 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 595 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 596 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 597 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 598 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 599callSites: [] 600constants: [] 601machineFunctionInfo: {} 602body: | 603 ; CHECK-LABEL: name: else_vcpt 604 ; CHECK: bb.0.entry: 605 ; CHECK-NEXT: successors: %bb.1(0x80000000) 606 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 607 ; CHECK-NEXT: {{ $}} 608 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 609 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 610 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 611 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 612 ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 613 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate 614 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 615 ; CHECK-NEXT: {{ $}} 616 ; CHECK-NEXT: bb.1.vector.ph: 617 ; CHECK-NEXT: successors: %bb.2(0x80000000) 618 ; CHECK-NEXT: liveins: $r0, $r1, $r2 619 ; CHECK-NEXT: {{ $}} 620 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 621 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 622 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r1 623 ; CHECK-NEXT: {{ $}} 624 ; CHECK-NEXT: bb.2.vector.body: 625 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 626 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r2, $r3 627 ; CHECK-NEXT: {{ $}} 628 ; CHECK-NEXT: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg 629 ; CHECK-NEXT: MVE_VPTv4s32r 12, renamable $q1, renamable $r2, 10, implicit-def $vpr 630 ; CHECK-NEXT: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr, $noreg 631 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr, $noreg 632 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 633 ; CHECK-NEXT: {{ $}} 634 ; CHECK-NEXT: bb.3.for.cond.cleanup: 635 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 636 bb.0.entry: 637 successors: %bb.1(0x80000000) 638 liveins: $r0, $r1, $r2, $r7, $lr 639 640 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 641 frame-setup CFI_INSTRUCTION def_cfa_offset 8 642 frame-setup CFI_INSTRUCTION offset $lr, -4 643 frame-setup CFI_INSTRUCTION offset $r7, -8 644 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 645 t2IT 11, 8, implicit-def $itstate 646 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 647 648 bb.1.vector.ph: 649 successors: %bb.2(0x80000000) 650 liveins: $r0, $r1, $r2, $r7, $lr 651 652 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 653 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 654 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 655 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 656 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 657 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 658 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 659 $lr = t2DoLoopStart renamable $lr 660 661 bb.2.vector.body: 662 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 663 liveins: $lr, $q0, $r0, $r1, $r2, $r3 664 665 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg 666 MVE_VPST 8, implicit $vpr 667 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg 668 MVE_VPTv4s32r 14, renamable $q1, renamable $r2, 10, implicit-def $vpr 669 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr, $noreg 670 renamable $vpr = MVE_VCTP32 renamable $r1, 2, killed renamable $vpr, $noreg 671 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr, $noreg 672 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 673 renamable $lr = t2LoopDec killed renamable $lr, 1 674 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 675 tB %bb.3, 14 /* CC::al */, $noreg 676 677 bb.3.for.cond.cleanup: 678 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 679... 680--- 681name: loop_invariant_vpt_operands 682alignment: 2 683exposesReturnsTwice: false 684legalized: false 685regBankSelected: false 686selected: false 687failedISel: false 688tracksRegLiveness: true 689hasWinCFI: false 690registers: [] 691liveins: 692 - { reg: '$r0', virtual-reg: '' } 693 - { reg: '$r1', virtual-reg: '' } 694 - { reg: '$r2', virtual-reg: '' } 695frameInfo: 696 isFrameAddressTaken: false 697 isReturnAddressTaken: false 698 hasStackMap: false 699 hasPatchPoint: false 700 stackSize: 8 701 offsetAdjustment: 0 702 maxAlignment: 4 703 adjustsStack: false 704 hasCalls: false 705 stackProtector: '' 706 maxCallFrameSize: 0 707 cvBytesOfCalleeSavedRegisters: 0 708 hasOpaqueSPAdjustment: false 709 hasVAStart: false 710 hasMustTailInVarArgFunc: false 711 localFrameSize: 0 712 savePoint: '' 713 restorePoint: '' 714fixedStack: [] 715stack: 716 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 717 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 718 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 719 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 720 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 721 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 722callSites: [] 723constants: [] 724machineFunctionInfo: {} 725body: | 726 ; CHECK-LABEL: name: loop_invariant_vpt_operands 727 ; CHECK: bb.0.entry: 728 ; CHECK-NEXT: successors: %bb.1(0x80000000) 729 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 730 ; CHECK-NEXT: {{ $}} 731 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 732 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 733 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 734 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 735 ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 736 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate 737 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 738 ; CHECK-NEXT: {{ $}} 739 ; CHECK-NEXT: bb.1.vector.ph: 740 ; CHECK-NEXT: successors: %bb.2(0x80000000) 741 ; CHECK-NEXT: liveins: $r0, $r1, $r2 742 ; CHECK-NEXT: {{ $}} 743 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 744 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 745 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r1 746 ; CHECK-NEXT: {{ $}} 747 ; CHECK-NEXT: bb.2.vector.body: 748 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 749 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r2, $r3 750 ; CHECK-NEXT: {{ $}} 751 ; CHECK-NEXT: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg 752 ; CHECK-NEXT: MVE_VPTv4s32r 4, renamable $q0, renamable $r2, 11, implicit-def $vpr 753 ; CHECK-NEXT: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg 754 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg 755 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 756 ; CHECK-NEXT: {{ $}} 757 ; CHECK-NEXT: bb.3.for.cond.cleanup: 758 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 759 bb.0.entry: 760 successors: %bb.1(0x80000000) 761 liveins: $r0, $r1, $r2, $r7, $lr 762 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 763 frame-setup CFI_INSTRUCTION def_cfa_offset 8 764 frame-setup CFI_INSTRUCTION offset $lr, -4 765 frame-setup CFI_INSTRUCTION offset $r7, -8 766 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 767 t2IT 11, 8, implicit-def $itstate 768 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 769 770 bb.1.vector.ph: 771 successors: %bb.2(0x80000000) 772 liveins: $r0, $r1, $r2, $r7, $lr 773 774 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 775 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 776 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 777 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 778 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 779 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 780 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 781 $lr = t2DoLoopStart renamable $lr 782 783 bb.2.vector.body: 784 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 785 liveins: $lr, $q0, $r0, $r1, $r2, $r3 786 787 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg 788 MVE_VPST 8, implicit $vpr 789 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg 790 MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 11, implicit-def $vpr 791 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg 792 renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg 793 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg 794 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 795 renamable $lr = t2LoopDec killed renamable $lr, 1 796 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 797 tB %bb.3, 14 /* CC::al */, $noreg 798 799 bb.3.for.cond.cleanup: 800 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 801... 802--- 803name: vctp_before_vpt 804alignment: 2 805exposesReturnsTwice: false 806legalized: false 807regBankSelected: false 808selected: false 809failedISel: false 810tracksRegLiveness: true 811hasWinCFI: false 812registers: [] 813liveins: 814 - { reg: '$r0', virtual-reg: '' } 815 - { reg: '$r1', virtual-reg: '' } 816 - { reg: '$r2', virtual-reg: '' } 817frameInfo: 818 isFrameAddressTaken: false 819 isReturnAddressTaken: false 820 hasStackMap: false 821 hasPatchPoint: false 822 stackSize: 8 823 offsetAdjustment: 0 824 maxAlignment: 4 825 adjustsStack: false 826 hasCalls: false 827 stackProtector: '' 828 maxCallFrameSize: 0 829 cvBytesOfCalleeSavedRegisters: 0 830 hasOpaqueSPAdjustment: false 831 hasVAStart: false 832 hasMustTailInVarArgFunc: false 833 localFrameSize: 0 834 savePoint: '' 835 restorePoint: '' 836fixedStack: [] 837stack: 838 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 839 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 840 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 841 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 842 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 843 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 844callSites: [] 845constants: [] 846machineFunctionInfo: {} 847body: | 848 ; CHECK-LABEL: name: vctp_before_vpt 849 ; CHECK: bb.0.entry: 850 ; CHECK-NEXT: successors: %bb.1(0x80000000) 851 ; CHECK-NEXT: liveins: $lr, $r1, $r2, $r7 852 ; CHECK-NEXT: {{ $}} 853 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 854 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 855 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 856 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 857 ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 858 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate 859 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 860 ; CHECK-NEXT: {{ $}} 861 ; CHECK-NEXT: bb.1.vector.ph: 862 ; CHECK-NEXT: successors: %bb.2(0x80000000) 863 ; CHECK-NEXT: liveins: $r1, $r2 864 ; CHECK-NEXT: {{ $}} 865 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 866 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 867 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r1 868 ; CHECK-NEXT: {{ $}} 869 ; CHECK-NEXT: bb.2.vector.body: 870 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 871 ; CHECK-NEXT: liveins: $lr, $q0, $r2, $r3 872 ; CHECK-NEXT: {{ $}} 873 ; CHECK-NEXT: MVE_VPTv4s32r 8, renamable $q0, renamable $r2, 8, implicit-def $vpr 874 ; CHECK-NEXT: dead renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r3, 12, 1, killed renamable $vpr, $noreg 875 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 876 ; CHECK-NEXT: {{ $}} 877 ; CHECK-NEXT: bb.3.for.cond.cleanup: 878 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 879 bb.0.entry: 880 successors: %bb.1(0x80000000) 881 liveins: $r0, $r1, $r2, $r7, $lr 882 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 883 frame-setup CFI_INSTRUCTION def_cfa_offset 8 884 frame-setup CFI_INSTRUCTION offset $lr, -4 885 frame-setup CFI_INSTRUCTION offset $r7, -8 886 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 887 t2IT 11, 8, implicit-def $itstate 888 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 889 890 bb.1.vector.ph: 891 successors: %bb.2(0x80000000) 892 liveins: $r0, $r1, $r2, $r7, $lr 893 894 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 895 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 896 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 897 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 898 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 899 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 900 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 901 $lr = t2DoLoopStart renamable $lr 902 903 bb.2.vector.body: 904 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 905 liveins: $lr, $q0, $r0, $r1, $r2, $r3 906 907 MVE_VPTv4s32r 8, renamable $q0, renamable $r2, 8, implicit-def $vpr 908 renamable $vpr = MVE_VCMPs32r killed renamable $q0, renamable $r3, 12, 1, killed renamable $vpr, $noreg 909 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg 910 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 911 renamable $lr = t2LoopDec killed renamable $lr, 1 912 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 913 tB %bb.3, 14 /* CC::al */, $noreg 914 915 bb.3.for.cond.cleanup: 916 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 917... 918# This shouldn't be tail-predicated because the VLDR isn't predicated on the VCTP. 919--- 920name: vpt_load_vctp_store 921alignment: 2 922exposesReturnsTwice: false 923legalized: false 924regBankSelected: false 925selected: false 926failedISel: false 927tracksRegLiveness: true 928hasWinCFI: false 929registers: [] 930liveins: 931 - { reg: '$r0', virtual-reg: '' } 932 - { reg: '$r1', virtual-reg: '' } 933 - { reg: '$r2', virtual-reg: '' } 934frameInfo: 935 isFrameAddressTaken: false 936 isReturnAddressTaken: false 937 hasStackMap: false 938 hasPatchPoint: false 939 stackSize: 8 940 offsetAdjustment: 0 941 maxAlignment: 4 942 adjustsStack: false 943 hasCalls: false 944 stackProtector: '' 945 maxCallFrameSize: 0 946 cvBytesOfCalleeSavedRegisters: 0 947 hasOpaqueSPAdjustment: false 948 hasVAStart: false 949 hasMustTailInVarArgFunc: false 950 localFrameSize: 0 951 savePoint: '' 952 restorePoint: '' 953fixedStack: [] 954stack: 955 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 956 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 957 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 958 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 959 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 960 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 961callSites: [] 962constants: [] 963machineFunctionInfo: {} 964body: | 965 ; CHECK-LABEL: name: vpt_load_vctp_store 966 ; CHECK: bb.0.entry: 967 ; CHECK-NEXT: successors: %bb.1(0x80000000) 968 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 969 ; CHECK-NEXT: {{ $}} 970 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 971 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 972 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 973 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 974 ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 975 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate 976 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 977 ; CHECK-NEXT: {{ $}} 978 ; CHECK-NEXT: bb.1.vector.ph: 979 ; CHECK-NEXT: successors: %bb.2(0x80000000) 980 ; CHECK-NEXT: liveins: $r0, $r1, $r2 981 ; CHECK-NEXT: {{ $}} 982 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 983 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 984 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 985 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 986 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 987 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 988 ; CHECK-NEXT: dead renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 989 ; CHECK-NEXT: {{ $}} 990 ; CHECK-NEXT: bb.2.vector.body: 991 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 992 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2 993 ; CHECK-NEXT: {{ $}} 994 ; CHECK-NEXT: MVE_VPTv4s32r 2, killed renamable $q0, renamable $r2, 2, implicit-def $vpr 995 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 renamable $r0, 0, 1, $vpr, $noreg 996 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed $vpr, $noreg 997 ; CHECK-NEXT: MVE_VSTRWU32 renamable $q0, renamable $r0, 0, 1, killed $vpr, $noreg 998 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 999 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 1000 ; CHECK-NEXT: {{ $}} 1001 ; CHECK-NEXT: bb.3.for.cond.cleanup: 1002 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1003 bb.0.entry: 1004 successors: %bb.1(0x80000000) 1005 liveins: $r0, $r1, $r2, $r7, $lr 1006 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1007 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1008 frame-setup CFI_INSTRUCTION offset $lr, -4 1009 frame-setup CFI_INSTRUCTION offset $r7, -8 1010 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 1011 t2IT 11, 8, implicit-def $itstate 1012 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1013 1014 bb.1.vector.ph: 1015 successors: %bb.2(0x80000000) 1016 liveins: $r0, $r1, $r2, $r7, $lr 1017 1018 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 1019 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 1020 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1021 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1022 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1023 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1024 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 1025 $lr = t2DoLoopStart renamable $lr 1026 1027 bb.2.vector.body: 1028 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1029 liveins: $lr, $q0, $r0, $r1, $r2, $r3 1030 1031 MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 2, implicit-def $vpr 1032 renamable $q0 = MVE_VLDRWU32 renamable $r0, 0, 1, $vpr, $noreg 1033 renamable $vpr = MVE_VCTP32 renamable $r1, 1, $vpr, $noreg 1034 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, $vpr, $noreg 1035 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 1036 renamable $lr = t2LoopDec killed renamable $lr, 1 1037 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 1038 tB %bb.3, 14 /* CC::al */, $noreg 1039 1040 bb.3.for.cond.cleanup: 1041 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1042... 1043--- 1044name: emptyblock 1045tracksRegLiveness: true 1046liveins: 1047 - { reg: '$r0', virtual-reg: '' } 1048 - { reg: '$r1', virtual-reg: '' } 1049 - { reg: '$r2', virtual-reg: '' } 1050stack: 1051 - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 1052 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 1053 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1054 - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1055 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1056 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1057 - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1058 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1059 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1060body: | 1061 ; CHECK-LABEL: name: emptyblock 1062 ; CHECK: bb.0: 1063 ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.3(0x30000000) 1064 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 1065 ; CHECK-NEXT: {{ $}} 1066 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1067 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1068 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 1069 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 1070 ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg 1071 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 12 1072 ; CHECK-NEXT: tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 1073 ; CHECK-NEXT: tBcc %bb.3, 11 /* CC::lt */, killed $cpsr 1074 ; CHECK-NEXT: {{ $}} 1075 ; CHECK-NEXT: bb.1: 1076 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1077 ; CHECK-NEXT: liveins: $r0, $r1, $r2 1078 ; CHECK-NEXT: {{ $}} 1079 ; CHECK-NEXT: tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1080 ; CHECK-NEXT: renamable $r2 = t2CSINC $zr, $zr, 0, implicit killed $cpsr 1081 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 1082 ; CHECK-NEXT: renamable $r12 = t2ANDri killed renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg 1083 ; CHECK-NEXT: renamable $r2 = t2RSBri killed renamable $r12, 0, 14 /* CC::al */, $noreg, $noreg 1084 ; CHECK-NEXT: $vpr = VMSR_P0 killed $r2, 14 /* CC::al */, $noreg 1085 ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) 1086 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r0 1087 ; CHECK-NEXT: {{ $}} 1088 ; CHECK-NEXT: bb.2 (align 4): 1089 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1090 ; CHECK-NEXT: liveins: $lr, $q0, $r1 1091 ; CHECK-NEXT: {{ $}} 1092 ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 1093 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 1094 ; CHECK-NEXT: renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4) 1095 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 1096 ; CHECK-NEXT: {{ $}} 1097 ; CHECK-NEXT: bb.3: 1098 ; CHECK-NEXT: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg 1099 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit undef $r0 1100 bb.0: 1101 successors: %bb.1(0x50000000), %bb.3(0x30000000) 1102 liveins: $r0, $r1, $r2, $r7, $lr 1103 1104 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1105 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1106 frame-setup CFI_INSTRUCTION offset $lr, -4 1107 frame-setup CFI_INSTRUCTION offset $r7, -8 1108 $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg 1109 frame-setup CFI_INSTRUCTION def_cfa_offset 12 1110 tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 1111 tBcc %bb.3, 11 /* CC::lt */, killed $cpsr 1112 1113 bb.1: 1114 successors: %bb.2(0x80000000) 1115 liveins: $r0, $r1, $r2 1116 1117 tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1118 renamable $r2 = t2CSINC $zr, $zr, 0, implicit killed $cpsr 1119 renamable $r3, dead $cpsr = tADDi3 renamable $r0, 3, 14 /* CC::al */, $noreg 1120 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 1121 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1122 renamable $r12 = t2ANDri killed renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg 1123 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg 1124 renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1125 renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg 1126 renamable $r2 = t2RSBri killed renamable $r12, 0, 14 /* CC::al */, $noreg, $noreg 1127 $vpr = VMSR_P0 killed $r2, 14 /* CC::al */, $noreg 1128 VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) 1129 renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r0 1130 1131 bb.2 (align 4): 1132 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1133 liveins: $lr, $q0, $r0, $r1 1134 1135 renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 1136 MVE_VPST 8, implicit $vpr 1137 renamable $vpr = MVE_VCTP32 renamable $r0, 1, killed renamable $vpr, $noreg 1138 renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg 1139 MVE_VPST 8, implicit $vpr 1140 renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4) 1141 renamable $lr = t2LoopDec killed renamable $lr, 1 1142 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 1143 tB %bb.3, 14 /* CC::al */, $noreg 1144 1145 bb.3: 1146 $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg 1147 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit undef $r0 1148... 1149--- 1150name: predvcmp 1151alignment: 8 1152tracksRegLiveness: true 1153liveins: 1154 - { reg: '$r0', virtual-reg: '' } 1155 - { reg: '$r1', virtual-reg: '' } 1156 - { reg: '$r2', virtual-reg: '' } 1157stack: 1158 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1159 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1160 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1161 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1162 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1163 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1164constants: 1165 - id: 0 1166 value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>' 1167 alignment: 8 1168 isTargetSpecific: false 1169body: | 1170 ; CHECK-LABEL: name: predvcmp 1171 ; CHECK: bb.0: 1172 ; CHECK-NEXT: successors: %bb.1(0x80000000) 1173 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 1174 ; CHECK-NEXT: {{ $}} 1175 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1176 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1177 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 1178 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 1179 ; CHECK-NEXT: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 1180 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate 1181 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1182 ; CHECK-NEXT: {{ $}} 1183 ; CHECK-NEXT: bb.1: 1184 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1185 ; CHECK-NEXT: liveins: $r0, $r1, $r2 1186 ; CHECK-NEXT: {{ $}} 1187 ; CHECK-NEXT: renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg 1188 ; CHECK-NEXT: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 1189 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8) 1190 ; CHECK-NEXT: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2 1191 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 1192 ; CHECK-NEXT: {{ $}} 1193 ; CHECK-NEXT: bb.2 (align 4): 1194 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1195 ; CHECK-NEXT: liveins: $lr, $q0, $q1, $q2, $r0, $r1 1196 ; CHECK-NEXT: {{ $}} 1197 ; CHECK-NEXT: MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr 1198 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4) 1199 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0 1200 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 1201 ; CHECK-NEXT: {{ $}} 1202 ; CHECK-NEXT: bb.3: 1203 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1204 ; CHECK-NEXT: {{ $}} 1205 ; CHECK-NEXT: bb.4 (align 8): 1206 ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16 1207 bb.0: 1208 successors: %bb.1(0x80000000) 1209 liveins: $r0, $r1, $r2, $r7, $lr 1210 1211 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1212 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1213 frame-setup CFI_INSTRUCTION offset $lr, -4 1214 frame-setup CFI_INSTRUCTION offset $r7, -8 1215 tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 1216 t2IT 11, 8, implicit-def $itstate 1217 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1218 1219 bb.1: 1220 successors: %bb.2(0x80000000) 1221 liveins: $r0, $r1, $r2 1222 1223 renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg 1224 renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1225 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1226 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 1227 renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8) 1228 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1229 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1230 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1231 renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2 1232 renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r2 1233 1234 bb.2 (align 4): 1235 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1236 liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2 1237 1238 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 1239 MVE_VPST 4, implicit $vpr 1240 renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r1, 11, 1, killed renamable $vpr, $noreg 1241 renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4) 1242 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1243 renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0 1244 renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def dead $cpsr 1245 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1246 tB %bb.3, 14 /* CC::al */, $noreg 1247 1248 bb.3: 1249 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1250 1251 bb.4 (align 8): 1252 CONSTPOOL_ENTRY 0, %const.0, 16 1253 1254... 1255--- 1256name: predvpt 1257alignment: 8 1258tracksRegLiveness: true 1259liveins: 1260 - { reg: '$r0', virtual-reg: '' } 1261 - { reg: '$r1', virtual-reg: '' } 1262 - { reg: '$r2', virtual-reg: '' } 1263stack: 1264 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1265 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1266 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1267 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1268 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1269 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1270constants: 1271 - id: 0 1272 value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>' 1273 alignment: 8 1274 isTargetSpecific: false 1275body: | 1276 ; CHECK-LABEL: name: predvpt 1277 ; CHECK: bb.0: 1278 ; CHECK-NEXT: successors: %bb.1(0x80000000) 1279 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 1280 ; CHECK-NEXT: {{ $}} 1281 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1282 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1283 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 1284 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 1285 ; CHECK-NEXT: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 1286 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate 1287 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1288 ; CHECK-NEXT: {{ $}} 1289 ; CHECK-NEXT: bb.1: 1290 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1291 ; CHECK-NEXT: liveins: $r0, $r1, $r2 1292 ; CHECK-NEXT: {{ $}} 1293 ; CHECK-NEXT: renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg 1294 ; CHECK-NEXT: renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1295 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1296 ; CHECK-NEXT: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 1297 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8) 1298 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1299 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1300 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1301 ; CHECK-NEXT: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2 1302 ; CHECK-NEXT: {{ $}} 1303 ; CHECK-NEXT: bb.2 (align 4): 1304 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1305 ; CHECK-NEXT: liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2 1306 ; CHECK-NEXT: {{ $}} 1307 ; CHECK-NEXT: MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr 1308 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed $vpr, $noreg 1309 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 1310 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4) 1311 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1312 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0 1313 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 1314 ; CHECK-NEXT: {{ $}} 1315 ; CHECK-NEXT: bb.3: 1316 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1317 ; CHECK-NEXT: {{ $}} 1318 ; CHECK-NEXT: bb.4 (align 8): 1319 ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16 1320 bb.0: 1321 successors: %bb.1(0x80000000) 1322 liveins: $r0, $r1, $r2, $r7, $lr 1323 1324 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1325 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1326 frame-setup CFI_INSTRUCTION offset $lr, -4 1327 frame-setup CFI_INSTRUCTION offset $r7, -8 1328 tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 1329 t2IT 11, 8, implicit-def $itstate 1330 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1331 1332 bb.1: 1333 successors: %bb.2(0x80000000) 1334 liveins: $r0, $r1, $r2 1335 1336 renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg 1337 renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1338 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1339 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 1340 renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8) 1341 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1342 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1343 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1344 renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2 1345 renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r2 1346 1347 bb.2 (align 4): 1348 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1349 liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2 1350 1351 MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr 1352 renamable $vpr = MVE_VCTP32 renamable $r2, 1, $vpr, $noreg 1353 MVE_VPST 8, implicit $vpr 1354 renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4) 1355 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1356 renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0 1357 renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def dead $cpsr 1358 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1359 tB %bb.3, 14 /* CC::al */, $noreg 1360 1361 bb.3: 1362 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1363 1364 bb.4 (align 8): 1365 CONSTPOOL_ENTRY 0, %const.0, 16 1366... 1367