1 2; RUN: opt -mtriple=thumbv8.1m.main -mve-tail-predication -tail-predication=enabled -mattr=+mve %s -S -o - | FileCheck %s 3 4; CHECK-LABEL: vec_mul_reduce_add 5 6; CHECK: vector.ph: 7; CHECK: %start = call i32 @llvm.start.loop.iterations.i32 8; CHECK: br label %vector.body 9 10; CHECK: vector.body: 11; CHECK: [[ELTS:%[^ ]+]] = phi i32 [ %N, %vector.ph ], [ [[SUB:%[^ ]+]], %vector.body ] 12; CHECK: [[VCTP:%[^ ]+]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 [[ELTS]]) 13; CHECK: [[SUB]] = sub i32 [[ELTS]], 4 14; CHECK: call <4 x i32> @llvm.masked.load.v4i32.p0(ptr {{.*}}, i32 4, <4 x i1> [[VCTP]] 15; CHECK: call <4 x i32> @llvm.masked.load.v4i32.p0(ptr {{.*}}, i32 4, <4 x i1> [[VCTP]], 16 17; CHECK: middle.block: 18; CHECK: [[VPSEL:%[^ ]+]] = select <4 x i1> [[VCTP]], 19; CHECK: call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[VPSEL]]) 20 21define i32 @vec_mul_reduce_add(ptr noalias nocapture readonly %a, ptr noalias nocapture readonly %b, i32 %N) { 22entry: 23 %cmp8 = icmp eq i32 %N, 0 24 %0 = add i32 %N, 3 25 %1 = lshr i32 %0, 2 26 %2 = shl nuw i32 %1, 2 27 %3 = add i32 %2, -4 28 %4 = lshr i32 %3, 2 29 %5 = add nuw nsw i32 %4, 1 30 br i1 %cmp8, label %for.cond.cleanup, label %vector.ph 31 32vector.ph: ; preds = %entry 33 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 34 br label %vector.body 35 36vector.body: ; preds = %vector.body, %vector.ph 37 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] 38 %lsr.iv2 = phi ptr [ %scevgep3, %vector.body ], [ %a, %vector.ph ] 39 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %b, %vector.ph ] 40 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %9, %vector.body ] 41 %6 = phi i32 [ %start, %vector.ph ], [ %10, %vector.body ] 42 %7 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N) 43 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv2, i32 4, <4 x i1> %7, <4 x i32> undef) 44 %wide.masked.load13 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv, i32 4, <4 x i1> %7, <4 x i32> undef) 45 %8 = mul nsw <4 x i32> %wide.masked.load13, %wide.masked.load 46 %9 = add nsw <4 x i32> %8, %vec.phi 47 %index.next = add i32 %index, 4 48 %scevgep = getelementptr i32, ptr %lsr.iv, i32 4 49 %scevgep3 = getelementptr i32, ptr %lsr.iv2, i32 4 50 %10 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1) 51 %11 = icmp ne i32 %10, 0 52 br i1 %11, label %vector.body, label %middle.block 53 54middle.block: ; preds = %vector.body 55 %12 = select <4 x i1> %7, <4 x i32> %9, <4 x i32> %vec.phi 56 %13 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %12) 57 br label %for.cond.cleanup 58 59for.cond.cleanup: ; preds = %middle.block, %entry 60 %res.0.lcssa = phi i32 [ 0, %entry ], [ %13, %middle.block ] 61 ret i32 %res.0.lcssa 62} 63 64declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) 65declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) 66declare i32 @llvm.start.loop.iterations.i32(i32) 67declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 68declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) 69