1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve,+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 define dso_local void @vctp_tsubi3(ptr noalias nocapture %A, ptr noalias nocapture readonly %B, ptr noalias nocapture readonly %C, i32 %N) local_unnamed_addr #0 { 6 entry: 7 %cmp8 = icmp sgt i32 %N, 0 8 %0 = add i32 %N, 3 9 %1 = lshr i32 %0, 2 10 %2 = shl nuw i32 %1, 2 11 %3 = add i32 %2, -4 12 %4 = lshr i32 %3, 2 13 %5 = add nuw nsw i32 %4, 1 14 br i1 %cmp8, label %vector.ph, label %for.cond.cleanup 15 16 vector.ph: ; preds = %entry 17 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 18 br label %vector.body 19 20 vector.body: ; preds = %vector.body, %vector.ph 21 %lsr.iv17 = phi ptr [ %scevgep18, %vector.body ], [ %A, %vector.ph ] 22 %lsr.iv14 = phi ptr [ %scevgep15, %vector.body ], [ %C, %vector.ph ] 23 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %B, %vector.ph ] 24 %6 = phi i32 [ %start, %vector.ph ], [ %11, %vector.body ] 25 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ] 26 %lsr.iv13 = bitcast ptr %lsr.iv to ptr 27 %lsr.iv1416 = bitcast ptr %lsr.iv14 to ptr 28 %lsr.iv1719 = bitcast ptr %lsr.iv17 to ptr 29 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7) 30 %9 = sub i32 %7, 5 31 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv13, i32 4, <4 x i1> %8, <4 x i32> undef) 32 %wide.masked.load12 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv1416, i32 4, <4 x i1> %8, <4 x i32> undef) 33 %10 = add nsw <4 x i32> %wide.masked.load12, %wide.masked.load 34 call void @llvm.masked.store.v4i32.p0(<4 x i32> %10, ptr %lsr.iv1719, i32 4, <4 x i1> %8) 35 %scevgep = getelementptr i32, ptr %lsr.iv, i32 4 36 %scevgep15 = getelementptr i32, ptr %lsr.iv14, i32 4 37 %scevgep18 = getelementptr i32, ptr %lsr.iv17, i32 4 38 %11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1) 39 %12 = icmp ne i32 %11, 0 40 br i1 %12, label %vector.body, label %for.cond.cleanup 41 42 for.cond.cleanup: ; preds = %vector.body, %entry 43 ret void 44 } 45 declare i32 @llvm.start.loop.iterations.i32(i32) 46 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 47 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 48 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) 49 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>) 50 51... 52--- 53name: vctp_tsubi3 54alignment: 2 55exposesReturnsTwice: false 56legalized: false 57regBankSelected: false 58selected: false 59failedISel: false 60tracksRegLiveness: true 61hasWinCFI: false 62registers: [] 63liveins: 64 - { reg: '$r0', virtual-reg: '' } 65 - { reg: '$r1', virtual-reg: '' } 66 - { reg: '$r2', virtual-reg: '' } 67 - { reg: '$r3', virtual-reg: '' } 68frameInfo: 69 isFrameAddressTaken: false 70 isReturnAddressTaken: false 71 hasStackMap: false 72 hasPatchPoint: false 73 stackSize: 8 74 offsetAdjustment: 0 75 maxAlignment: 4 76 adjustsStack: false 77 hasCalls: false 78 stackProtector: '' 79 maxCallFrameSize: 0 80 cvBytesOfCalleeSavedRegisters: 0 81 hasOpaqueSPAdjustment: false 82 hasVAStart: false 83 hasMustTailInVarArgFunc: false 84 localFrameSize: 0 85 savePoint: '' 86 restorePoint: '' 87fixedStack: [] 88stack: 89 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 90 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 91 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 92 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 93 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 94 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 95callSites: [] 96constants: [] 97machineFunctionInfo: {} 98body: | 99 ; CHECK-LABEL: name: vctp_tsubi3 100 ; CHECK: bb.0.entry: 101 ; CHECK-NEXT: successors: %bb.1(0x80000000) 102 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 103 ; CHECK-NEXT: {{ $}} 104 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 105 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 106 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 107 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 108 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 109 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate 110 ; CHECK-NEXT: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 111 ; CHECK-NEXT: {{ $}} 112 ; CHECK-NEXT: bb.1.vector.ph: 113 ; CHECK-NEXT: successors: %bb.2(0x80000000) 114 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 115 ; CHECK-NEXT: {{ $}} 116 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3 117 ; CHECK-NEXT: {{ $}} 118 ; CHECK-NEXT: bb.2.vector.body: 119 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 120 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 121 ; CHECK-NEXT: {{ $}} 122 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) 123 ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) 124 ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 125 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) 126 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 127 ; CHECK-NEXT: {{ $}} 128 ; CHECK-NEXT: bb.3.for.cond.cleanup: 129 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 130 bb.0.entry: 131 successors: %bb.1(0x80000000) 132 liveins: $r0, $r1, $r2, $r3, $r7, $lr 133 134 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 135 frame-setup CFI_INSTRUCTION def_cfa_offset 8 136 frame-setup CFI_INSTRUCTION offset $lr, -4 137 frame-setup CFI_INSTRUCTION offset $r7, -8 138 tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr 139 t2IT 11, 8, implicit-def $itstate 140 tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate 141 142 bb.1.vector.ph: 143 successors: %bb.2(0x80000000) 144 liveins: $r0, $r1, $r2, $r3, $r7, $lr 145 146 renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg 147 renamable $lr = t2MOVi 1, 14, $noreg, $noreg 148 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg 149 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg 150 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg 151 $lr = t2DoLoopStart renamable $lr 152 153 bb.2.vector.body: 154 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 155 liveins: $lr, $r0, $r1, $r2, $r3 156 157 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg 158 MVE_VPST 4, implicit $vpr 159 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) 160 renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) 161 renamable $r3 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg 162 renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 163 MVE_VPST 8, implicit $vpr 164 renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) 165 renamable $lr = t2LoopDec killed renamable $lr, 1 166 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 167 tB %bb.3, 14, $noreg 168 169 bb.3.for.cond.cleanup: 170 tPOP_RET 14, $noreg, def $r7, def $pc 171 172... 173