1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s 3--- | 4 define dso_local void @test_vldr_p0(ptr noalias nocapture %arg, ptr noalias nocapture readonly %arg1, i32 %arg2, i16 zeroext %mask) local_unnamed_addr #0 { 5 bb: 6 %tmp = icmp eq i32 %arg2, 0 7 %tmp1 = add i32 %arg2, 3 8 %tmp2 = lshr i32 %tmp1, 2 9 %tmp3 = shl nuw i32 %tmp2, 2 10 %tmp4 = add i32 %tmp3, -4 11 %tmp5 = lshr i32 %tmp4, 2 12 %tmp6 = add nuw nsw i32 %tmp5, 1 13 %conv.mask = zext i16 %mask to i32 14 %invariant.mask = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %conv.mask) 15 br i1 %tmp, label %bb27, label %bb3 16 17 bb3: ; preds = %bb 18 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp6) 19 br label %bb9 20 21 bb9: ; preds = %bb9, %bb3 22 %lsr.iv2 = phi ptr [ %scevgep3, %bb9 ], [ %arg1, %bb3 ] 23 %lsr.iv = phi ptr [ %scevgep, %bb9 ], [ %arg, %bb3 ] 24 %tmp7 = phi i32 [ %start, %bb3 ], [ %tmp12, %bb9 ] 25 %tmp8 = phi i32 [ %arg2, %bb3 ], [ %tmp11, %bb9 ] 26 %lsr.iv24 = bitcast ptr %lsr.iv2 to ptr 27 %lsr.iv1 = bitcast ptr %lsr.iv to ptr 28 %vctp = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp8) 29 %and = and <4 x i1> %vctp, %invariant.mask 30 %tmp11 = sub i32 %tmp8, 4 31 %tmp17 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv24, i32 4, <4 x i1> %and, <4 x i32> undef) 32 %tmp22 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv1, i32 4, <4 x i1> %and, <4 x i32> undef) 33 %tmp23 = mul nsw <4 x i32> %tmp22, %tmp17 34 call void @llvm.masked.store.v4i32.p0(<4 x i32> %tmp23, ptr %lsr.iv1, i32 4, <4 x i1> %and) 35 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp7, i32 1) 36 %tmp13 = icmp ne i32 %tmp12, 0 37 %scevgep = getelementptr i32, ptr %lsr.iv, i32 4 38 %scevgep3 = getelementptr i32, ptr %lsr.iv2, i32 4 39 br i1 %tmp13, label %bb9, label %bb27 40 41 bb27: ; preds = %bb9, %bb 42 ret void 43 } 44 45 define dso_local void @test_vstr_p0(ptr noalias nocapture %arg, ptr noalias nocapture readonly %arg1, i32 %arg2, i16 zeroext %mask) { 46 bb: 47 unreachable 48 bb3: ; preds = %bb 49 unreachable 50 bb9: ; preds = %bb9, %bb3 51 unreachable 52 bb27: ; preds = %bb9, %bb 53 ret void 54 } 55 56 define dso_local void @test_vmsr_p0(ptr noalias nocapture %arg, ptr noalias nocapture readonly %arg1, i32 %arg2, i16 zeroext %mask) { 57 bb: 58 unreachable 59 bb3: ; preds = %bb 60 unreachable 61 bb9: ; preds = %bb9, %bb3 62 unreachable 63 bb27: ; preds = %bb9, %bb 64 ret void 65 } 66 67 define dso_local void @test_vmrs_p0(ptr noalias nocapture %arg, ptr noalias nocapture readonly %arg1, i32 %arg2, i16 zeroext %mask) { 68 bb: 69 unreachable 70 bb3: ; preds = %bb 71 unreachable 72 bb9: ; preds = %bb9, %bb3 73 unreachable 74 bb27: ; preds = %bb9, %bb 75 ret void 76 } 77 78 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) #1 79 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>) #2 80 declare i32 @llvm.start.loop.iterations.i32(i32) #3 81 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3 82 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4 83 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #4 84 85... 86--- 87name: test_vldr_p0 88alignment: 2 89exposesReturnsTwice: false 90legalized: false 91regBankSelected: false 92selected: false 93failedISel: false 94tracksRegLiveness: true 95hasWinCFI: false 96registers: [] 97liveins: 98 - { reg: '$r0', virtual-reg: '' } 99 - { reg: '$r1', virtual-reg: '' } 100 - { reg: '$r2', virtual-reg: '' } 101 - { reg: '$r3', virtual-reg: '' } 102frameInfo: 103 isFrameAddressTaken: false 104 isReturnAddressTaken: false 105 hasStackMap: false 106 hasPatchPoint: false 107 stackSize: 12 108 offsetAdjustment: -4 109 maxAlignment: 4 110 adjustsStack: false 111 hasCalls: false 112 stackProtector: '' 113 maxCallFrameSize: 0 114 cvBytesOfCalleeSavedRegisters: 0 115 hasOpaqueSPAdjustment: false 116 hasVAStart: false 117 hasMustTailInVarArgFunc: false 118 localFrameSize: 0 119 savePoint: '' 120 restorePoint: '' 121fixedStack: [] 122stack: 123 - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 124 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 125 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 126 - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 127 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 128 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 129 - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 130 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 131 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 132callSites: [] 133constants: [] 134machineFunctionInfo: {} 135body: | 136 ; CHECK-LABEL: name: test_vldr_p0 137 ; CHECK: bb.0.bb: 138 ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) 139 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 140 ; CHECK-NEXT: {{ $}} 141 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 142 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 143 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 144 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 145 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 146 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 147 ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg 148 ; CHECK-NEXT: tCBZ $r2, %bb.3 149 ; CHECK-NEXT: {{ $}} 150 ; CHECK-NEXT: bb.1.bb3: 151 ; CHECK-NEXT: successors: %bb.2(0x80000000) 152 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 153 ; CHECK-NEXT: {{ $}} 154 ; CHECK-NEXT: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg 155 ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) 156 ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg 157 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 158 ; CHECK-NEXT: {{ $}} 159 ; CHECK-NEXT: bb.2.bb9: 160 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 161 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r3 162 ; CHECK-NEXT: {{ $}} 163 ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 164 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr 165 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4) 166 ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4) 167 ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 168 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 169 ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4) 170 ; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg 171 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 172 ; CHECK-NEXT: {{ $}} 173 ; CHECK-NEXT: bb.3.bb27: 174 ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg 175 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 176 bb.0.bb: 177 successors: %bb.3(0x30000000), %bb.1(0x50000000) 178 liveins: $r0, $r1, $r2, $r3, $lr 179 180 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp 181 frame-setup CFI_INSTRUCTION def_cfa_offset 8 182 frame-setup CFI_INSTRUCTION offset $lr, -4 183 frame-setup CFI_INSTRUCTION offset $r7, -8 184 $r7 = frame-setup tMOVr $sp, 14, $noreg 185 frame-setup CFI_INSTRUCTION def_cfa_register $r7 186 $sp = frame-setup tSUBspi $sp, 1, 14, $noreg 187 tCBZ $r2, %bb.3 188 189 bb.1.bb3: 190 successors: %bb.2(0x80000000) 191 liveins: $r0, $r1, $r2, $r3 192 193 renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg 194 renamable $lr = t2MOVi 1, 14, $noreg, $noreg 195 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg 196 $vpr = VMSR_P0 killed $r3, 14, $noreg 197 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg 198 VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store (s32) into %stack.0) 199 $r3 = tMOVr $r0, 14, $noreg 200 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg 201 $lr = t2DoLoopStart renamable $lr 202 203 bb.2.bb9: 204 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 205 liveins: $lr, $r0, $r1, $r2, $r3 206 207 renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0) 208 MVE_VPST 2, implicit $vpr 209 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg 210 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4) 211 renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4) 212 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg 213 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 214 MVE_VPST 8, implicit $vpr 215 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4) 216 renamable $lr = t2LoopDec killed renamable $lr, 1 217 $r0 = tMOVr $r3, 14, $noreg 218 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 219 tB %bb.3, 14, $noreg 220 221 bb.3.bb27: 222 $sp = tADDspi $sp, 1, 14, $noreg 223 tPOP_RET 14, $noreg, def $r7, def $pc 224 225... 226--- 227name: test_vstr_p0 228alignment: 2 229exposesReturnsTwice: false 230legalized: false 231regBankSelected: false 232selected: false 233failedISel: false 234tracksRegLiveness: true 235hasWinCFI: false 236registers: [] 237liveins: 238 - { reg: '$r0', virtual-reg: '' } 239 - { reg: '$r1', virtual-reg: '' } 240 - { reg: '$r2', virtual-reg: '' } 241 - { reg: '$r3', virtual-reg: '' } 242frameInfo: 243 isFrameAddressTaken: false 244 isReturnAddressTaken: false 245 hasStackMap: false 246 hasPatchPoint: false 247 stackSize: 12 248 offsetAdjustment: -4 249 maxAlignment: 4 250 adjustsStack: false 251 hasCalls: false 252 stackProtector: '' 253 maxCallFrameSize: 0 254 cvBytesOfCalleeSavedRegisters: 0 255 hasOpaqueSPAdjustment: false 256 hasVAStart: false 257 hasMustTailInVarArgFunc: false 258 localFrameSize: 0 259 savePoint: '' 260 restorePoint: '' 261fixedStack: [] 262stack: 263 - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 264 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 265 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 266 - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 267 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 268 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 269 - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 270 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 271 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 272callSites: [] 273constants: [] 274machineFunctionInfo: {} 275body: | 276 ; CHECK-LABEL: name: test_vstr_p0 277 ; CHECK: bb.0.bb: 278 ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) 279 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 280 ; CHECK-NEXT: {{ $}} 281 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 282 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 283 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 284 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 285 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 286 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 287 ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg 288 ; CHECK-NEXT: tCBZ $r2, %bb.3 289 ; CHECK-NEXT: {{ $}} 290 ; CHECK-NEXT: bb.1.bb3: 291 ; CHECK-NEXT: successors: %bb.2(0x80000000) 292 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 293 ; CHECK-NEXT: {{ $}} 294 ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 295 ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg 296 ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg 297 ; CHECK-NEXT: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg 298 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg 299 ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) 300 ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg 301 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 302 ; CHECK-NEXT: {{ $}} 303 ; CHECK-NEXT: bb.2.bb9: 304 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 305 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 306 ; CHECK-NEXT: {{ $}} 307 ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 308 ; CHECK-NEXT: MVE_VPST 2, implicit $vpr 309 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg 310 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg 311 ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg 312 ; CHECK-NEXT: VSTR_P0_off renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) 313 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 314 ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 315 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 316 ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg 317 ; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg 318 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 319 ; CHECK-NEXT: {{ $}} 320 ; CHECK-NEXT: bb.3.bb27: 321 ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg 322 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 323 bb.0.bb: 324 successors: %bb.3(0x30000000), %bb.1(0x50000000) 325 liveins: $r0, $r1, $r2, $r3, $lr 326 327 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp 328 frame-setup CFI_INSTRUCTION def_cfa_offset 8 329 frame-setup CFI_INSTRUCTION offset $lr, -4 330 frame-setup CFI_INSTRUCTION offset $r7, -8 331 $r7 = frame-setup tMOVr $sp, 14, $noreg 332 frame-setup CFI_INSTRUCTION def_cfa_register $r7 333 $sp = frame-setup tSUBspi $sp, 1, 14, $noreg 334 tCBZ $r2, %bb.3 335 336 bb.1.bb3: 337 successors: %bb.2(0x80000000) 338 liveins: $r0, $r1, $r2, $r3 339 340 renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg 341 renamable $lr = t2MOVi 1, 14, $noreg, $noreg 342 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg 343 $vpr = VMSR_P0 killed $r3, 14, $noreg 344 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg 345 VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store (s32) into %stack.0) 346 $r3 = tMOVr $r0, 14, $noreg 347 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg 348 $lr = t2DoLoopStart renamable $lr 349 350 bb.2.bb9: 351 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 352 liveins: $lr, $r0, $r1, $r2, $r3 353 354 renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0) 355 MVE_VPST 2, implicit $vpr 356 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg 357 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg 358 renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg 359 VSTR_P0_off renamable $vpr, $sp, 0, 14, $noreg :: (store (s32) into %stack.0) 360 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg 361 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 362 MVE_VPST 8, implicit $vpr 363 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg 364 renamable $lr = t2LoopDec killed renamable $lr, 1 365 $r0 = tMOVr $r3, 14, $noreg 366 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 367 tB %bb.3, 14, $noreg 368 369 bb.3.bb27: 370 $sp = tADDspi $sp, 1, 14, $noreg 371 tPOP_RET 14, $noreg, def $r7, def $pc 372 373... 374--- 375name: test_vmsr_p0 376alignment: 2 377exposesReturnsTwice: false 378legalized: false 379regBankSelected: false 380selected: false 381failedISel: false 382tracksRegLiveness: true 383hasWinCFI: false 384registers: [] 385liveins: 386 - { reg: '$r0', virtual-reg: '' } 387 - { reg: '$r1', virtual-reg: '' } 388 - { reg: '$r2', virtual-reg: '' } 389 - { reg: '$r3', virtual-reg: '' } 390frameInfo: 391 isFrameAddressTaken: false 392 isReturnAddressTaken: false 393 hasStackMap: false 394 hasPatchPoint: false 395 stackSize: 12 396 offsetAdjustment: -4 397 maxAlignment: 4 398 adjustsStack: false 399 hasCalls: false 400 stackProtector: '' 401 maxCallFrameSize: 0 402 cvBytesOfCalleeSavedRegisters: 0 403 hasOpaqueSPAdjustment: false 404 hasVAStart: false 405 hasMustTailInVarArgFunc: false 406 localFrameSize: 0 407 savePoint: '' 408 restorePoint: '' 409fixedStack: [] 410stack: 411 - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 412 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 413 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 414 - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 415 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 416 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 417 - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 418 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 419 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 420callSites: [] 421constants: [] 422machineFunctionInfo: {} 423body: | 424 ; CHECK-LABEL: name: test_vmsr_p0 425 ; CHECK: bb.0.bb: 426 ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) 427 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 428 ; CHECK-NEXT: {{ $}} 429 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 430 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 431 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 432 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 433 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 434 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 435 ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg 436 ; CHECK-NEXT: tCBZ $r2, %bb.3 437 ; CHECK-NEXT: {{ $}} 438 ; CHECK-NEXT: bb.1.bb3: 439 ; CHECK-NEXT: successors: %bb.2(0x80000000) 440 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 441 ; CHECK-NEXT: {{ $}} 442 ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 443 ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg 444 ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg 445 ; CHECK-NEXT: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg 446 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg 447 ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) 448 ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg 449 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 450 ; CHECK-NEXT: {{ $}} 451 ; CHECK-NEXT: bb.2.bb9: 452 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 453 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 454 ; CHECK-NEXT: {{ $}} 455 ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 456 ; CHECK-NEXT: MVE_VPST 2, implicit $vpr 457 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg 458 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg 459 ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr, $noreg 460 ; CHECK-NEXT: $vpr = VMSR_P0 $r3, 14 /* CC::al */, $noreg 461 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 462 ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 463 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 464 ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg 465 ; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg 466 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 467 ; CHECK-NEXT: {{ $}} 468 ; CHECK-NEXT: bb.3.bb27: 469 ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg 470 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 471 bb.0.bb: 472 successors: %bb.3(0x30000000), %bb.1(0x50000000) 473 liveins: $r0, $r1, $r2, $r3, $lr 474 475 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp 476 frame-setup CFI_INSTRUCTION def_cfa_offset 8 477 frame-setup CFI_INSTRUCTION offset $lr, -4 478 frame-setup CFI_INSTRUCTION offset $r7, -8 479 $r7 = frame-setup tMOVr $sp, 14, $noreg 480 frame-setup CFI_INSTRUCTION def_cfa_register $r7 481 $sp = frame-setup tSUBspi $sp, 1, 14, $noreg 482 tCBZ $r2, %bb.3 483 484 bb.1.bb3: 485 successors: %bb.2(0x80000000) 486 liveins: $r0, $r1, $r2, $r3 487 488 renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg 489 renamable $lr = t2MOVi 1, 14, $noreg, $noreg 490 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg 491 $vpr = VMSR_P0 killed $r3, 14, $noreg 492 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg 493 VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store (s32) into %stack.0) 494 $r3 = tMOVr $r0, 14, $noreg 495 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg 496 $lr = t2DoLoopStart renamable $lr 497 498 bb.2.bb9: 499 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 500 liveins: $lr, $r0, $r1, $r2, $r3 501 502 renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0) 503 MVE_VPST 2, implicit $vpr 504 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg 505 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg 506 renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg 507 $vpr = VMSR_P0 $r3, 14, $noreg 508 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg 509 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 510 MVE_VPST 8, implicit $vpr 511 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg 512 renamable $lr = t2LoopDec killed renamable $lr, 1 513 $r0 = tMOVr $r3, 14, $noreg 514 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 515 tB %bb.3, 14, $noreg 516 517 bb.3.bb27: 518 $sp = tADDspi $sp, 1, 14, $noreg 519 tPOP_RET 14, $noreg, def $r7, def $pc 520 521... 522--- 523name: test_vmrs_p0 524alignment: 2 525exposesReturnsTwice: false 526legalized: false 527regBankSelected: false 528selected: false 529failedISel: false 530tracksRegLiveness: true 531hasWinCFI: false 532registers: [] 533liveins: 534 - { reg: '$r0', virtual-reg: '' } 535 - { reg: '$r1', virtual-reg: '' } 536 - { reg: '$r2', virtual-reg: '' } 537 - { reg: '$r3', virtual-reg: '' } 538frameInfo: 539 isFrameAddressTaken: false 540 isReturnAddressTaken: false 541 hasStackMap: false 542 hasPatchPoint: false 543 stackSize: 12 544 offsetAdjustment: -4 545 maxAlignment: 4 546 adjustsStack: false 547 hasCalls: false 548 stackProtector: '' 549 maxCallFrameSize: 0 550 cvBytesOfCalleeSavedRegisters: 0 551 hasOpaqueSPAdjustment: false 552 hasVAStart: false 553 hasMustTailInVarArgFunc: false 554 localFrameSize: 0 555 savePoint: '' 556 restorePoint: '' 557fixedStack: [] 558stack: 559 - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 560 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 561 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 562 - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 563 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 564 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 565 - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 566 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 567 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 568callSites: [] 569constants: [] 570machineFunctionInfo: {} 571body: | 572 ; CHECK-LABEL: name: test_vmrs_p0 573 ; CHECK: bb.0.bb: 574 ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) 575 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 576 ; CHECK-NEXT: {{ $}} 577 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 578 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 579 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 580 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 581 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 582 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 583 ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg 584 ; CHECK-NEXT: tCBZ $r2, %bb.3 585 ; CHECK-NEXT: {{ $}} 586 ; CHECK-NEXT: bb.1.bb3: 587 ; CHECK-NEXT: successors: %bb.2(0x80000000) 588 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 589 ; CHECK-NEXT: {{ $}} 590 ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 591 ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg 592 ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg 593 ; CHECK-NEXT: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg 594 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg 595 ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) 596 ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg 597 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 598 ; CHECK-NEXT: {{ $}} 599 ; CHECK-NEXT: bb.2.bb9: 600 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 601 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 602 ; CHECK-NEXT: {{ $}} 603 ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 604 ; CHECK-NEXT: MVE_VPST 2, implicit $vpr 605 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg 606 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg 607 ; CHECK-NEXT: dead renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg 608 ; CHECK-NEXT: $r3 = VMRS_P0 $vpr, 14 /* CC::al */, $noreg 609 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 610 ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 611 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 612 ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg 613 ; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg 614 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 615 ; CHECK-NEXT: {{ $}} 616 ; CHECK-NEXT: bb.3.bb27: 617 ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg 618 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 619 bb.0.bb: 620 successors: %bb.3(0x30000000), %bb.1(0x50000000) 621 liveins: $r0, $r1, $r2, $r3, $lr 622 623 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp 624 frame-setup CFI_INSTRUCTION def_cfa_offset 8 625 frame-setup CFI_INSTRUCTION offset $lr, -4 626 frame-setup CFI_INSTRUCTION offset $r7, -8 627 $r7 = frame-setup tMOVr $sp, 14, $noreg 628 frame-setup CFI_INSTRUCTION def_cfa_register $r7 629 $sp = frame-setup tSUBspi $sp, 1, 14, $noreg 630 tCBZ $r2, %bb.3 631 632 bb.1.bb3: 633 successors: %bb.2(0x80000000) 634 liveins: $r0, $r1, $r2, $r3 635 636 renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg 637 renamable $lr = t2MOVi 1, 14, $noreg, $noreg 638 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg 639 $vpr = VMSR_P0 killed $r3, 14, $noreg 640 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg 641 VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store (s32) into %stack.0) 642 $r3 = tMOVr $r0, 14, $noreg 643 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg 644 $lr = t2DoLoopStart renamable $lr 645 646 bb.2.bb9: 647 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 648 liveins: $lr, $r0, $r1, $r2, $r3 649 650 renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0) 651 MVE_VPST 2, implicit $vpr 652 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg 653 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg 654 renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg 655 $r3 = VMRS_P0 $vpr, 14, $noreg 656 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg 657 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 658 MVE_VPST 8, implicit $vpr 659 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg 660 renamable $lr = t2LoopDec killed renamable $lr, 1 661 $r0 = tMOVr $r3, 14, $noreg 662 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 663 tB %bb.3, 14, $noreg 664 665 bb.3.bb27: 666 $sp = tADDspi $sp, 1, 14, $noreg 667 tPOP_RET 14, $noreg, def $r7, def $pc 668 669... 670