xref: /llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir (revision 59c6bd156cc8b42758ce90909615748e21c6eee2) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
3
4# This example is actually equivalent as there's a sub in the loop, which is
5# then used by the add in the exit - making the vctp operands equivalent.
6
7--- |
8  define dso_local i32 @wrong_vctp_liveout(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
9  entry:
10    %cmp9 = icmp eq i32 %N, 0
11    %0 = add i32 %N, 3
12    %1 = lshr i32 %0, 2
13    %2 = shl nuw i32 %1, 2
14    %3 = add i32 %2, -4
15    %4 = lshr i32 %3, 2
16    %5 = add nuw nsw i32 %4, 1
17    br i1 %cmp9, label %for.cond.cleanup, label %vector.ph
18
19  vector.ph:                                        ; preds = %entry
20    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
21    br label %vector.body
22
23  vector.body:                                      ; preds = %vector.body, %vector.ph
24    %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]
25    %lsr.iv18 = phi ptr [ %scevgep19, %vector.body ], [ %b, %vector.ph ]
26    %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]
27    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]
28    %6 = phi i32 [ %N, %vector.ph ], [ %8, %vector.body ]
29    %lsr.iv17 = bitcast ptr %lsr.iv to ptr
30    %lsr.iv1820 = bitcast ptr %lsr.iv18 to ptr
31    %7 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %6)
32    %8 = sub i32 %6, 4
33    %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %7, <4 x i16> undef)
34    %9 = sext <4 x i16> %wide.masked.load to <4 x i32>
35    %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1820, i32 2, <4 x i1> %7, <4 x i16> undef)
36    %10 = sext <4 x i16> %wide.masked.load14 to <4 x i32>
37    %11 = mul nsw <4 x i32> %10, %9
38    %12 = add <4 x i32> %11, %vec.phi
39    %scevgep = getelementptr i16, ptr %lsr.iv, i32 4
40    %scevgep19 = getelementptr i16, ptr %lsr.iv18, i32 4
41    %13 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)
42    %14 = icmp ne i32 %13, 0
43    %lsr.iv.next = add nsw i32 %lsr.iv1, -1
44    br i1 %14, label %vector.body, label %middle.block
45
46  middle.block:                                     ; preds = %vector.body
47    %15 = add i32 %8, 4
48    %16 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %15)
49    %17 = select <4 x i1> %16, <4 x i32> %12, <4 x i32> %vec.phi
50    %18 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %17)
51    br label %for.cond.cleanup
52
53  for.cond.cleanup:                                 ; preds = %middle.block, %entry
54    %res.0.lcssa = phi i32 [ 0, %entry ], [ %18, %middle.block ]
55    ret i32 %res.0.lcssa
56  }
57  declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>)
58  declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
59  declare i32 @llvm.start.loop.iterations.i32(i32)
60  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
61  declare <4 x i1> @llvm.arm.mve.vctp32(i32)
62
63...
64---
65name:            wrong_vctp_liveout
66alignment:       2
67exposesReturnsTwice: false
68legalized:       false
69regBankSelected: false
70selected:        false
71failedISel:      false
72tracksRegLiveness: true
73hasWinCFI:       false
74registers:       []
75liveins:
76  - { reg: '$r0', virtual-reg: '' }
77  - { reg: '$r1', virtual-reg: '' }
78  - { reg: '$r2', virtual-reg: '' }
79frameInfo:
80  isFrameAddressTaken: false
81  isReturnAddressTaken: false
82  hasStackMap:     false
83  hasPatchPoint:   false
84  stackSize:       8
85  offsetAdjustment: 0
86  maxAlignment:    4
87  adjustsStack:    false
88  hasCalls:        false
89  stackProtector:  ''
90  maxCallFrameSize: 0
91  cvBytesOfCalleeSavedRegisters: 0
92  hasOpaqueSPAdjustment: false
93  hasVAStart:      false
94  hasMustTailInVarArgFunc: false
95  localFrameSize:  0
96  savePoint:       ''
97  restorePoint:    ''
98fixedStack:      []
99stack:
100  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
101      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
102      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
103  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
104      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
105      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
106callSites:       []
107constants:       []
108machineFunctionInfo: {}
109body:             |
110  ; CHECK-LABEL: name: wrong_vctp_liveout
111  ; CHECK: bb.0.entry:
112  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
113  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2, $r7
114  ; CHECK-NEXT: {{  $}}
115  ; CHECK-NEXT:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
116  ; CHECK-NEXT:   t2IT 0, 4, implicit-def $itstate
117  ; CHECK-NEXT:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
118  ; CHECK-NEXT:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
119  ; CHECK-NEXT: {{  $}}
120  ; CHECK-NEXT: bb.1.vector.ph:
121  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
122  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2, $r7
123  ; CHECK-NEXT: {{  $}}
124  ; CHECK-NEXT:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
125  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
126  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -4
127  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r7, -8
128  ; CHECK-NEXT:   renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
129  ; CHECK-NEXT:   renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
130  ; CHECK-NEXT:   renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
131  ; CHECK-NEXT:   renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
132  ; CHECK-NEXT:   renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
133  ; CHECK-NEXT:   renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
134  ; CHECK-NEXT:   dead $lr = t2DLS renamable $r12
135  ; CHECK-NEXT:   $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
136  ; CHECK-NEXT: {{  $}}
137  ; CHECK-NEXT: bb.2.vector.body:
138  ; CHECK-NEXT:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
139  ; CHECK-NEXT:   liveins: $q1, $r0, $r1, $r2, $r3
140  ; CHECK-NEXT: {{  $}}
141  ; CHECK-NEXT:   renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
142  ; CHECK-NEXT:   $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0
143  ; CHECK-NEXT:   MVE_VPST 4, implicit $vpr
144  ; CHECK-NEXT:   renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
145  ; CHECK-NEXT:   renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
146  ; CHECK-NEXT:   $lr = tMOVr $r3, 14 /* CC::al */, $noreg
147  ; CHECK-NEXT:   renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
148  ; CHECK-NEXT:   renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
149  ; CHECK-NEXT:   renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
150  ; CHECK-NEXT:   renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
151  ; CHECK-NEXT:   dead $lr = t2LEUpdate killed renamable $lr, %bb.2
152  ; CHECK-NEXT: {{  $}}
153  ; CHECK-NEXT: bb.3.middle.block:
154  ; CHECK-NEXT:   liveins: $q0, $q1, $r2
155  ; CHECK-NEXT: {{  $}}
156  ; CHECK-NEXT:   renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
157  ; CHECK-NEXT:   renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg, $noreg
158  ; CHECK-NEXT:   renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg
159  ; CHECK-NEXT:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
160  ; CHECK-NEXT:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
161  bb.0.entry:
162    successors: %bb.1(0x80000000)
163    liveins: $r0, $r1, $r2, $lr, $r7
164
165    tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
166    t2IT 0, 4, implicit-def $itstate
167    renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
168    tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
169
170  bb.1.vector.ph:
171    successors: %bb.2(0x80000000)
172    liveins: $r0, $r1, $r2, $lr, $r7
173
174    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
175    frame-setup CFI_INSTRUCTION def_cfa_offset 8
176    frame-setup CFI_INSTRUCTION offset $lr, -4
177    frame-setup CFI_INSTRUCTION offset $r7, -8
178    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
179    renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
180    renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
181    renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg
182    renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
183    renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
184    $lr = t2DoLoopStart renamable $r12
185    $r3 = tMOVr killed $r12, 14, $noreg
186
187  bb.2.vector.body:
188    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
189    liveins: $q1, $r0, $r1, $r2, $r3
190
191    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
192    $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, $noreg, undef $q0
193    MVE_VPST 4, implicit $vpr
194    renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
195    renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
196    $lr = tMOVr $r3, 14, $noreg
197    renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
198    renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg
199    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
200    renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
201    renamable $lr = t2LoopDec killed renamable $lr, 1
202    t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
203    tB %bb.3, 14, $noreg
204
205  bb.3.middle.block:
206    liveins: $q0, $q1, $r2
207
208    renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14, $noreg
209    renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg, $noreg
210    renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg
211    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
212    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
213
214...
215