1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s 3--- | 4 define dso_local void @legal_vaddv_s32(ptr nocapture readonly %a, ptr %c, i32 %N) { 5 entry: 6 %cmp9 = icmp eq i32 %N, 0 7 %tmp = add i32 %N, 3 8 %tmp1 = lshr i32 %tmp, 2 9 %tmp2 = shl nuw i32 %tmp1, 2 10 %tmp3 = add i32 %tmp2, -4 11 %tmp4 = lshr i32 %tmp3, 2 12 %tmp5 = add nuw nsw i32 %tmp4, 1 13 br i1 %cmp9, label %exit, label %vector.ph 14 15 vector.ph: ; preds = %entry 16 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 17 br label %vector.body 18 19 vector.body: ; preds = %vector.body, %vector.ph 20 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 21 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 22 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ] 23 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 24 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 25 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 26 %tmp9 = sub i32 %tmp7, 4 27 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 28 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> 29 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp10) 30 store i32 %tmp11, ptr %store.addr 31 %store.next = getelementptr i32, ptr %store.addr, i32 1 32 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4 33 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 34 %tmp13 = icmp ne i32 %tmp12, 0 35 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 36 br i1 %tmp13, label %vector.body, label %exit 37 38 exit: ; preds = %vector.body, %entry 39 ret void 40 } 41 42 define dso_local void @legal_vaddv_s16(ptr nocapture readonly %a, ptr %c, i32 %N) { 43 entry: 44 %cmp9 = icmp eq i32 %N, 0 45 %tmp = add i32 %N, 3 46 %tmp1 = lshr i32 %tmp, 2 47 %tmp2 = shl nuw i32 %tmp1, 2 48 %tmp3 = add i32 %tmp2, -4 49 %tmp4 = lshr i32 %tmp3, 2 50 %tmp5 = add nuw nsw i32 %tmp4, 1 51 br i1 %cmp9, label %exit, label %vector.ph 52 53 vector.ph: ; preds = %entry 54 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 55 br label %vector.body 56 57 vector.body: ; preds = %vector.body, %vector.ph 58 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 59 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 60 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ] 61 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 62 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 63 %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7) 64 %tmp9 = sub i32 %tmp7, 8 65 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef) 66 %sext = sext <8 x i16> %wide.masked.load to <8 x i32> 67 %tmp11 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %sext) 68 store i32 %tmp11, ptr %store.addr 69 %store.next = getelementptr i32, ptr %store.addr, i32 1 70 %scevgep = getelementptr i16, ptr %lsr.iv, i32 8 71 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 72 %tmp13 = icmp ne i32 %tmp12, 0 73 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 74 br i1 %tmp13, label %vector.body, label %exit 75 76 exit: ; preds = %vector.body, %entry 77 ret void 78 } 79 80 define dso_local void @legal_vaddv_s8(ptr nocapture readonly %a, ptr %c, i32 %N) { 81 entry: 82 %cmp9 = icmp eq i32 %N, 0 83 %tmp = add i32 %N, 7 84 %tmp1 = lshr i32 %tmp, 3 85 %tmp2 = shl nuw i32 %tmp1, 3 86 %tmp3 = add i32 %tmp2, -7 87 %tmp4 = lshr i32 %tmp3, 3 88 %tmp5 = add nuw nsw i32 %tmp4, 1 89 br i1 %cmp9, label %exit, label %vector.ph 90 91 vector.ph: ; preds = %entry 92 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 93 br label %vector.body 94 95 vector.body: ; preds = %vector.body, %vector.ph 96 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 97 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 98 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ] 99 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 100 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 101 %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7) 102 %tmp9 = sub i32 %tmp7, 16 103 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef) 104 %sext = sext <16 x i8> %wide.masked.load to <16 x i32> 105 %tmp11 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %sext) 106 store i32 %tmp11, ptr %store.addr 107 %store.next = getelementptr i32, ptr %store.addr, i32 1 108 %scevgep = getelementptr i8, ptr %lsr.iv, i32 16 109 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 110 %tmp13 = icmp ne i32 %tmp12, 0 111 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 112 br i1 %tmp13, label %vector.body, label %exit 113 114 exit: ; preds = %vector.body, %entry 115 ret void 116 } 117 118 define dso_local i32 @legal_vaddva_s32(ptr nocapture readonly %a, i32 %N) { 119 entry: 120 %cmp9 = icmp eq i32 %N, 0 121 %tmp = add i32 %N, 3 122 %tmp1 = lshr i32 %tmp, 2 123 %tmp2 = shl nuw i32 %tmp1, 2 124 %tmp3 = add i32 %tmp2, -4 125 %tmp4 = lshr i32 %tmp3, 2 126 %tmp5 = add nuw nsw i32 %tmp4, 1 127 br i1 %cmp9, label %exit, label %vector.ph 128 129 vector.ph: ; preds = %entry 130 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 131 br label %vector.body 132 133 vector.body: ; preds = %vector.body, %vector.ph 134 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 135 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 136 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 137 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] 138 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 139 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 140 %tmp9 = sub i32 %tmp7, 4 141 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 142 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> 143 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp10) 144 %acc.next = add i32 %tmp11, %acc 145 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4 146 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 147 %tmp13 = icmp ne i32 %tmp12, 0 148 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 149 br i1 %tmp13, label %vector.body, label %exit 150 151 exit: ; preds = %vector.body, %entry 152 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] 153 ret i32 %res 154 } 155 156 define dso_local void @illegal_vaddv_s32(ptr nocapture readonly %a, ptr %c, i32 %N) { 157 entry: 158 %cmp9 = icmp eq i32 %N, 0 159 %tmp = add i32 %N, 3 160 %tmp1 = lshr i32 %tmp, 2 161 %tmp2 = shl nuw i32 %tmp1, 2 162 %tmp3 = add i32 %tmp2, -4 163 %tmp4 = lshr i32 %tmp3, 2 164 %tmp5 = add nuw nsw i32 %tmp4, 1 165 br i1 %cmp9, label %exit, label %vector.ph 166 167 vector.ph: ; preds = %entry 168 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 169 br label %vector.body 170 171 vector.body: ; preds = %vector.body, %vector.ph 172 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 173 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 174 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ] 175 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 176 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 177 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 178 %tmp9 = sub i32 %tmp7, 4 179 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 180 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> 181 %not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1> 182 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %not) 183 store i32 %tmp11, ptr %store.addr 184 %store.next = getelementptr i32, ptr %store.addr, i32 1 185 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4 186 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 187 %tmp13 = icmp ne i32 %tmp12, 0 188 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 189 br i1 %tmp13, label %vector.body, label %exit 190 191 exit: ; preds = %vector.body, %entry 192 ret void 193 } 194 195 define dso_local i32 @illegal_vaddva_s32(ptr nocapture readonly %a, i32 %N) { 196 entry: 197 %cmp9 = icmp eq i32 %N, 0 198 %tmp = add i32 %N, 3 199 %tmp1 = lshr i32 %tmp, 2 200 %tmp2 = shl nuw i32 %tmp1, 2 201 %tmp3 = add i32 %tmp2, -4 202 %tmp4 = lshr i32 %tmp3, 2 203 %tmp5 = add nuw nsw i32 %tmp4, 1 204 br i1 %cmp9, label %exit, label %vector.ph 205 206 vector.ph: ; preds = %entry 207 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 208 br label %vector.body 209 210 vector.body: ; preds = %vector.body, %vector.ph 211 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 212 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 213 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 214 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] 215 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 216 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 217 %tmp9 = sub i32 %tmp7, 4 218 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 219 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> 220 %not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1> 221 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %not) 222 %acc.next = add i32 %tmp11, %acc 223 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4 224 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 225 %tmp13 = icmp ne i32 %tmp12, 0 226 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 227 br i1 %tmp13, label %vector.body, label %exit 228 229 exit: ; preds = %vector.body, %entry 230 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] 231 ret i32 %res 232 } 233 234 define dso_local void @illegal_vaddv_u32(ptr nocapture readonly %a, ptr %c, i32 %N) { 235 entry: 236 %cmp9 = icmp eq i32 %N, 0 237 %tmp = add i32 %N, 3 238 %tmp1 = lshr i32 %tmp, 2 239 %tmp2 = shl nuw i32 %tmp1, 2 240 %tmp3 = add i32 %tmp2, -4 241 %tmp4 = lshr i32 %tmp3, 2 242 %tmp5 = add nuw nsw i32 %tmp4, 1 243 br i1 %cmp9, label %exit, label %vector.ph 244 245 vector.ph: ; preds = %entry 246 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 247 br label %vector.body 248 249 vector.body: ; preds = %vector.body, %vector.ph 250 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 251 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 252 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ] 253 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 254 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 255 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 256 %tmp9 = sub i32 %tmp7, 4 257 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 258 %tmp10 = zext <4 x i16> %wide.masked.load to <4 x i32> 259 %not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1> 260 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %not) 261 store i32 %tmp11, ptr %store.addr 262 %store.next = getelementptr i32, ptr %store.addr, i32 1 263 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4 264 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 265 %tmp13 = icmp ne i32 %tmp12, 0 266 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 267 br i1 %tmp13, label %vector.body, label %exit 268 269 exit: ; preds = %vector.body, %entry 270 ret void 271 } 272 273 define dso_local i32 @illegal_vaddva_u32(ptr nocapture readonly %a, i32 %N) { 274 entry: 275 %cmp9 = icmp eq i32 %N, 0 276 %tmp = add i32 %N, 3 277 %tmp1 = lshr i32 %tmp, 2 278 %tmp2 = shl nuw i32 %tmp1, 2 279 %tmp3 = add i32 %tmp2, -4 280 %tmp4 = lshr i32 %tmp3, 2 281 %tmp5 = add nuw nsw i32 %tmp4, 1 282 br i1 %cmp9, label %exit, label %vector.ph 283 284 vector.ph: ; preds = %entry 285 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 286 br label %vector.body 287 288 vector.body: ; preds = %vector.body, %vector.ph 289 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 290 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 291 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 292 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] 293 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 294 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 295 %tmp9 = sub i32 %tmp7, 4 296 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 297 %tmp10 = zext <4 x i16> %wide.masked.load to <4 x i32> 298 %not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1> 299 %tmp11 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %not) 300 %acc.next = add i32 %tmp11, %acc 301 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4 302 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 303 %tmp13 = icmp ne i32 %tmp12, 0 304 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 305 br i1 %tmp13, label %vector.body, label %exit 306 307 exit: ; preds = %vector.body, %entry 308 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] 309 ret i32 %res 310 } 311 312 define dso_local void @illegal_vaddv_s16(ptr nocapture readonly %a, ptr %c, i32 %N, <8 x i16> %pass) { 313 entry: 314 %cmp9 = icmp eq i32 %N, 0 315 %tmp = add i32 %N, 3 316 %tmp1 = lshr i32 %tmp, 2 317 %tmp2 = shl nuw i32 %tmp1, 2 318 %tmp3 = add i32 %tmp2, -4 319 %tmp4 = lshr i32 %tmp3, 2 320 %tmp5 = add nuw nsw i32 %tmp4, 1 321 br i1 %cmp9, label %exit, label %vector.ph 322 323 vector.ph: ; preds = %entry 324 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 325 br label %vector.body 326 327 vector.body: ; preds = %vector.body, %vector.ph 328 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 329 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 330 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ] 331 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 332 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 333 %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7) 334 %tmp9 = sub i32 %tmp7, 8 335 %wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %lsr.iv17, i32 1, <8 x i1> %tmp8, <8 x i8> undef) 336 %sext.wide = sext <8 x i8> %wide.masked.load to <8 x i16> 337 %sub = sub <8 x i16> %sext.wide, %pass 338 %reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %sub) 339 %sext.reduce = sext i16 %reduce to i32 340 store i32 %sext.reduce, ptr %store.addr 341 %store.next = getelementptr i32, ptr %store.addr, i32 1 342 %scevgep = getelementptr i8, ptr %lsr.iv, i32 8 343 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 344 %tmp13 = icmp ne i32 %tmp12, 0 345 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 346 br i1 %tmp13, label %vector.body, label %exit 347 348 exit: ; preds = %vector.body, %entry 349 ret void 350 } 351 352 define dso_local i32 @illegal_vaddva_s16(ptr nocapture readonly %a, i32 %N, <8 x i16> %pass) { 353 entry: 354 %cmp9 = icmp eq i32 %N, 0 355 %tmp = add i32 %N, 3 356 %tmp1 = lshr i32 %tmp, 2 357 %tmp2 = shl nuw i32 %tmp1, 2 358 %tmp3 = add i32 %tmp2, -4 359 %tmp4 = lshr i32 %tmp3, 2 360 %tmp5 = add nuw nsw i32 %tmp4, 1 361 br i1 %cmp9, label %exit, label %vector.ph 362 363 vector.ph: ; preds = %entry 364 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 365 br label %vector.body 366 367 vector.body: ; preds = %vector.body, %vector.ph 368 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 369 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 370 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 371 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] 372 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 373 %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7) 374 %tmp9 = sub i32 %tmp7, 8 375 %wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %lsr.iv17, i32 1, <8 x i1> %tmp8, <8 x i8> undef) 376 %sext.wide = sext <8 x i8> %wide.masked.load to <8 x i16> 377 %sub = sub <8 x i16> %sext.wide, %pass 378 %reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %sub) 379 %sext.reduce = sext i16 %reduce to i32 380 %acc.next = add i32 %sext.reduce, %acc 381 %scevgep = getelementptr i8, ptr %lsr.iv, i32 8 382 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 383 %tmp13 = icmp ne i32 %tmp12, 0 384 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 385 br i1 %tmp13, label %vector.body, label %exit 386 387 exit: ; preds = %vector.body, %entry 388 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] 389 ret i32 %res 390 } 391 392 define dso_local void @illegal_vaddv_u16(ptr nocapture readonly %a, ptr %c, i32 %N, <8 x i16> %pass) { 393 entry: 394 %cmp9 = icmp eq i32 %N, 0 395 %tmp = add i32 %N, 3 396 %tmp1 = lshr i32 %tmp, 2 397 %tmp2 = shl nuw i32 %tmp1, 2 398 %tmp3 = add i32 %tmp2, -4 399 %tmp4 = lshr i32 %tmp3, 2 400 %tmp5 = add nuw nsw i32 %tmp4, 1 401 br i1 %cmp9, label %exit, label %vector.ph 402 403 vector.ph: ; preds = %entry 404 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 405 br label %vector.body 406 407 vector.body: ; preds = %vector.body, %vector.ph 408 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 409 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 410 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ] 411 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 412 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 413 %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7) 414 %tmp9 = sub i32 %tmp7, 8 415 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef) 416 %sub = sub <8 x i16> %wide.masked.load, %pass 417 %reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %sub) 418 %zext.reduce = zext i16 %reduce to i32 419 store i32 %zext.reduce, ptr %store.addr 420 %store.next = getelementptr i32, ptr %store.addr, i32 1 421 %scevgep = getelementptr i16, ptr %lsr.iv, i32 8 422 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 423 %tmp13 = icmp ne i32 %tmp12, 0 424 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 425 br i1 %tmp13, label %vector.body, label %exit 426 427 exit: ; preds = %vector.body, %entry 428 ret void 429 } 430 431 define dso_local i32 @illegal_vaddva_u16(ptr nocapture readonly %a, i32 %N, <8 x i16> %pass) { 432 entry: 433 %cmp9 = icmp eq i32 %N, 0 434 %tmp = add i32 %N, 3 435 %tmp1 = lshr i32 %tmp, 2 436 %tmp2 = shl nuw i32 %tmp1, 2 437 %tmp3 = add i32 %tmp2, -4 438 %tmp4 = lshr i32 %tmp3, 2 439 %tmp5 = add nuw nsw i32 %tmp4, 1 440 br i1 %cmp9, label %exit, label %vector.ph 441 442 vector.ph: ; preds = %entry 443 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 444 br label %vector.body 445 446 vector.body: ; preds = %vector.body, %vector.ph 447 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 448 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 449 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 450 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] 451 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 452 %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7) 453 %tmp9 = sub i32 %tmp7, 8 454 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef) 455 %sub = sub <8 x i16> %wide.masked.load, %pass 456 %reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %sub) 457 %zext.reduce = zext i16 %reduce to i32 458 %acc.next = add i32 %zext.reduce, %acc 459 %scevgep = getelementptr i16, ptr %lsr.iv, i32 8 460 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 461 %tmp13 = icmp ne i32 %tmp12, 0 462 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 463 br i1 %tmp13, label %vector.body, label %exit 464 465 exit: ; preds = %vector.body, %entry 466 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] 467 ret i32 %res 468 } 469 470 define dso_local void @illegal_vaddv_s8(ptr nocapture readonly %a, ptr %c, i32 %N, <16 x i8> %pass) { 471 entry: 472 %cmp9 = icmp eq i32 %N, 0 473 %tmp = add i32 %N, 7 474 %tmp1 = lshr i32 %tmp, 3 475 %tmp2 = shl nuw i32 %tmp1, 3 476 %tmp3 = add i32 %tmp2, -7 477 %tmp4 = lshr i32 %tmp3, 3 478 %tmp5 = add nuw nsw i32 %tmp4, 1 479 br i1 %cmp9, label %exit, label %vector.ph 480 481 vector.ph: ; preds = %entry 482 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 483 br label %vector.body 484 485 vector.body: ; preds = %vector.body, %vector.ph 486 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 487 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 488 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ] 489 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 490 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 491 %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7) 492 %tmp9 = sub i32 %tmp7, 16 493 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef) 494 %xor = xor <16 x i8> %wide.masked.load, %pass 495 %reduce = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %xor) 496 %sext.reduce = sext i8 %reduce to i32 497 store i32 %sext.reduce, ptr %store.addr 498 %store.next = getelementptr i32, ptr %store.addr, i32 1 499 %scevgep = getelementptr i8, ptr %lsr.iv, i32 16 500 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 501 %tmp13 = icmp ne i32 %tmp12, 0 502 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 503 br i1 %tmp13, label %vector.body, label %exit 504 505 exit: ; preds = %vector.body, %entry 506 ret void 507 } 508 509 define dso_local i32 @illegal_vaddva_s8(ptr nocapture readonly %a, i32 %N, <16 x i8> %pass) { 510 entry: 511 %cmp9 = icmp eq i32 %N, 0 512 %tmp = add i32 %N, 7 513 %tmp1 = lshr i32 %tmp, 3 514 %tmp2 = shl nuw i32 %tmp1, 3 515 %tmp3 = add i32 %tmp2, -7 516 %tmp4 = lshr i32 %tmp3, 3 517 %tmp5 = add nuw nsw i32 %tmp4, 1 518 br i1 %cmp9, label %exit, label %vector.ph 519 520 vector.ph: ; preds = %entry 521 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 522 br label %vector.body 523 524 vector.body: ; preds = %vector.body, %vector.ph 525 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 526 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 527 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 528 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] 529 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 530 %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7) 531 %tmp9 = sub i32 %tmp7, 16 532 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef) 533 %xor = xor <16 x i8> %wide.masked.load, %pass 534 %reduce = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %xor) 535 %sext.reduce = sext i8 %reduce to i32 536 %acc.next = add i32 %sext.reduce, %acc 537 %scevgep = getelementptr i8, ptr %lsr.iv, i32 16 538 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 539 %tmp13 = icmp ne i32 %tmp12, 0 540 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 541 br i1 %tmp13, label %vector.body, label %exit 542 543 exit: ; preds = %vector.body, %entry 544 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] 545 ret i32 %res 546 } 547 548 define dso_local void @illegal_vaddv_u8(ptr nocapture readonly %a, ptr %c, i32 %N, <16 x i8> %pass) { 549 entry: 550 %cmp9 = icmp eq i32 %N, 0 551 %tmp = add i32 %N, 7 552 %tmp1 = lshr i32 %tmp, 3 553 %tmp2 = shl nuw i32 %tmp1, 3 554 %tmp3 = add i32 %tmp2, -7 555 %tmp4 = lshr i32 %tmp3, 3 556 %tmp5 = add nuw nsw i32 %tmp4, 1 557 br i1 %cmp9, label %exit, label %vector.ph 558 559 vector.ph: ; preds = %entry 560 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 561 br label %vector.body 562 563 vector.body: ; preds = %vector.body, %vector.ph 564 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 565 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 566 %store.addr = phi ptr [ %c, %vector.ph ], [ %store.next, %vector.body ] 567 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 568 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 569 %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7) 570 %tmp9 = sub i32 %tmp7, 16 571 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef) 572 %xor = xor <16 x i8> %wide.masked.load, %pass 573 %reduce = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %xor) 574 %zext.reduce = zext i8 %reduce to i32 575 store i32 %zext.reduce, ptr %store.addr 576 %store.next = getelementptr i32, ptr %store.addr, i32 1 577 %scevgep = getelementptr i8, ptr %lsr.iv, i32 16 578 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 579 %tmp13 = icmp ne i32 %tmp12, 0 580 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 581 br i1 %tmp13, label %vector.body, label %exit 582 583 exit: ; preds = %vector.body, %entry 584 ret void 585 } 586 587 define dso_local i32 @illegal_vaddva_u8(ptr nocapture readonly %a, i32 %N, <16 x i8> %pass) { 588 entry: 589 %cmp9 = icmp eq i32 %N, 0 590 %tmp = add i32 %N, 7 591 %tmp1 = lshr i32 %tmp, 3 592 %tmp2 = shl nuw i32 %tmp1, 3 593 %tmp3 = add i32 %tmp2, -7 594 %tmp4 = lshr i32 %tmp3, 3 595 %tmp5 = add nuw nsw i32 %tmp4, 1 596 br i1 %cmp9, label %exit, label %vector.ph 597 598 vector.ph: ; preds = %entry 599 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 600 br label %vector.body 601 602 vector.body: ; preds = %vector.body, %vector.ph 603 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 604 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 605 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 606 %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] 607 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 608 %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7) 609 %tmp9 = sub i32 %tmp7, 16 610 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef) 611 %xor = xor <16 x i8> %wide.masked.load, %pass 612 %reduce = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %xor) 613 %zext.reduce = zext i8 %reduce to i32 614 %acc.next = add i32 %zext.reduce, %acc 615 %scevgep = getelementptr i8, ptr %lsr.iv, i32 16 616 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 617 %tmp13 = icmp ne i32 %tmp12, 0 618 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 619 br i1 %tmp13, label %vector.body, label %exit 620 621 exit: ; preds = %vector.body, %entry 622 %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] 623 ret i32 %res 624 } 625 626 define hidden i32 @regalloc_legality_vaddva_u32(ptr %x, ptr %y, i32 %n) { 627 entry: 628 %cmp22 = icmp sgt i32 %n, 0 629 %0 = add i32 %n, 3 630 %1 = icmp slt i32 %n, 4 631 %smin = select i1 %1, i32 %n, i32 4 632 %2 = sub i32 %0, %smin 633 %3 = lshr i32 %2, 2 634 %4 = add nuw nsw i32 %3, 1 635 br i1 %cmp22, label %while.body.preheader, label %while.end 636 637 while.body.preheader: ; preds = %entry 638 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4) 639 br label %while.body 640 641 while.body: ; preds = %while.body.preheader, %while.body 642 %x.addr.026 = phi ptr [ %add.ptr, %while.body ], [ %x, %while.body.preheader ] 643 %y.addr.025 = phi ptr [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ] 644 %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ] 645 %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ] 646 %5 = phi i32 [ %start, %while.body.preheader ], [ %6, %while.body ] 647 %tmp3 = bitcast ptr %y.addr.025 to ptr 648 %tmp1 = bitcast ptr %x.addr.026 to ptr 649 %tmp = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %n.addr.023) 650 %tmp2 = tail call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %tmp1, i32 2, <4 x i1> %tmp, <4 x i16> zeroinitializer) 651 %zext.wide.1 = zext <4 x i16> %tmp2 to <4 x i32> 652 %tmp4 = tail call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %tmp3, i32 2, <4 x i1> %tmp, <4 x i16> zeroinitializer) 653 %zext.wide.2 = zext <4 x i16> %tmp4 to <4 x i32> 654 %or = or <4 x i32> %zext.wide.1, %zext.wide.2 655 %reduce = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %or) 656 %acc.next = add i32 %reduce, %acc 657 %add.ptr = getelementptr inbounds i16, ptr %x.addr.026, i32 4 658 %add.ptr4 = getelementptr inbounds i16, ptr %y.addr.025, i32 4 659 %sub = add nsw i32 %n.addr.023, -4 660 %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1) 661 %7 = icmp ne i32 %6, 0 662 br i1 %7, label %while.body, label %while.end 663 664 while.end: ; preds = %while.body, %entry 665 %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ] 666 ret i32 %res 667 } 668 669 define hidden i32 @regalloc_legality_vaddv_u16(ptr %x, ptr %y, i32 %n) { 670 entry: 671 %cmp22 = icmp sgt i32 %n, 0 672 %0 = add i32 %n, 7 673 %1 = icmp slt i32 %n, 8 674 %smin = select i1 %1, i32 %n, i32 8 675 %2 = sub i32 %0, %smin 676 %3 = lshr i32 %2, 3 677 %4 = add nuw nsw i32 %3, 1 678 br i1 %cmp22, label %while.body.preheader, label %while.end 679 680 while.body.preheader: ; preds = %entry 681 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4) 682 br label %while.body 683 684 while.body: ; preds = %while.body.preheader, %while.body 685 %x.addr.026 = phi ptr [ %add.ptr, %while.body ], [ %x, %while.body.preheader ] 686 %y.addr.025 = phi ptr [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ] 687 %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ] 688 %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ] 689 %5 = phi i32 [ %start, %while.body.preheader ], [ %6, %while.body ] 690 %tmp3 = bitcast ptr %y.addr.025 to ptr 691 %tmp1 = bitcast ptr %x.addr.026 to ptr 692 %tmp = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %n.addr.023) 693 %tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) 694 %tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) 695 %or = or <8 x i16> %tmp2, %tmp4 696 %reduce = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %or) 697 %zext.reduce = zext i16 %reduce to i32 698 %acc.next = add i32 %zext.reduce, %acc 699 %add.ptr = getelementptr inbounds i16, ptr %x.addr.026, i32 8 700 %add.ptr4 = getelementptr inbounds i16, ptr %y.addr.025, i32 8 701 %sub = add nsw i32 %n.addr.023, -8 702 %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1) 703 %7 = icmp ne i32 %6, 0 704 br i1 %7, label %while.body, label %while.end 705 706 while.end: ; preds = %while.body, %entry 707 %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ] 708 ret i32 %res 709 } 710 711 define hidden i32 @regalloc_illegality_vaddva_s32(ptr %x, ptr %y, ptr %z, i32 %n) { 712 entry: 713 %cmp22 = icmp sgt i32 %n, 0 714 %0 = add i32 %n, 7 715 %1 = icmp slt i32 %n, 8 716 %smin = select i1 %1, i32 %n, i32 8 717 %2 = sub i32 %0, %smin 718 %3 = lshr i32 %2, 3 719 %4 = add nuw nsw i32 %3, 1 720 br i1 %cmp22, label %while.body.preheader, label %while.end 721 722 while.body.preheader: ; preds = %entry 723 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4) 724 br label %while.body 725 726 while.body: ; preds = %while.body.preheader, %while.body 727 %x.addr.026 = phi ptr [ %add.ptr, %while.body ], [ %x, %while.body.preheader ] 728 %y.addr.025 = phi ptr [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ] 729 %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ] 730 %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ] 731 %5 = phi i32 [ %start, %while.body.preheader ], [ %6, %while.body ] 732 %tmp3 = bitcast ptr %y.addr.025 to ptr 733 %tmp1 = bitcast ptr %x.addr.026 to ptr 734 %tmp = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %n.addr.023) 735 %tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) 736 %tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) 737 %tmp5 = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 1) 738 %tmp6 = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 0) 739 %mul = add <4 x i32> %tmp5, %tmp6 740 %reduce = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %mul) 741 %acc.next = add i32 %reduce, %acc 742 %add.ptr = getelementptr inbounds i16, ptr %x.addr.026, i32 8 743 %add.ptr4 = getelementptr inbounds i16, ptr %y.addr.025, i32 8 744 %sub = add nsw i32 %n.addr.023, -8 745 %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1) 746 %7 = icmp ne i32 %6, 0 747 br i1 %7, label %while.body, label %while.end 748 749 while.end: ; preds = %while.body, %entry 750 %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ] 751 ret i32 %res 752 } 753 754 define hidden i32 @illegal_vmull_non_zero(ptr %x, ptr %y, ptr %z, i32 %n) { 755 entry: 756 %cmp22 = icmp sgt i32 %n, 0 757 %0 = add i32 %n, 7 758 %1 = icmp slt i32 %n, 8 759 %smin = select i1 %1, i32 %n, i32 8 760 %2 = sub i32 %0, %smin 761 %3 = lshr i32 %2, 3 762 %4 = add nuw nsw i32 %3, 1 763 br i1 %cmp22, label %while.body.preheader, label %while.end 764 765 while.body.preheader: ; preds = %entry 766 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4) 767 br label %while.body 768 769 while.body: ; preds = %while.body.preheader, %while.body 770 %x.addr.026 = phi ptr [ %add.ptr, %while.body ], [ %x, %while.body.preheader ] 771 %y.addr.025 = phi ptr [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ] 772 %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ] 773 %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ] 774 %5 = phi i32 [ %start, %while.body.preheader ], [ %6, %while.body ] 775 %tmp3 = bitcast ptr %y.addr.025 to ptr 776 %tmp1 = bitcast ptr %x.addr.026 to ptr 777 %tmp = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %n.addr.023) 778 %tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) 779 %tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) 780 %mul = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 1) 781 %reduce = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %mul) 782 %acc.next = add i32 %reduce, %acc 783 %add.ptr = getelementptr inbounds i16, ptr %x.addr.026, i32 8 784 %add.ptr4 = getelementptr inbounds i16, ptr %y.addr.025, i32 8 785 %sub = add nsw i32 %n.addr.023, -8 786 %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1) 787 %7 = icmp ne i32 %6, 0 788 br i1 %7, label %while.body, label %while.end 789 790 while.end: ; preds = %while.body, %entry 791 %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ] 792 ret i32 %res 793 } 794 795 declare <8 x i8> @llvm.masked.load.v8i8.p0(ptr, i32 immarg, <8 x i1>, <8 x i8>) 796 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>) 797 declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32 immarg, <8 x i1>, <8 x i16>) 798 declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr, i32 immarg, <16 x i1>, <16 x i8>) 799 declare void @llvm.masked.store.v8i16.p0(<8 x i16>, ptr, i32 immarg, <8 x i1>) 800 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>) 801 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) 802 declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>) 803 declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>) 804 declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>) 805 declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>) 806 declare i32 @llvm.start.loop.iterations.i32(i32) 807 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 808 declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) 809 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 810 declare <8 x i1> @llvm.arm.mve.vctp16(i32) 811 declare <16 x i1> @llvm.arm.mve.vctp8(i32) 812 813... 814--- 815name: legal_vaddv_s32 816alignment: 2 817tracksRegLiveness: true 818registers: [] 819liveins: 820 - { reg: '$r0', virtual-reg: '' } 821 - { reg: '$r1', virtual-reg: '' } 822 - { reg: '$r2', virtual-reg: '' } 823frameInfo: 824 stackSize: 8 825 offsetAdjustment: 0 826 maxAlignment: 4 827 stackProtector: '' 828 maxCallFrameSize: 0 829 cvBytesOfCalleeSavedRegisters: 0 830 localFrameSize: 0 831 savePoint: '' 832 restorePoint: '' 833fixedStack: [] 834stack: 835 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 836 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 837 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 838 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 839 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 840 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 841callSites: [] 842constants: [] 843machineFunctionInfo: {} 844body: | 845 ; CHECK-LABEL: name: legal_vaddv_s32 846 ; CHECK: bb.0.entry: 847 ; CHECK-NEXT: successors: %bb.1(0x80000000) 848 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 849 ; CHECK-NEXT: {{ $}} 850 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 851 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 852 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 853 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 854 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 855 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 856 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 857 ; CHECK-NEXT: {{ $}} 858 ; CHECK-NEXT: bb.1.vector.ph: 859 ; CHECK-NEXT: successors: %bb.2(0x80000000) 860 ; CHECK-NEXT: liveins: $r0, $r1, $r2 861 ; CHECK-NEXT: {{ $}} 862 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 863 ; CHECK-NEXT: {{ $}} 864 ; CHECK-NEXT: bb.2.vector.body: 865 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 866 ; CHECK-NEXT: liveins: $lr, $r0, $r1 867 ; CHECK-NEXT: {{ $}} 868 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 869 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg 870 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 871 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 872 ; CHECK-NEXT: {{ $}} 873 ; CHECK-NEXT: bb.3.exit: 874 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 875 bb.0.entry: 876 successors: %bb.1(0x80000000) 877 liveins: $r0, $r1, $r2, $r7, $lr 878 879 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 880 frame-setup CFI_INSTRUCTION def_cfa_offset 8 881 frame-setup CFI_INSTRUCTION offset $lr, -4 882 frame-setup CFI_INSTRUCTION offset $r7, -8 883 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 884 t2IT 0, 8, implicit-def $itstate 885 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 886 887 bb.1.vector.ph: 888 successors: %bb.2(0x80000000) 889 liveins: $r0, $r1, $r2, $r7, $lr 890 891 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 892 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 893 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 894 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 895 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 896 $lr = t2DoLoopStart renamable $r12 897 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg 898 899 bb.2.vector.body: 900 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 901 liveins: $r0, $r1, $r2, $r3 902 903 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 904 MVE_VPST 8, implicit $vpr 905 renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 906 renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg 907 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 908 early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 909 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 910 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 911 renamable $lr = t2LoopDec killed renamable $lr, 1 912 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 913 tB %bb.3, 14 /* CC::al */, $noreg 914 915 bb.3.exit: 916 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 917 918... 919--- 920name: legal_vaddv_s16 921alignment: 2 922tracksRegLiveness: true 923registers: [] 924liveins: 925 - { reg: '$r0', virtual-reg: '' } 926 - { reg: '$r1', virtual-reg: '' } 927 - { reg: '$r2', virtual-reg: '' } 928frameInfo: 929 stackSize: 8 930 offsetAdjustment: 0 931 maxAlignment: 4 932 stackProtector: '' 933 maxCallFrameSize: 0 934 cvBytesOfCalleeSavedRegisters: 0 935 localFrameSize: 0 936 savePoint: '' 937 restorePoint: '' 938fixedStack: [] 939stack: 940 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 941 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 942 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 943 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 944 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 945 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 946callSites: [] 947constants: [] 948machineFunctionInfo: {} 949body: | 950 ; CHECK-LABEL: name: legal_vaddv_s16 951 ; CHECK: bb.0.entry: 952 ; CHECK-NEXT: successors: %bb.1(0x80000000) 953 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 954 ; CHECK-NEXT: {{ $}} 955 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 956 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 957 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 958 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 959 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 960 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 961 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 962 ; CHECK-NEXT: {{ $}} 963 ; CHECK-NEXT: bb.1.vector.ph: 964 ; CHECK-NEXT: successors: %bb.2(0x80000000) 965 ; CHECK-NEXT: liveins: $r0, $r1, $r2 966 ; CHECK-NEXT: {{ $}} 967 ; CHECK-NEXT: $lr = MVE_DLSTP_16 killed renamable $r2 968 ; CHECK-NEXT: {{ $}} 969 ; CHECK-NEXT: bb.2.vector.body: 970 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 971 ; CHECK-NEXT: liveins: $lr, $r0, $r1 972 ; CHECK-NEXT: {{ $}} 973 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg, $noreg :: (load (s128) from %ir.lsr.iv17, align 2) 974 ; CHECK-NEXT: renamable $r12 = MVE_VADDVs16no_acc killed renamable $q0, 0, $noreg, $noreg 975 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 976 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 977 ; CHECK-NEXT: {{ $}} 978 ; CHECK-NEXT: bb.3.exit: 979 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 980 bb.0.entry: 981 successors: %bb.1(0x80000000) 982 liveins: $r0, $r1, $r2, $r7, $lr 983 984 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 985 frame-setup CFI_INSTRUCTION def_cfa_offset 8 986 frame-setup CFI_INSTRUCTION offset $lr, -4 987 frame-setup CFI_INSTRUCTION offset $r7, -8 988 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 989 t2IT 0, 8, implicit-def $itstate 990 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 991 992 bb.1.vector.ph: 993 successors: %bb.2(0x80000000) 994 liveins: $r0, $r1, $r2, $r7, $lr 995 996 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 997 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 998 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 999 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1000 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1001 $lr = t2DoLoopStart renamable $r12 1002 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg 1003 1004 bb.2.vector.body: 1005 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1006 liveins: $r0, $r1, $r2, $r3 1007 1008 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg 1009 MVE_VPST 8, implicit $vpr 1010 renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2) 1011 renamable $r12 = MVE_VADDVs16no_acc killed renamable $q0, 0, $noreg, $noreg 1012 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1013 early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 1014 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1015 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg 1016 renamable $lr = t2LoopDec killed renamable $lr, 1 1017 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1018 tB %bb.3, 14 /* CC::al */, $noreg 1019 1020 bb.3.exit: 1021 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1022 1023... 1024--- 1025name: legal_vaddv_s8 1026alignment: 2 1027tracksRegLiveness: true 1028registers: [] 1029liveins: 1030 - { reg: '$r0', virtual-reg: '' } 1031 - { reg: '$r1', virtual-reg: '' } 1032 - { reg: '$r2', virtual-reg: '' } 1033frameInfo: 1034 stackSize: 8 1035 offsetAdjustment: 0 1036 maxAlignment: 4 1037 stackProtector: '' 1038 maxCallFrameSize: 0 1039 cvBytesOfCalleeSavedRegisters: 0 1040 localFrameSize: 0 1041 savePoint: '' 1042 restorePoint: '' 1043fixedStack: [] 1044stack: 1045 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1046 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1047 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1048 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1049 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1050 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1051callSites: [] 1052constants: [] 1053machineFunctionInfo: {} 1054body: | 1055 ; CHECK-LABEL: name: legal_vaddv_s8 1056 ; CHECK: bb.0.entry: 1057 ; CHECK-NEXT: successors: %bb.1(0x80000000) 1058 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 1059 ; CHECK-NEXT: {{ $}} 1060 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1061 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1062 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 1063 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 1064 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1065 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 1066 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1067 ; CHECK-NEXT: {{ $}} 1068 ; CHECK-NEXT: bb.1.vector.ph: 1069 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1070 ; CHECK-NEXT: liveins: $r0, $r1, $r2 1071 ; CHECK-NEXT: {{ $}} 1072 ; CHECK-NEXT: $lr = MVE_DLSTP_8 killed renamable $r2 1073 ; CHECK-NEXT: {{ $}} 1074 ; CHECK-NEXT: bb.2.vector.body: 1075 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1076 ; CHECK-NEXT: liveins: $lr, $r0, $r1 1077 ; CHECK-NEXT: {{ $}} 1078 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRBU8_post killed renamable $r0, 16, 0, killed $noreg, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) 1079 ; CHECK-NEXT: renamable $r12 = MVE_VADDVs8no_acc killed renamable $q0, 0, $noreg, $noreg 1080 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 1081 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 1082 ; CHECK-NEXT: {{ $}} 1083 ; CHECK-NEXT: bb.3.exit: 1084 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1085 bb.0.entry: 1086 successors: %bb.1(0x80000000) 1087 liveins: $r0, $r1, $r2, $r7, $lr 1088 1089 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1090 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1091 frame-setup CFI_INSTRUCTION offset $lr, -4 1092 frame-setup CFI_INSTRUCTION offset $r7, -8 1093 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1094 t2IT 0, 8, implicit-def $itstate 1095 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1096 1097 bb.1.vector.ph: 1098 successors: %bb.2(0x80000000) 1099 liveins: $r0, $r1, $r2, $r7, $lr 1100 1101 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg 1102 renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 1103 renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 1104 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1105 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 1106 $lr = t2DoLoopStart renamable $r12 1107 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg 1108 1109 bb.2.vector.body: 1110 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1111 liveins: $r0, $r1, $r2, $r3 1112 1113 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 1114 MVE_VPST 8, implicit $vpr 1115 renamable $r0, renamable $q0 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) 1116 renamable $r12 = MVE_VADDVs8no_acc killed renamable $q0, 0, $noreg, $noreg 1117 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1118 early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 1119 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1120 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 1121 renamable $lr = t2LoopDec killed renamable $lr, 1 1122 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1123 tB %bb.3, 14 /* CC::al */, $noreg 1124 1125 bb.3.exit: 1126 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1127 1128... 1129--- 1130name: legal_vaddva_s32 1131alignment: 2 1132tracksRegLiveness: true 1133registers: [] 1134liveins: 1135 - { reg: '$r0', virtual-reg: '' } 1136 - { reg: '$r1', virtual-reg: '' } 1137frameInfo: 1138 stackSize: 8 1139 offsetAdjustment: 0 1140 maxAlignment: 4 1141 stackProtector: '' 1142 maxCallFrameSize: 0 1143 cvBytesOfCalleeSavedRegisters: 0 1144 localFrameSize: 0 1145 savePoint: '' 1146 restorePoint: '' 1147fixedStack: [] 1148stack: 1149 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1150 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1151 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1152 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1153 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1154 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1155callSites: [] 1156constants: [] 1157machineFunctionInfo: {} 1158body: | 1159 ; CHECK-LABEL: name: legal_vaddva_s32 1160 ; CHECK: bb.0.entry: 1161 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) 1162 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r7 1163 ; CHECK-NEXT: {{ $}} 1164 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1165 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1166 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 1167 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 1168 ; CHECK-NEXT: tCBZ $r1, %bb.4 1169 ; CHECK-NEXT: {{ $}} 1170 ; CHECK-NEXT: bb.1.vector.ph: 1171 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1172 ; CHECK-NEXT: liveins: $r0, $r1 1173 ; CHECK-NEXT: {{ $}} 1174 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r1 1175 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1176 ; CHECK-NEXT: {{ $}} 1177 ; CHECK-NEXT: bb.2.vector.body: 1178 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1179 ; CHECK-NEXT: liveins: $lr, $r0, $r2 1180 ; CHECK-NEXT: {{ $}} 1181 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 1182 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg 1183 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 1184 ; CHECK-NEXT: {{ $}} 1185 ; CHECK-NEXT: bb.3.exit: 1186 ; CHECK-NEXT: liveins: $r2 1187 ; CHECK-NEXT: {{ $}} 1188 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1189 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1190 ; CHECK-NEXT: {{ $}} 1191 ; CHECK-NEXT: bb.4: 1192 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1193 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1194 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1195 bb.0.entry: 1196 successors: %bb.4(0x30000000), %bb.1(0x50000000) 1197 liveins: $r0, $r1, $r7, $lr 1198 1199 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1200 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1201 frame-setup CFI_INSTRUCTION offset $lr, -4 1202 frame-setup CFI_INSTRUCTION offset $r7, -8 1203 tCBZ $r1, %bb.4 1204 1205 bb.1.vector.ph: 1206 successors: %bb.2(0x80000000) 1207 liveins: $r0, $r1 1208 1209 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 1210 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1211 renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 1212 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1213 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 1214 $lr = t2DoLoopStart renamable $r2 1215 $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1216 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1217 1218 bb.2.vector.body: 1219 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1220 liveins: $r0, $r1, $r2, $r3 1221 1222 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg 1223 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1224 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1225 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 1226 MVE_VPST 8, implicit $vpr 1227 renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 1228 renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg 1229 renamable $lr = t2LoopDec killed renamable $lr, 1 1230 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1231 tB %bb.3, 14 /* CC::al */, $noreg 1232 1233 bb.3.exit: 1234 liveins: $r2 1235 1236 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1237 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1238 1239 bb.4: 1240 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1241 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1242 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1243 1244... 1245--- 1246name: illegal_vaddv_s32 1247alignment: 2 1248tracksRegLiveness: true 1249registers: [] 1250liveins: 1251 - { reg: '$r0', virtual-reg: '' } 1252 - { reg: '$r1', virtual-reg: '' } 1253 - { reg: '$r2', virtual-reg: '' } 1254frameInfo: 1255 stackSize: 8 1256 offsetAdjustment: 0 1257 maxAlignment: 4 1258 stackProtector: '' 1259 maxCallFrameSize: 0 1260 cvBytesOfCalleeSavedRegisters: 0 1261 localFrameSize: 0 1262 savePoint: '' 1263 restorePoint: '' 1264fixedStack: [] 1265stack: 1266 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1267 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1268 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1269 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1270 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1271 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1272callSites: [] 1273constants: [] 1274machineFunctionInfo: {} 1275body: | 1276 ; CHECK-LABEL: name: illegal_vaddv_s32 1277 ; CHECK: bb.0.entry: 1278 ; CHECK-NEXT: successors: %bb.1(0x80000000) 1279 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 1280 ; CHECK-NEXT: {{ $}} 1281 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1282 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1283 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 1284 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 1285 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1286 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 1287 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1288 ; CHECK-NEXT: {{ $}} 1289 ; CHECK-NEXT: bb.1.vector.ph: 1290 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1291 ; CHECK-NEXT: liveins: $r0, $r1, $r2 1292 ; CHECK-NEXT: {{ $}} 1293 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1294 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1295 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1296 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1297 ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1298 ; CHECK-NEXT: dead $lr = t2DLS renamable $r12 1299 ; CHECK-NEXT: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg 1300 ; CHECK-NEXT: {{ $}} 1301 ; CHECK-NEXT: bb.2.vector.body: 1302 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1303 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 1304 ; CHECK-NEXT: {{ $}} 1305 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 1306 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 1307 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 1308 ; CHECK-NEXT: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 1309 ; CHECK-NEXT: $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1310 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg 1311 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1312 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 1313 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1314 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 1315 ; CHECK-NEXT: {{ $}} 1316 ; CHECK-NEXT: bb.3.exit: 1317 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1318 bb.0.entry: 1319 successors: %bb.1(0x80000000) 1320 liveins: $r0, $r1, $r2, $r7, $lr 1321 1322 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1323 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1324 frame-setup CFI_INSTRUCTION offset $lr, -4 1325 frame-setup CFI_INSTRUCTION offset $r7, -8 1326 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1327 t2IT 0, 8, implicit-def $itstate 1328 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1329 1330 bb.1.vector.ph: 1331 successors: %bb.2(0x80000000) 1332 liveins: $r0, $r1, $r2, $r7, $lr 1333 1334 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1335 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1336 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1337 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1338 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1339 $lr = t2DoLoopStart renamable $r12 1340 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg 1341 1342 bb.2.vector.body: 1343 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1344 liveins: $r0, $r1, $r2, $r3 1345 1346 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 1347 MVE_VPST 8, implicit $vpr 1348 renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 1349 renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 1350 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1351 renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg 1352 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1353 early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 1354 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1355 renamable $lr = t2LoopDec killed renamable $lr, 1 1356 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1357 tB %bb.3, 14 /* CC::al */, $noreg 1358 1359 bb.3.exit: 1360 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1361 1362... 1363--- 1364name: illegal_vaddva_s32 1365alignment: 2 1366tracksRegLiveness: true 1367registers: [] 1368liveins: 1369 - { reg: '$r0', virtual-reg: '' } 1370 - { reg: '$r1', virtual-reg: '' } 1371frameInfo: 1372 stackSize: 8 1373 offsetAdjustment: 0 1374 maxAlignment: 4 1375 stackProtector: '' 1376 maxCallFrameSize: 0 1377 cvBytesOfCalleeSavedRegisters: 0 1378 localFrameSize: 0 1379 savePoint: '' 1380 restorePoint: '' 1381fixedStack: [] 1382stack: 1383 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1384 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1385 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1386 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1387 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1388 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1389callSites: [] 1390constants: [] 1391machineFunctionInfo: {} 1392body: | 1393 ; CHECK-LABEL: name: illegal_vaddva_s32 1394 ; CHECK: bb.0.entry: 1395 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) 1396 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r7 1397 ; CHECK-NEXT: {{ $}} 1398 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1399 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1400 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 1401 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 1402 ; CHECK-NEXT: tCBZ $r1, %bb.4 1403 ; CHECK-NEXT: {{ $}} 1404 ; CHECK-NEXT: bb.1.vector.ph: 1405 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1406 ; CHECK-NEXT: liveins: $r0, $r1 1407 ; CHECK-NEXT: {{ $}} 1408 ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 1409 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1410 ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 1411 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1412 ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 1413 ; CHECK-NEXT: dead $lr = t2DLS renamable $r2 1414 ; CHECK-NEXT: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1415 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1416 ; CHECK-NEXT: {{ $}} 1417 ; CHECK-NEXT: bb.2.vector.body: 1418 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1419 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 1420 ; CHECK-NEXT: {{ $}} 1421 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg 1422 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 1423 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 1424 ; CHECK-NEXT: $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1425 ; CHECK-NEXT: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 1426 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1427 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 1428 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg 1429 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 1430 ; CHECK-NEXT: {{ $}} 1431 ; CHECK-NEXT: bb.3.exit: 1432 ; CHECK-NEXT: liveins: $r2 1433 ; CHECK-NEXT: {{ $}} 1434 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1435 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1436 ; CHECK-NEXT: {{ $}} 1437 ; CHECK-NEXT: bb.4: 1438 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1439 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1440 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1441 bb.0.entry: 1442 successors: %bb.4(0x30000000), %bb.1(0x50000000) 1443 liveins: $r0, $r1, $r7, $lr 1444 1445 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1446 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1447 frame-setup CFI_INSTRUCTION offset $lr, -4 1448 frame-setup CFI_INSTRUCTION offset $r7, -8 1449 tCBZ $r1, %bb.4 1450 1451 bb.1.vector.ph: 1452 successors: %bb.2(0x80000000) 1453 liveins: $r0, $r1 1454 1455 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 1456 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1457 renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 1458 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1459 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 1460 $lr = t2DoLoopStart renamable $r2 1461 $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1462 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1463 1464 bb.2.vector.body: 1465 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1466 liveins: $r0, $r1, $r2, $r3 1467 1468 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg 1469 MVE_VPST 8, implicit $vpr 1470 renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 1471 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1472 renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 1473 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1474 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 1475 renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg 1476 renamable $lr = t2LoopDec killed renamable $lr, 1 1477 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1478 tB %bb.3, 14 /* CC::al */, $noreg 1479 1480 bb.3.exit: 1481 liveins: $r2 1482 1483 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1484 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1485 1486 bb.4: 1487 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1488 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1489 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1490 1491... 1492--- 1493name: illegal_vaddv_u32 1494alignment: 2 1495tracksRegLiveness: true 1496registers: [] 1497liveins: 1498 - { reg: '$r0', virtual-reg: '' } 1499 - { reg: '$r1', virtual-reg: '' } 1500 - { reg: '$r2', virtual-reg: '' } 1501frameInfo: 1502 stackSize: 8 1503 offsetAdjustment: 0 1504 maxAlignment: 4 1505 stackProtector: '' 1506 maxCallFrameSize: 0 1507 cvBytesOfCalleeSavedRegisters: 0 1508 localFrameSize: 0 1509 savePoint: '' 1510 restorePoint: '' 1511fixedStack: [] 1512stack: 1513 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1514 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1515 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1516 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1517 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1518 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1519callSites: [] 1520constants: [] 1521machineFunctionInfo: {} 1522body: | 1523 ; CHECK-LABEL: name: illegal_vaddv_u32 1524 ; CHECK: bb.0.entry: 1525 ; CHECK-NEXT: successors: %bb.1(0x80000000) 1526 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 1527 ; CHECK-NEXT: {{ $}} 1528 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1529 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1530 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 1531 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 1532 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1533 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 1534 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1535 ; CHECK-NEXT: {{ $}} 1536 ; CHECK-NEXT: bb.1.vector.ph: 1537 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1538 ; CHECK-NEXT: liveins: $r0, $r1, $r2 1539 ; CHECK-NEXT: {{ $}} 1540 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1541 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1542 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1543 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1544 ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1545 ; CHECK-NEXT: dead $lr = t2DLS renamable $r12 1546 ; CHECK-NEXT: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg 1547 ; CHECK-NEXT: {{ $}} 1548 ; CHECK-NEXT: bb.2.vector.body: 1549 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1550 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 1551 ; CHECK-NEXT: {{ $}} 1552 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 1553 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 1554 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 1555 ; CHECK-NEXT: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 1556 ; CHECK-NEXT: $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1557 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg 1558 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1559 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 1560 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1561 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 1562 ; CHECK-NEXT: {{ $}} 1563 ; CHECK-NEXT: bb.3.exit: 1564 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1565 bb.0.entry: 1566 successors: %bb.1(0x80000000) 1567 liveins: $r0, $r1, $r2, $r7, $lr 1568 1569 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1570 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1571 frame-setup CFI_INSTRUCTION offset $lr, -4 1572 frame-setup CFI_INSTRUCTION offset $r7, -8 1573 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1574 t2IT 0, 8, implicit-def $itstate 1575 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1576 1577 bb.1.vector.ph: 1578 successors: %bb.2(0x80000000) 1579 liveins: $r0, $r1, $r2, $r7, $lr 1580 1581 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1582 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1583 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1584 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1585 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1586 $lr = t2DoLoopStart renamable $r12 1587 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg 1588 1589 bb.2.vector.body: 1590 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1591 liveins: $r0, $r1, $r2, $r3 1592 1593 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 1594 MVE_VPST 8, implicit $vpr 1595 renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 1596 renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 1597 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1598 renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg 1599 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1600 early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 1601 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1602 renamable $lr = t2LoopDec killed renamable $lr, 1 1603 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1604 tB %bb.3, 14 /* CC::al */, $noreg 1605 1606 bb.3.exit: 1607 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1608 1609... 1610--- 1611name: illegal_vaddva_u32 1612alignment: 2 1613tracksRegLiveness: true 1614registers: [] 1615liveins: 1616 - { reg: '$r0', virtual-reg: '' } 1617 - { reg: '$r1', virtual-reg: '' } 1618frameInfo: 1619 stackSize: 8 1620 offsetAdjustment: 0 1621 maxAlignment: 4 1622 stackProtector: '' 1623 maxCallFrameSize: 0 1624 cvBytesOfCalleeSavedRegisters: 0 1625 localFrameSize: 0 1626 savePoint: '' 1627 restorePoint: '' 1628fixedStack: [] 1629stack: 1630 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1631 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1632 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1633 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1634 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1635 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1636callSites: [] 1637constants: [] 1638machineFunctionInfo: {} 1639body: | 1640 ; CHECK-LABEL: name: illegal_vaddva_u32 1641 ; CHECK: bb.0.entry: 1642 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) 1643 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r7 1644 ; CHECK-NEXT: {{ $}} 1645 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1646 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1647 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 1648 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 1649 ; CHECK-NEXT: tCBZ $r1, %bb.4 1650 ; CHECK-NEXT: {{ $}} 1651 ; CHECK-NEXT: bb.1.vector.ph: 1652 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1653 ; CHECK-NEXT: liveins: $r0, $r1 1654 ; CHECK-NEXT: {{ $}} 1655 ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 1656 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1657 ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 1658 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1659 ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 1660 ; CHECK-NEXT: dead $lr = t2DLS renamable $r2 1661 ; CHECK-NEXT: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1662 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1663 ; CHECK-NEXT: {{ $}} 1664 ; CHECK-NEXT: bb.2.vector.body: 1665 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1666 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 1667 ; CHECK-NEXT: {{ $}} 1668 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg 1669 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 1670 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 1671 ; CHECK-NEXT: $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1672 ; CHECK-NEXT: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 1673 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1674 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 1675 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg 1676 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 1677 ; CHECK-NEXT: {{ $}} 1678 ; CHECK-NEXT: bb.3.exit: 1679 ; CHECK-NEXT: liveins: $r2 1680 ; CHECK-NEXT: {{ $}} 1681 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1682 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1683 ; CHECK-NEXT: {{ $}} 1684 ; CHECK-NEXT: bb.4: 1685 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1686 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1687 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1688 bb.0.entry: 1689 successors: %bb.4(0x30000000), %bb.1(0x50000000) 1690 liveins: $r0, $r1, $r7, $lr 1691 1692 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1693 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1694 frame-setup CFI_INSTRUCTION offset $lr, -4 1695 frame-setup CFI_INSTRUCTION offset $r7, -8 1696 tCBZ $r1, %bb.4 1697 1698 bb.1.vector.ph: 1699 successors: %bb.2(0x80000000) 1700 liveins: $r0, $r1 1701 1702 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 1703 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1704 renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 1705 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1706 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 1707 $lr = t2DoLoopStart renamable $r2 1708 $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1709 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1710 1711 bb.2.vector.body: 1712 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1713 liveins: $r0, $r1, $r2, $r3 1714 1715 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg 1716 MVE_VPST 8, implicit $vpr 1717 renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 1718 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 1719 renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 1720 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 1721 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 1722 renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg 1723 renamable $lr = t2LoopDec killed renamable $lr, 1 1724 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1725 tB %bb.3, 14 /* CC::al */, $noreg 1726 1727 bb.3.exit: 1728 liveins: $r2 1729 1730 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1731 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1732 1733 bb.4: 1734 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1735 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1736 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 1737 1738... 1739--- 1740name: illegal_vaddv_s16 1741alignment: 2 1742tracksRegLiveness: true 1743registers: [] 1744liveins: 1745 - { reg: '$r0', virtual-reg: '' } 1746 - { reg: '$r1', virtual-reg: '' } 1747 - { reg: '$r2', virtual-reg: '' } 1748frameInfo: 1749 stackSize: 8 1750 offsetAdjustment: 0 1751 maxAlignment: 8 1752 stackProtector: '' 1753 maxCallFrameSize: 0 1754 cvBytesOfCalleeSavedRegisters: 0 1755 localFrameSize: 0 1756 savePoint: '' 1757 restorePoint: '' 1758fixedStack: 1759 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, 1760 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 1761 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1762stack: 1763 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1764 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1765 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1766 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1767 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 1768 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1769callSites: [] 1770constants: [] 1771machineFunctionInfo: {} 1772body: | 1773 ; CHECK-LABEL: name: illegal_vaddv_s16 1774 ; CHECK: bb.0.entry: 1775 ; CHECK-NEXT: successors: %bb.1(0x80000000) 1776 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4 1777 ; CHECK-NEXT: {{ $}} 1778 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 1779 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1780 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 1781 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 1782 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1783 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 1784 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 1785 ; CHECK-NEXT: {{ $}} 1786 ; CHECK-NEXT: bb.1.vector.ph: 1787 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1788 ; CHECK-NEXT: liveins: $r0, $r1, $r2 1789 ; CHECK-NEXT: {{ $}} 1790 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1791 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1792 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1793 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1794 ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1795 ; CHECK-NEXT: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 1796 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) 1797 ; CHECK-NEXT: dead $lr = t2DLS renamable $r12 1798 ; CHECK-NEXT: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg 1799 ; CHECK-NEXT: {{ $}} 1800 ; CHECK-NEXT: bb.2.vector.body: 1801 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1802 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r4 1803 ; CHECK-NEXT: {{ $}} 1804 ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg 1805 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 1806 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 1) 1807 ; CHECK-NEXT: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 1808 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 1809 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg 1810 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 1811 ; CHECK-NEXT: renamable $r3 = t2SXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg 1812 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg 1813 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 1814 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 1815 ; CHECK-NEXT: {{ $}} 1816 ; CHECK-NEXT: bb.3.exit: 1817 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 1818 1819 bb.0.entry: 1820 successors: %bb.1(0x80000000) 1821 liveins: $r0, $r1, $r2, $r4, $lr 1822 1823 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 1824 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1825 frame-setup CFI_INSTRUCTION offset $lr, -4 1826 frame-setup CFI_INSTRUCTION offset $r4, -8 1827 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1828 t2IT 0, 8, implicit-def $itstate 1829 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 1830 1831 bb.1.vector.ph: 1832 successors: %bb.2(0x80000000) 1833 liveins: $r0, $r1, $r2, $r4, $lr 1834 1835 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1836 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1837 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1838 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1839 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1840 renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 1841 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) 1842 $lr = t2DoLoopStart renamable $r12 1843 $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg 1844 1845 bb.2.vector.body: 1846 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1847 liveins: $q0, $r0, $r1, $r2, $r4 1848 1849 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg 1850 MVE_VPST 8, implicit $vpr 1851 renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 1) 1852 renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 1853 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 1854 renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg 1855 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 1856 renamable $r3 = t2SXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg 1857 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg 1858 early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 1859 renamable $lr = t2LoopDec killed renamable $lr, 1 1860 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1861 tB %bb.3, 14 /* CC::al */, $noreg 1862 1863 bb.3.exit: 1864 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 1865 1866... 1867--- 1868name: illegal_vaddva_s16 1869alignment: 2 1870tracksRegLiveness: true 1871registers: [] 1872liveins: 1873 - { reg: '$r0', virtual-reg: '' } 1874 - { reg: '$r1', virtual-reg: '' } 1875 - { reg: '$r2', virtual-reg: '' } 1876 - { reg: '$r3', virtual-reg: '' } 1877frameInfo: 1878 stackSize: 8 1879 offsetAdjustment: 0 1880 maxAlignment: 8 1881 stackProtector: '' 1882 maxCallFrameSize: 0 1883 cvBytesOfCalleeSavedRegisters: 0 1884 localFrameSize: 0 1885 savePoint: '' 1886 restorePoint: '' 1887fixedStack: 1888 - { id: 0, type: default, offset: 0, size: 8, alignment: 8, stack-id: default, 1889 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 1890 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1891stack: 1892 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1893 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1894 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1895 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1896 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 1897 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1898callSites: [] 1899constants: [] 1900machineFunctionInfo: {} 1901body: | 1902 ; CHECK-LABEL: name: illegal_vaddva_s16 1903 ; CHECK: bb.0.entry: 1904 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) 1905 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 1906 ; CHECK-NEXT: {{ $}} 1907 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 1908 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1909 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 1910 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 1911 ; CHECK-NEXT: tCBZ $r1, %bb.4 1912 ; CHECK-NEXT: {{ $}} 1913 ; CHECK-NEXT: bb.1.vector.ph: 1914 ; CHECK-NEXT: successors: %bb.2(0x80000000) 1915 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 1916 ; CHECK-NEXT: {{ $}} 1917 ; CHECK-NEXT: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 1918 ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 1919 ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 1920 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1921 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1922 ; CHECK-NEXT: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) 1923 ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 1924 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1925 ; CHECK-NEXT: dead $lr = t2DLS renamable $r2 1926 ; CHECK-NEXT: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1927 ; CHECK-NEXT: {{ $}} 1928 ; CHECK-NEXT: bb.2.vector.body: 1929 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1930 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r3, $r4 1931 ; CHECK-NEXT: {{ $}} 1932 ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg, $noreg 1933 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 1934 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 1) 1935 ; CHECK-NEXT: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 1936 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 1937 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg 1938 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 1939 ; CHECK-NEXT: renamable $r3 = t2SXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg 1940 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg 1941 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 1942 ; CHECK-NEXT: {{ $}} 1943 ; CHECK-NEXT: bb.3.exit: 1944 ; CHECK-NEXT: liveins: $r3 1945 ; CHECK-NEXT: {{ $}} 1946 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 1947 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 1948 ; CHECK-NEXT: {{ $}} 1949 ; CHECK-NEXT: bb.4: 1950 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1951 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 1952 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 1953 bb.0.entry: 1954 successors: %bb.4(0x30000000), %bb.1(0x50000000) 1955 liveins: $r0, $r1, $r2, $r3, $r4, $lr 1956 1957 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 1958 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1959 frame-setup CFI_INSTRUCTION offset $lr, -4 1960 frame-setup CFI_INSTRUCTION offset $r4, -8 1961 tCBZ $r1, %bb.4 1962 1963 bb.1.vector.ph: 1964 successors: %bb.2(0x80000000) 1965 liveins: $r0, $r1, $r2, $r3 1966 1967 renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 1968 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 1969 renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 1970 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1971 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1972 renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) 1973 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 1974 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 1975 $lr = t2DoLoopStart renamable $r2 1976 $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg 1977 1978 bb.2.vector.body: 1979 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1980 liveins: $q0, $r0, $r1, $r3, $r4 1981 1982 renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg, $noreg 1983 MVE_VPST 8, implicit $vpr 1984 renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 1) 1985 renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 1986 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 1987 renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg 1988 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 1989 renamable $r3 = t2SXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg 1990 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg 1991 renamable $lr = t2LoopDec killed renamable $lr, 1 1992 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1993 tB %bb.3, 14 /* CC::al */, $noreg 1994 1995 bb.3.exit: 1996 liveins: $r3 1997 1998 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 1999 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2000 2001 bb.4: 2002 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2003 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2004 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2005 2006... 2007--- 2008name: illegal_vaddv_u16 2009alignment: 2 2010tracksRegLiveness: true 2011registers: [] 2012liveins: 2013 - { reg: '$r0', virtual-reg: '' } 2014 - { reg: '$r1', virtual-reg: '' } 2015 - { reg: '$r2', virtual-reg: '' } 2016frameInfo: 2017 stackSize: 8 2018 offsetAdjustment: 0 2019 maxAlignment: 8 2020 stackProtector: '' 2021 maxCallFrameSize: 0 2022 cvBytesOfCalleeSavedRegisters: 0 2023 localFrameSize: 0 2024 savePoint: '' 2025 restorePoint: '' 2026fixedStack: 2027 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, 2028 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 2029 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2030stack: 2031 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 2032 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 2033 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2034 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 2035 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 2036 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2037callSites: [] 2038constants: [] 2039machineFunctionInfo: {} 2040body: | 2041 ; CHECK-LABEL: name: illegal_vaddv_u16 2042 ; CHECK: bb.0.entry: 2043 ; CHECK-NEXT: successors: %bb.1(0x80000000) 2044 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4 2045 ; CHECK-NEXT: {{ $}} 2046 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2047 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 2048 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 2049 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 2050 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 2051 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 2052 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 2053 ; CHECK-NEXT: {{ $}} 2054 ; CHECK-NEXT: bb.1.vector.ph: 2055 ; CHECK-NEXT: successors: %bb.2(0x80000000) 2056 ; CHECK-NEXT: liveins: $r0, $r1, $r2 2057 ; CHECK-NEXT: {{ $}} 2058 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 2059 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 2060 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 2061 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2062 ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 2063 ; CHECK-NEXT: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 2064 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) 2065 ; CHECK-NEXT: dead $lr = t2DLS renamable $r12 2066 ; CHECK-NEXT: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2067 ; CHECK-NEXT: {{ $}} 2068 ; CHECK-NEXT: bb.2.vector.body: 2069 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2070 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r4 2071 ; CHECK-NEXT: {{ $}} 2072 ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg 2073 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 2074 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2) 2075 ; CHECK-NEXT: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 2076 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2077 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg 2078 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2079 ; CHECK-NEXT: renamable $r3 = t2UXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg 2080 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg 2081 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 2082 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 2083 ; CHECK-NEXT: {{ $}} 2084 ; CHECK-NEXT: bb.3.exit: 2085 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 2086 bb.0.entry: 2087 successors: %bb.1(0x80000000) 2088 liveins: $r0, $r1, $r2, $r4, $lr 2089 2090 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2091 frame-setup CFI_INSTRUCTION def_cfa_offset 8 2092 frame-setup CFI_INSTRUCTION offset $lr, -4 2093 frame-setup CFI_INSTRUCTION offset $r4, -8 2094 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 2095 t2IT 0, 8, implicit-def $itstate 2096 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 2097 2098 bb.1.vector.ph: 2099 successors: %bb.2(0x80000000) 2100 liveins: $r0, $r1, $r2, $r4, $lr 2101 2102 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 2103 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 2104 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 2105 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2106 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 2107 renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 2108 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) 2109 $lr = t2DoLoopStart renamable $r12 2110 $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2111 2112 bb.2.vector.body: 2113 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2114 liveins: $q0, $r0, $r1, $r2, $r4 2115 2116 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg 2117 MVE_VPST 8, implicit $vpr 2118 renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2) 2119 renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 2120 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2121 renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg 2122 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2123 renamable $r3 = t2UXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg 2124 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg 2125 early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 2126 renamable $lr = t2LoopDec killed renamable $lr, 1 2127 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 2128 tB %bb.3, 14 /* CC::al */, $noreg 2129 2130 bb.3.exit: 2131 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 2132 2133... 2134--- 2135name: illegal_vaddva_u16 2136alignment: 2 2137tracksRegLiveness: true 2138registers: [] 2139liveins: 2140 - { reg: '$r0', virtual-reg: '' } 2141 - { reg: '$r1', virtual-reg: '' } 2142 - { reg: '$r2', virtual-reg: '' } 2143 - { reg: '$r3', virtual-reg: '' } 2144frameInfo: 2145 stackSize: 8 2146 offsetAdjustment: 0 2147 maxAlignment: 8 2148 stackProtector: '' 2149 maxCallFrameSize: 0 2150 cvBytesOfCalleeSavedRegisters: 0 2151 localFrameSize: 0 2152 savePoint: '' 2153 restorePoint: '' 2154fixedStack: 2155 - { id: 0, type: default, offset: 0, size: 8, alignment: 8, stack-id: default, 2156 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 2157 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2158stack: 2159 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 2160 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 2161 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2162 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 2163 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 2164 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2165callSites: [] 2166constants: [] 2167machineFunctionInfo: {} 2168body: | 2169 ; CHECK-LABEL: name: illegal_vaddva_u16 2170 ; CHECK: bb.0.entry: 2171 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) 2172 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 2173 ; CHECK-NEXT: {{ $}} 2174 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2175 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 2176 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 2177 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 2178 ; CHECK-NEXT: tCBZ $r1, %bb.4 2179 ; CHECK-NEXT: {{ $}} 2180 ; CHECK-NEXT: bb.1.vector.ph: 2181 ; CHECK-NEXT: successors: %bb.2(0x80000000) 2182 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 2183 ; CHECK-NEXT: {{ $}} 2184 ; CHECK-NEXT: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 2185 ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 2186 ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 2187 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2188 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 2189 ; CHECK-NEXT: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) 2190 ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 2191 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2192 ; CHECK-NEXT: dead $lr = t2DLS renamable $r2 2193 ; CHECK-NEXT: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg 2194 ; CHECK-NEXT: {{ $}} 2195 ; CHECK-NEXT: bb.2.vector.body: 2196 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2197 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r3, $r4 2198 ; CHECK-NEXT: {{ $}} 2199 ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg, $noreg 2200 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 2201 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2) 2202 ; CHECK-NEXT: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 2203 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2204 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg 2205 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2206 ; CHECK-NEXT: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg 2207 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg 2208 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 2209 ; CHECK-NEXT: {{ $}} 2210 ; CHECK-NEXT: bb.3.exit: 2211 ; CHECK-NEXT: liveins: $r3 2212 ; CHECK-NEXT: {{ $}} 2213 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2214 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2215 ; CHECK-NEXT: {{ $}} 2216 ; CHECK-NEXT: bb.4: 2217 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2218 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2219 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2220 bb.0.entry: 2221 successors: %bb.4(0x30000000), %bb.1(0x50000000) 2222 liveins: $r0, $r1, $r2, $r3, $r4, $lr 2223 2224 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2225 frame-setup CFI_INSTRUCTION def_cfa_offset 8 2226 frame-setup CFI_INSTRUCTION offset $lr, -4 2227 frame-setup CFI_INSTRUCTION offset $r4, -8 2228 tCBZ $r1, %bb.4 2229 2230 bb.1.vector.ph: 2231 successors: %bb.2(0x80000000) 2232 liveins: $r0, $r1, $r2, $r3 2233 2234 renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 2235 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 2236 renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 2237 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2238 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 2239 renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) 2240 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 2241 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2242 $lr = t2DoLoopStart renamable $r2 2243 $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg 2244 2245 bb.2.vector.body: 2246 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2247 liveins: $q0, $r0, $r1, $r3, $r4 2248 2249 renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg, $noreg 2250 MVE_VPST 8, implicit $vpr 2251 renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2) 2252 renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 2253 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2254 renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg 2255 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2256 renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg 2257 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg 2258 renamable $lr = t2LoopDec killed renamable $lr, 1 2259 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 2260 tB %bb.3, 14 /* CC::al */, $noreg 2261 2262 bb.3.exit: 2263 liveins: $r3 2264 2265 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2266 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2267 2268 bb.4: 2269 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2270 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2271 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2272 2273... 2274--- 2275name: illegal_vaddv_s8 2276alignment: 2 2277tracksRegLiveness: true 2278registers: [] 2279liveins: 2280 - { reg: '$r0', virtual-reg: '' } 2281 - { reg: '$r1', virtual-reg: '' } 2282 - { reg: '$r2', virtual-reg: '' } 2283frameInfo: 2284 stackSize: 8 2285 offsetAdjustment: 0 2286 maxAlignment: 8 2287 stackProtector: '' 2288 maxCallFrameSize: 0 2289 cvBytesOfCalleeSavedRegisters: 0 2290 localFrameSize: 0 2291 savePoint: '' 2292 restorePoint: '' 2293fixedStack: 2294 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, 2295 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 2296 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2297stack: 2298 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 2299 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 2300 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2301 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 2302 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 2303 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2304callSites: [] 2305constants: [] 2306machineFunctionInfo: {} 2307body: | 2308 ; CHECK-LABEL: name: illegal_vaddv_s8 2309 ; CHECK: bb.0.entry: 2310 ; CHECK-NEXT: successors: %bb.1(0x80000000) 2311 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4 2312 ; CHECK-NEXT: {{ $}} 2313 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2314 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 2315 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 2316 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 2317 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 2318 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 2319 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 2320 ; CHECK-NEXT: {{ $}} 2321 ; CHECK-NEXT: bb.1.vector.ph: 2322 ; CHECK-NEXT: successors: %bb.2(0x80000000) 2323 ; CHECK-NEXT: liveins: $r0, $r1, $r2 2324 ; CHECK-NEXT: {{ $}} 2325 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg 2326 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2327 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2328 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2329 ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 2330 ; CHECK-NEXT: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 2331 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) 2332 ; CHECK-NEXT: dead $lr = t2DLS renamable $r12 2333 ; CHECK-NEXT: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2334 ; CHECK-NEXT: {{ $}} 2335 ; CHECK-NEXT: bb.2.vector.body: 2336 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2337 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r4 2338 ; CHECK-NEXT: {{ $}} 2339 ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 2340 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 2341 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) 2342 ; CHECK-NEXT: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 2343 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2344 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg 2345 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2346 ; CHECK-NEXT: renamable $r3 = t2SXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg 2347 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 2348 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 2349 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 2350 ; CHECK-NEXT: {{ $}} 2351 ; CHECK-NEXT: bb.3.exit: 2352 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 2353 bb.0.entry: 2354 successors: %bb.1(0x80000000) 2355 liveins: $r0, $r1, $r2, $r4, $lr 2356 2357 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2358 frame-setup CFI_INSTRUCTION def_cfa_offset 8 2359 frame-setup CFI_INSTRUCTION offset $lr, -4 2360 frame-setup CFI_INSTRUCTION offset $r4, -8 2361 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 2362 t2IT 0, 8, implicit-def $itstate 2363 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 2364 2365 bb.1.vector.ph: 2366 successors: %bb.2(0x80000000) 2367 liveins: $r0, $r1, $r2, $r4, $lr 2368 2369 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg 2370 renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2371 renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2372 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2373 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 2374 renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 2375 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) 2376 $lr = t2DoLoopStart renamable $r12 2377 $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2378 2379 bb.2.vector.body: 2380 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2381 liveins: $q0, $r0, $r1, $r2, $r4 2382 2383 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 2384 MVE_VPST 8, implicit $vpr 2385 renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) 2386 renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 2387 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2388 renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg 2389 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2390 renamable $r3 = t2SXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg 2391 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 2392 early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 2393 renamable $lr = t2LoopDec killed renamable $lr, 1 2394 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 2395 tB %bb.3, 14 /* CC::al */, $noreg 2396 2397 bb.3.exit: 2398 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 2399 2400... 2401--- 2402name: illegal_vaddva_s8 2403alignment: 2 2404tracksRegLiveness: true 2405registers: [] 2406liveins: 2407 - { reg: '$r0', virtual-reg: '' } 2408 - { reg: '$r1', virtual-reg: '' } 2409 - { reg: '$r2', virtual-reg: '' } 2410 - { reg: '$r3', virtual-reg: '' } 2411frameInfo: 2412 stackSize: 8 2413 offsetAdjustment: 0 2414 maxAlignment: 8 2415 stackProtector: '' 2416 maxCallFrameSize: 0 2417 cvBytesOfCalleeSavedRegisters: 0 2418 localFrameSize: 0 2419 savePoint: '' 2420 restorePoint: '' 2421fixedStack: 2422 - { id: 0, type: default, offset: 0, size: 8, alignment: 8, stack-id: default, 2423 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 2424 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2425stack: 2426 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 2427 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 2428 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2429 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 2430 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 2431 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2432callSites: [] 2433constants: [] 2434machineFunctionInfo: {} 2435body: | 2436 ; CHECK-LABEL: name: illegal_vaddva_s8 2437 ; CHECK: bb.0.entry: 2438 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) 2439 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 2440 ; CHECK-NEXT: {{ $}} 2441 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2442 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 2443 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 2444 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 2445 ; CHECK-NEXT: tCBZ $r1, %bb.4 2446 ; CHECK-NEXT: {{ $}} 2447 ; CHECK-NEXT: bb.1.vector.ph: 2448 ; CHECK-NEXT: successors: %bb.2(0x80000000) 2449 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 2450 ; CHECK-NEXT: {{ $}} 2451 ; CHECK-NEXT: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 2452 ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg 2453 ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg 2454 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2455 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg 2456 ; CHECK-NEXT: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) 2457 ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg 2458 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2459 ; CHECK-NEXT: dead $lr = t2DLS renamable $r2 2460 ; CHECK-NEXT: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg 2461 ; CHECK-NEXT: {{ $}} 2462 ; CHECK-NEXT: bb.2.vector.body: 2463 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2464 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r3, $r4 2465 ; CHECK-NEXT: {{ $}} 2466 ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg, $noreg 2467 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 2468 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) 2469 ; CHECK-NEXT: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 2470 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2471 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg 2472 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2473 ; CHECK-NEXT: renamable $r3 = t2SXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg 2474 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg 2475 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 2476 ; CHECK-NEXT: {{ $}} 2477 ; CHECK-NEXT: bb.3.exit: 2478 ; CHECK-NEXT: liveins: $r3 2479 ; CHECK-NEXT: {{ $}} 2480 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2481 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2482 ; CHECK-NEXT: {{ $}} 2483 ; CHECK-NEXT: bb.4: 2484 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2485 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2486 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2487 bb.0.entry: 2488 successors: %bb.4(0x30000000), %bb.1(0x50000000) 2489 liveins: $r0, $r1, $r2, $r3, $r4, $lr 2490 2491 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2492 frame-setup CFI_INSTRUCTION def_cfa_offset 8 2493 frame-setup CFI_INSTRUCTION offset $lr, -4 2494 frame-setup CFI_INSTRUCTION offset $r4, -8 2495 tCBZ $r1, %bb.4 2496 2497 bb.1.vector.ph: 2498 successors: %bb.2(0x80000000) 2499 liveins: $r0, $r1, $r2, $r3 2500 2501 renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 2502 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg 2503 renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg 2504 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2505 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg 2506 renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) 2507 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg 2508 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2509 $lr = t2DoLoopStart renamable $r2 2510 $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg 2511 2512 bb.2.vector.body: 2513 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2514 liveins: $q0, $r0, $r1, $r3, $r4 2515 2516 renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg, $noreg 2517 MVE_VPST 8, implicit $vpr 2518 renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) 2519 renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 2520 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2521 renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg 2522 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2523 renamable $r3 = t2SXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg 2524 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg 2525 renamable $lr = t2LoopDec killed renamable $lr, 1 2526 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 2527 tB %bb.3, 14 /* CC::al */, $noreg 2528 2529 bb.3.exit: 2530 liveins: $r3 2531 2532 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2533 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2534 2535 bb.4: 2536 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2537 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2538 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2539 2540... 2541--- 2542name: illegal_vaddv_u8 2543alignment: 2 2544tracksRegLiveness: true 2545registers: [] 2546liveins: 2547 - { reg: '$r0', virtual-reg: '' } 2548 - { reg: '$r1', virtual-reg: '' } 2549 - { reg: '$r2', virtual-reg: '' } 2550frameInfo: 2551 stackSize: 8 2552 offsetAdjustment: 0 2553 maxAlignment: 8 2554 stackProtector: '' 2555 maxCallFrameSize: 0 2556 cvBytesOfCalleeSavedRegisters: 0 2557 localFrameSize: 0 2558 savePoint: '' 2559 restorePoint: '' 2560fixedStack: 2561 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, 2562 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 2563 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2564stack: 2565 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 2566 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 2567 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2568 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 2569 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 2570 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2571callSites: [] 2572constants: [] 2573machineFunctionInfo: {} 2574body: | 2575 ; CHECK-LABEL: name: illegal_vaddv_u8 2576 ; CHECK: bb.0.entry: 2577 ; CHECK-NEXT: successors: %bb.1(0x80000000) 2578 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4 2579 ; CHECK-NEXT: {{ $}} 2580 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2581 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 2582 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 2583 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 2584 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 2585 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 2586 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 2587 ; CHECK-NEXT: {{ $}} 2588 ; CHECK-NEXT: bb.1.vector.ph: 2589 ; CHECK-NEXT: successors: %bb.2(0x80000000) 2590 ; CHECK-NEXT: liveins: $r0, $r1, $r2 2591 ; CHECK-NEXT: {{ $}} 2592 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg 2593 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2594 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2595 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2596 ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 2597 ; CHECK-NEXT: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 2598 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) 2599 ; CHECK-NEXT: dead $lr = t2DLS renamable $r12 2600 ; CHECK-NEXT: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2601 ; CHECK-NEXT: {{ $}} 2602 ; CHECK-NEXT: bb.2.vector.body: 2603 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2604 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r4 2605 ; CHECK-NEXT: {{ $}} 2606 ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 2607 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 2608 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) 2609 ; CHECK-NEXT: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 2610 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2611 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg 2612 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2613 ; CHECK-NEXT: renamable $r3 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg 2614 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 2615 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 2616 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 2617 ; CHECK-NEXT: {{ $}} 2618 ; CHECK-NEXT: bb.3.exit: 2619 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 2620 bb.0.entry: 2621 successors: %bb.1(0x80000000) 2622 liveins: $r0, $r1, $r2, $r4, $lr 2623 2624 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2625 frame-setup CFI_INSTRUCTION def_cfa_offset 8 2626 frame-setup CFI_INSTRUCTION offset $lr, -4 2627 frame-setup CFI_INSTRUCTION offset $r4, -8 2628 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 2629 t2IT 0, 8, implicit-def $itstate 2630 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 2631 2632 bb.1.vector.ph: 2633 successors: %bb.2(0x80000000) 2634 liveins: $r0, $r1, $r2, $r4, $lr 2635 2636 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg 2637 renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2638 renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 2639 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2640 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 2641 renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 2642 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) 2643 $lr = t2DoLoopStart renamable $r12 2644 $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2645 2646 bb.2.vector.body: 2647 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2648 liveins: $q0, $r0, $r1, $r2, $r4 2649 2650 renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg 2651 MVE_VPST 8, implicit $vpr 2652 renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) 2653 renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 2654 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2655 renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg 2656 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2657 renamable $r3 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg 2658 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg 2659 early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) 2660 renamable $lr = t2LoopDec killed renamable $lr, 1 2661 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 2662 tB %bb.3, 14 /* CC::al */, $noreg 2663 2664 bb.3.exit: 2665 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 2666 2667... 2668--- 2669name: illegal_vaddva_u8 2670alignment: 2 2671tracksRegLiveness: true 2672registers: [] 2673liveins: 2674 - { reg: '$r0', virtual-reg: '' } 2675 - { reg: '$r1', virtual-reg: '' } 2676 - { reg: '$r2', virtual-reg: '' } 2677 - { reg: '$r3', virtual-reg: '' } 2678frameInfo: 2679 stackSize: 8 2680 offsetAdjustment: 0 2681 maxAlignment: 8 2682 stackProtector: '' 2683 maxCallFrameSize: 0 2684 cvBytesOfCalleeSavedRegisters: 0 2685 localFrameSize: 0 2686 savePoint: '' 2687 restorePoint: '' 2688fixedStack: 2689 - { id: 0, type: default, offset: 0, size: 8, alignment: 8, stack-id: default, 2690 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 2691 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2692stack: 2693 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 2694 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 2695 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2696 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 2697 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 2698 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2699callSites: [] 2700constants: [] 2701machineFunctionInfo: {} 2702body: | 2703 ; CHECK-LABEL: name: illegal_vaddva_u8 2704 ; CHECK: bb.0.entry: 2705 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) 2706 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 2707 ; CHECK-NEXT: {{ $}} 2708 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2709 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 2710 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 2711 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 2712 ; CHECK-NEXT: tCBZ $r1, %bb.4 2713 ; CHECK-NEXT: {{ $}} 2714 ; CHECK-NEXT: bb.1.vector.ph: 2715 ; CHECK-NEXT: successors: %bb.2(0x80000000) 2716 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 2717 ; CHECK-NEXT: {{ $}} 2718 ; CHECK-NEXT: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 2719 ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg 2720 ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg 2721 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2722 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg 2723 ; CHECK-NEXT: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) 2724 ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg 2725 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2726 ; CHECK-NEXT: dead $lr = t2DLS renamable $r2 2727 ; CHECK-NEXT: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg 2728 ; CHECK-NEXT: {{ $}} 2729 ; CHECK-NEXT: bb.2.vector.body: 2730 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2731 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r3, $r4 2732 ; CHECK-NEXT: {{ $}} 2733 ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg, $noreg 2734 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 2735 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) 2736 ; CHECK-NEXT: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 2737 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2738 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg 2739 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2740 ; CHECK-NEXT: renamable $r3 = t2UXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg 2741 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg 2742 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 2743 ; CHECK-NEXT: {{ $}} 2744 ; CHECK-NEXT: bb.3.exit: 2745 ; CHECK-NEXT: liveins: $r3 2746 ; CHECK-NEXT: {{ $}} 2747 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2748 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2749 ; CHECK-NEXT: {{ $}} 2750 ; CHECK-NEXT: bb.4: 2751 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2752 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2753 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2754 bb.0.entry: 2755 successors: %bb.4(0x30000000), %bb.1(0x50000000) 2756 liveins: $r0, $r1, $r2, $r3, $r4, $lr 2757 2758 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 2759 frame-setup CFI_INSTRUCTION def_cfa_offset 8 2760 frame-setup CFI_INSTRUCTION offset $lr, -4 2761 frame-setup CFI_INSTRUCTION offset $r4, -8 2762 tCBZ $r1, %bb.4 2763 2764 bb.1.vector.ph: 2765 successors: %bb.2(0x80000000) 2766 liveins: $r0, $r1, $r2, $r3 2767 2768 renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 2769 renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg 2770 renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg 2771 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2772 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg 2773 renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) 2774 renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg 2775 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2776 $lr = t2DoLoopStart renamable $r2 2777 $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg 2778 2779 bb.2.vector.body: 2780 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2781 liveins: $q0, $r0, $r1, $r3, $r4 2782 2783 renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg, $noreg 2784 MVE_VPST 8, implicit $vpr 2785 renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) 2786 renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 2787 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 2788 renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg 2789 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 2790 renamable $r3 = t2UXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg 2791 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg 2792 renamable $lr = t2LoopDec killed renamable $lr, 1 2793 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 2794 tB %bb.3, 14 /* CC::al */, $noreg 2795 2796 bb.3.exit: 2797 liveins: $r3 2798 2799 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2800 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2801 2802 bb.4: 2803 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2804 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2805 tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 2806 2807... 2808--- 2809name: regalloc_legality_vaddva_u32 2810alignment: 2 2811tracksRegLiveness: true 2812registers: [] 2813liveins: 2814 - { reg: '$r0', virtual-reg: '' } 2815 - { reg: '$r1', virtual-reg: '' } 2816 - { reg: '$r2', virtual-reg: '' } 2817frameInfo: 2818 stackSize: 8 2819 offsetAdjustment: 0 2820 maxAlignment: 4 2821 stackProtector: '' 2822 maxCallFrameSize: 0 2823 cvBytesOfCalleeSavedRegisters: 0 2824 localFrameSize: 0 2825 savePoint: '' 2826 restorePoint: '' 2827fixedStack: [] 2828stack: 2829 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 2830 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 2831 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2832 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 2833 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 2834 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2835callSites: [] 2836constants: [] 2837machineFunctionInfo: {} 2838body: | 2839 ; CHECK-LABEL: name: regalloc_legality_vaddva_u32 2840 ; CHECK: bb.0.entry: 2841 ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.4(0x30000000) 2842 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 2843 ; CHECK-NEXT: {{ $}} 2844 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 2845 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 2846 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 2847 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 2848 ; CHECK-NEXT: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 2849 ; CHECK-NEXT: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr 2850 ; CHECK-NEXT: {{ $}} 2851 ; CHECK-NEXT: bb.1.while.body.preheader: 2852 ; CHECK-NEXT: successors: %bb.2(0x80000000) 2853 ; CHECK-NEXT: liveins: $r0, $r1, $r2 2854 ; CHECK-NEXT: {{ $}} 2855 ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 2856 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 2857 ; CHECK-NEXT: {{ $}} 2858 ; CHECK-NEXT: bb.2.while.body: 2859 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2860 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r12 2861 ; CHECK-NEXT: {{ $}} 2862 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.tmp3, align 2) 2863 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.tmp1, align 2) 2864 ; CHECK-NEXT: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 2865 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32acc killed renamable $r12, killed renamable $q0, 0, $noreg, $noreg 2866 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 2867 ; CHECK-NEXT: {{ $}} 2868 ; CHECK-NEXT: bb.3.while.end: 2869 ; CHECK-NEXT: liveins: $r12 2870 ; CHECK-NEXT: {{ $}} 2871 ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2872 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 2873 ; CHECK-NEXT: {{ $}} 2874 ; CHECK-NEXT: bb.4: 2875 ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 2876 ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2877 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 2878 bb.0.entry: 2879 successors: %bb.1(0x50000000), %bb.4(0x30000000) 2880 liveins: $r0, $r1, $r2, $r7, $lr 2881 2882 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 2883 frame-setup CFI_INSTRUCTION def_cfa_offset 8 2884 frame-setup CFI_INSTRUCTION offset $lr, -4 2885 frame-setup CFI_INSTRUCTION offset $r7, -8 2886 tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr 2887 $r3 = tMOVr $r2, 14 /* CC::al */, $noreg 2888 t2IT 10, 8, implicit-def $itstate 2889 renamable $r3 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate 2890 tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 2891 tBcc %bb.4, 11 /* CC::lt */, killed $cpsr 2892 2893 bb.1.while.body.preheader: 2894 successors: %bb.2(0x80000000) 2895 liveins: $r0, $r1, $r2, $r3 2896 2897 renamable $r3, dead $cpsr = tSUBrr renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg 2898 renamable $r12 = t2ADDri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 2899 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 2900 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 2901 renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 2902 $lr = t2DoLoopStart renamable $lr 2903 2904 bb.2.while.body: 2905 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2906 liveins: $lr, $r0, $r1, $r2, $r12 2907 2908 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 2909 MVE_VPST 4, implicit $vpr 2910 renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.tmp3, align 2) 2911 renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.tmp1, align 2) 2912 renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 2913 renamable $r2, dead $cpsr = nsw tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 2914 renamable $r12 = MVE_VADDVu32acc killed renamable $r12, killed renamable $q0, 0, $noreg, $noreg 2915 renamable $lr = t2LoopDec killed renamable $lr, 1 2916 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 2917 tB %bb.3, 14 /* CC::al */, $noreg 2918 2919 bb.3.while.end: 2920 liveins: $r12 2921 2922 $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2923 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 2924 2925 bb.4: 2926 renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 2927 $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg 2928 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 2929 2930... 2931--- 2932name: regalloc_legality_vaddv_u16 2933alignment: 2 2934tracksRegLiveness: true 2935registers: [] 2936liveins: 2937 - { reg: '$r0', virtual-reg: '' } 2938 - { reg: '$r1', virtual-reg: '' } 2939 - { reg: '$r2', virtual-reg: '' } 2940frameInfo: 2941 stackSize: 8 2942 offsetAdjustment: 0 2943 maxAlignment: 4 2944 stackProtector: '' 2945 maxCallFrameSize: 0 2946 cvBytesOfCalleeSavedRegisters: 0 2947 localFrameSize: 0 2948 savePoint: '' 2949 restorePoint: '' 2950fixedStack: [] 2951stack: 2952 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 2953 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 2954 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2955 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 2956 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 2957 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 2958callSites: [] 2959constants: [] 2960machineFunctionInfo: {} 2961body: | 2962 ; CHECK-LABEL: name: regalloc_legality_vaddv_u16 2963 ; CHECK: bb.0.entry: 2964 ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.4(0x30000000) 2965 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 2966 ; CHECK-NEXT: {{ $}} 2967 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 2968 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 2969 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 2970 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 2971 ; CHECK-NEXT: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 2972 ; CHECK-NEXT: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr 2973 ; CHECK-NEXT: {{ $}} 2974 ; CHECK-NEXT: bb.1.while.body.preheader: 2975 ; CHECK-NEXT: successors: %bb.2(0x80000000) 2976 ; CHECK-NEXT: liveins: $r0, $r1, $r2 2977 ; CHECK-NEXT: {{ $}} 2978 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 2979 ; CHECK-NEXT: $lr = MVE_DLSTP_16 killed renamable $r2 2980 ; CHECK-NEXT: {{ $}} 2981 ; CHECK-NEXT: bb.2.while.body: 2982 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 2983 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r3 2984 ; CHECK-NEXT: {{ $}} 2985 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.tmp3, align 2) 2986 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg, $noreg :: (load (s128) from %ir.tmp1, align 2) 2987 ; CHECK-NEXT: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 2988 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg 2989 ; CHECK-NEXT: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r12, 0, 14 /* CC::al */, $noreg 2990 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 2991 ; CHECK-NEXT: {{ $}} 2992 ; CHECK-NEXT: bb.3.while.end: 2993 ; CHECK-NEXT: liveins: $r3 2994 ; CHECK-NEXT: {{ $}} 2995 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 2996 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 2997 ; CHECK-NEXT: {{ $}} 2998 ; CHECK-NEXT: bb.4: 2999 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3000 ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 3001 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3002 bb.0.entry: 3003 successors: %bb.1(0x50000000), %bb.4(0x30000000) 3004 liveins: $r0, $r1, $r2, $r7, $lr 3005 3006 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 3007 frame-setup CFI_INSTRUCTION def_cfa_offset 8 3008 frame-setup CFI_INSTRUCTION offset $lr, -4 3009 frame-setup CFI_INSTRUCTION offset $r7, -8 3010 tCMPi8 renamable $r2, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr 3011 $r3 = tMOVr $r2, 14 /* CC::al */, $noreg 3012 t2IT 10, 8, implicit-def $itstate 3013 renamable $r3 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate 3014 tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 3015 tBcc %bb.4, 11 /* CC::lt */, killed $cpsr 3016 3017 bb.1.while.body.preheader: 3018 successors: %bb.2(0x80000000) 3019 liveins: $r0, $r1, $r2, $r3 3020 3021 renamable $r3, dead $cpsr = tSUBrr renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg 3022 renamable $r12 = t2ADDri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg 3023 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 3024 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 3025 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3026 $lr = t2DoLoopStart renamable $lr 3027 3028 bb.2.while.body: 3029 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 3030 liveins: $lr, $r0, $r1, $r2, $r3 3031 3032 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg 3033 MVE_VPST 4, implicit $vpr 3034 renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2) 3035 renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2) 3036 renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 3037 renamable $r2, dead $cpsr = nsw tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg 3038 renamable $r12 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg 3039 renamable $lr = t2LoopDec killed renamable $lr, 1 3040 renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r12, 0, 14 /* CC::al */, $noreg 3041 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 3042 tB %bb.3, 14 /* CC::al */, $noreg 3043 3044 bb.3.while.end: 3045 liveins: $r3 3046 3047 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 3048 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3049 3050 bb.4: 3051 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3052 $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg 3053 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3054 3055... 3056--- 3057name: regalloc_illegality_vaddva_s32 3058alignment: 2 3059tracksRegLiveness: true 3060registers: [] 3061liveins: 3062 - { reg: '$r0', virtual-reg: '' } 3063 - { reg: '$r1', virtual-reg: '' } 3064 - { reg: '$r3', virtual-reg: '' } 3065frameInfo: 3066 stackSize: 8 3067 offsetAdjustment: 0 3068 maxAlignment: 4 3069 stackProtector: '' 3070 maxCallFrameSize: 0 3071 cvBytesOfCalleeSavedRegisters: 0 3072 localFrameSize: 0 3073 savePoint: '' 3074 restorePoint: '' 3075fixedStack: [] 3076stack: 3077 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 3078 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 3079 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 3080 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 3081 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 3082 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 3083callSites: [] 3084constants: [] 3085machineFunctionInfo: {} 3086body: | 3087 ; CHECK-LABEL: name: regalloc_illegality_vaddva_s32 3088 ; CHECK: bb.0.entry: 3089 ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.4(0x30000000) 3090 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r3, $r7 3091 ; CHECK-NEXT: {{ $}} 3092 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 3093 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 3094 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 3095 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 3096 ; CHECK-NEXT: tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr 3097 ; CHECK-NEXT: $r2 = tMOVr $r3, 14 /* CC::al */, $noreg 3098 ; CHECK-NEXT: t2IT 10, 8, implicit-def $itstate 3099 ; CHECK-NEXT: renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate 3100 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 3101 ; CHECK-NEXT: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr 3102 ; CHECK-NEXT: {{ $}} 3103 ; CHECK-NEXT: bb.1.while.body.preheader: 3104 ; CHECK-NEXT: successors: %bb.2(0x80000000) 3105 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 3106 ; CHECK-NEXT: {{ $}} 3107 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg 3108 ; CHECK-NEXT: renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg 3109 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 3110 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 3111 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3112 ; CHECK-NEXT: {{ $}} 3113 ; CHECK-NEXT: bb.2.while.body: 3114 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 3115 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 3116 ; CHECK-NEXT: {{ $}} 3117 ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg 3118 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr 3119 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2) 3120 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2) 3121 ; CHECK-NEXT: renamable $q2 = MVE_VMULLBs16 renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q2 3122 ; CHECK-NEXT: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 3123 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q0 3124 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg 3125 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg 3126 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 3127 ; CHECK-NEXT: {{ $}} 3128 ; CHECK-NEXT: bb.3.while.end: 3129 ; CHECK-NEXT: liveins: $r2 3130 ; CHECK-NEXT: {{ $}} 3131 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3132 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3133 ; CHECK-NEXT: {{ $}} 3134 ; CHECK-NEXT: bb.4: 3135 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3136 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3137 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3138 bb.0.entry: 3139 successors: %bb.1(0x50000000), %bb.4(0x30000000) 3140 liveins: $r0, $r1, $r3, $r7, $lr 3141 3142 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 3143 frame-setup CFI_INSTRUCTION def_cfa_offset 8 3144 frame-setup CFI_INSTRUCTION offset $lr, -4 3145 frame-setup CFI_INSTRUCTION offset $r7, -8 3146 tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr 3147 $r2 = tMOVr $r3, 14 /* CC::al */, $noreg 3148 t2IT 10, 8, implicit-def $itstate 3149 renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate 3150 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 3151 tBcc %bb.4, 11 /* CC::lt */, killed $cpsr 3152 3153 bb.1.while.body.preheader: 3154 successors: %bb.2(0x80000000) 3155 liveins: $r0, $r1, $r2, $r3 3156 3157 renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg 3158 renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg 3159 renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 3160 renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 3161 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3162 $lr = t2DoLoopStart renamable $lr 3163 3164 bb.2.while.body: 3165 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 3166 liveins: $lr, $r0, $r1, $r2, $r3 3167 3168 renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg 3169 MVE_VPST 4, implicit $vpr 3170 renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2) 3171 renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2) 3172 renamable $q2 = MVE_VMULLBs16 renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q2 3173 renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 3174 renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q0 3175 renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg 3176 renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg 3177 renamable $lr = t2LoopDec killed renamable $lr, 1 3178 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 3179 tB %bb.3, 14 /* CC::al */, $noreg 3180 3181 bb.3.while.end: 3182 liveins: $r2 3183 3184 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3185 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3186 3187 bb.4: 3188 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3189 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3190 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3191 3192... 3193--- 3194name: illegal_vmull_non_zero 3195alignment: 2 3196tracksRegLiveness: true 3197registers: [] 3198liveins: 3199 - { reg: '$r0', virtual-reg: '' } 3200 - { reg: '$r1', virtual-reg: '' } 3201 - { reg: '$r3', virtual-reg: '' } 3202frameInfo: 3203 stackSize: 8 3204 offsetAdjustment: 0 3205 maxAlignment: 4 3206fixedStack: [] 3207stack: 3208 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 3209 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 3210 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 3211 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 3212 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 3213 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 3214callSites: [] 3215constants: [] 3216machineFunctionInfo: {} 3217body: | 3218 ; CHECK-LABEL: name: illegal_vmull_non_zero 3219 ; CHECK: bb.0.entry: 3220 ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.4(0x30000000) 3221 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r3, $r7 3222 ; CHECK-NEXT: {{ $}} 3223 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 3224 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 3225 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 3226 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 3227 ; CHECK-NEXT: tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr 3228 ; CHECK-NEXT: $r2 = tMOVr $r3, 14 /* CC::al */, $noreg 3229 ; CHECK-NEXT: t2IT 10, 8, implicit-def $itstate 3230 ; CHECK-NEXT: renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate 3231 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 3232 ; CHECK-NEXT: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr 3233 ; CHECK-NEXT: {{ $}} 3234 ; CHECK-NEXT: bb.1.while.body.preheader: 3235 ; CHECK-NEXT: successors: %bb.2(0x80000000) 3236 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 3237 ; CHECK-NEXT: {{ $}} 3238 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg 3239 ; CHECK-NEXT: renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg 3240 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 3241 ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 3242 ; CHECK-NEXT: dead $lr = t2DLS renamable $r2 3243 ; CHECK-NEXT: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3244 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3245 ; CHECK-NEXT: {{ $}} 3246 ; CHECK-NEXT: bb.2.while.body: 3247 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 3248 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12 3249 ; CHECK-NEXT: {{ $}} 3250 ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg 3251 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr 3252 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2) 3253 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2) 3254 ; CHECK-NEXT: $lr = tMOVr $r12, 14 /* CC::al */, $noreg 3255 ; CHECK-NEXT: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 3256 ; CHECK-NEXT: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg 3257 ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg 3258 ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg 3259 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 3260 ; CHECK-NEXT: {{ $}} 3261 ; CHECK-NEXT: bb.3.while.end: 3262 ; CHECK-NEXT: liveins: $r2 3263 ; CHECK-NEXT: {{ $}} 3264 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3265 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3266 ; CHECK-NEXT: {{ $}} 3267 ; CHECK-NEXT: bb.4: 3268 ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3269 ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3270 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3271 bb.0.entry: 3272 successors: %bb.1(0x50000000), %bb.4(0x30000000) 3273 liveins: $r0, $r1, $r3, $r7, $lr 3274 3275 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 3276 frame-setup CFI_INSTRUCTION def_cfa_offset 8 3277 frame-setup CFI_INSTRUCTION offset $lr, -4 3278 frame-setup CFI_INSTRUCTION offset $r7, -8 3279 tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr 3280 $r2 = tMOVr $r3, 14 /* CC::al */, $noreg 3281 t2IT 10, 8, implicit-def $itstate 3282 renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate 3283 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 3284 tBcc %bb.4, 11 /* CC::lt */, killed $cpsr 3285 3286 bb.1.while.body.preheader: 3287 successors: %bb.2(0x80000000) 3288 liveins: $r0, $r1, $r2, $r3 3289 3290 renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg 3291 renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg 3292 renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 3293 renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg 3294 $lr = t2DoLoopStart renamable $r2 3295 $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3296 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3297 3298 bb.2.while.body: 3299 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 3300 liveins: $r0, $r1, $r2, $r3, $r12 3301 3302 renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg 3303 MVE_VPST 4, implicit $vpr 3304 renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2) 3305 renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2) 3306 $lr = tMOVr $r12, 14 /* CC::al */, $noreg 3307 renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 3308 renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg 3309 renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg 3310 renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg 3311 renamable $lr = t2LoopDec killed renamable $lr, 1 3312 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 3313 tB %bb.3, 14 /* CC::al */, $noreg 3314 3315 bb.3.while.end: 3316 liveins: $r2 3317 3318 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3319 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3320 3321 bb.4: 3322 renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 3323 $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg 3324 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 3325 3326... 3327