1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s 3 4--- | 5 define arm_aapcs_vfpcc void @test_vmvn(ptr %a, ptr %b, ptr %c, i32 %elts, i32 %iters) #0 { 6 entry: 7 %cmp = icmp slt i32 %elts, 1 8 br i1 %cmp, label %exit, label %loop.ph 9 10 loop.ph: ; preds = %entry 11 %start = call i32 @llvm.start.loop.iterations.i32(i32 %iters) 12 br label %loop.body 13 14 loop.body: ; preds = %loop.body, %loop.ph 15 %lsr.iv = phi i32 [ %lsr.iv.next, %loop.body ], [ %start, %loop.ph ] 16 %count = phi i32 [ %elts, %loop.ph ], [ %elts.rem, %loop.body ] 17 %addr.a = phi ptr [ %a, %loop.ph ], [ %addr.a.next, %loop.body ] 18 %addr.b = phi ptr [ %b, %loop.ph ], [ %addr.b.next, %loop.body ] 19 %addr.c = phi ptr [ %c, %loop.ph ], [ %addr.c.next, %loop.body ] 20 %pred = call <4 x i1> @llvm.arm.mve.vctp32(i32 %count) 21 %elts.rem = sub i32 %count, 4 22 %masked.load.a = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %addr.a, i32 4, <4 x i1> %pred, <4 x i32> undef) 23 %masked.load.b = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %addr.b, i32 4, <4 x i1> %pred, <4 x i32> undef) 24 %not = xor <4 x i32> %masked.load.b, <i32 -1, i32 -1, i32 -1, i32 -1> 25 %bitcast.a = bitcast <4 x i32> %masked.load.a to <8 x i16> 26 %shrn = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %bitcast.a, <4 x i32> %not, i32 15, i32 1, i32 0, i32 0, i32 0, i32 0) 27 %bitcast = bitcast <8 x i16> %shrn to <4 x i32> 28 call void @llvm.masked.store.v4i32.p0(<4 x i32> %bitcast, ptr %addr.c, i32 4, <4 x i1> %pred) 29 %addr.a.next = getelementptr <4 x i32>, ptr %addr.a, i32 1 30 %addr.b.next = getelementptr <4 x i32>, ptr %addr.b, i32 1 31 %addr.c.next = getelementptr <4 x i32>, ptr %addr.c, i32 1 32 %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1) 33 %end = icmp ne i32 %loop.dec, 0 34 %lsr.iv.next = add i32 %lsr.iv, -1 35 br i1 %end, label %loop.body, label %exit 36 37 exit: ; preds = %loop.body, %entry 38 ret void 39 } 40 41 define arm_aapcs_vfpcc void @test_vorn(ptr %a, ptr %b, ptr %c, i32 %elts, i32 %iters) #0 { 42 entry: 43 %cmp = icmp slt i32 %elts, 1 44 br i1 %cmp, label %exit, label %loop.ph 45 46 loop.ph: ; preds = %entry 47 %start = call i32 @llvm.start.loop.iterations.i32(i32 %iters) 48 br label %loop.body 49 50 loop.body: ; preds = %loop.body, %loop.ph 51 %lsr.iv = phi i32 [ %lsr.iv.next, %loop.body ], [ %start, %loop.ph ] 52 %count = phi i32 [ %elts, %loop.ph ], [ %elts.rem, %loop.body ] 53 %addr.a = phi ptr [ %a, %loop.ph ], [ %addr.a.next, %loop.body ] 54 %addr.b = phi ptr [ %b, %loop.ph ], [ %addr.b.next, %loop.body ] 55 %addr.c = phi ptr [ %c, %loop.ph ], [ %addr.c.next, %loop.body ] 56 %pred = call <4 x i1> @llvm.arm.mve.vctp32(i32 %count) 57 %elts.rem = sub i32 %count, 4 58 %masked.load.a = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %addr.a, i32 4, <4 x i1> %pred, <4 x i32> undef) 59 %masked.load.b = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %addr.b, i32 4, <4 x i1> %pred, <4 x i32> undef) 60 %not = xor <4 x i32> %masked.load.b, <i32 -1, i32 -1, i32 -1, i32 -1> 61 %or = or <4 x i32> %not, %masked.load.a 62 %bitcast.a = bitcast <4 x i32> %masked.load.a to <8 x i16> 63 %shrn = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %bitcast.a, <4 x i32> %or, i32 3, i32 1, i32 0, i32 1, i32 0, i32 1) 64 %bitcast = bitcast <8 x i16> %shrn to <4 x i32> 65 call void @llvm.masked.store.v4i32.p0(<4 x i32> %bitcast, ptr %addr.c, i32 4, <4 x i1> %pred) 66 %addr.a.next = getelementptr <4 x i32>, ptr %addr.a, i32 1 67 %addr.b.next = getelementptr <4 x i32>, ptr %addr.b, i32 1 68 %addr.c.next = getelementptr <4 x i32>, ptr %addr.c, i32 1 69 %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1) 70 %end = icmp ne i32 %loop.dec, 0 71 %lsr.iv.next = add i32 %lsr.iv, -1 72 br i1 %end, label %loop.body, label %exit 73 74 exit: ; preds = %loop.body, %entry 75 ret void 76 } 77 78 declare i32 @llvm.start.loop.iterations.i32(i32) 79 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 80 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 81 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) 82 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>) 83 declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32) 84 85... 86--- 87name: test_vmvn 88alignment: 2 89tracksRegLiveness: true 90registers: [] 91liveins: 92 - { reg: '$r0', virtual-reg: '' } 93 - { reg: '$r1', virtual-reg: '' } 94 - { reg: '$r2', virtual-reg: '' } 95 - { reg: '$r3', virtual-reg: '' } 96frameInfo: 97 stackSize: 8 98 offsetAdjustment: 0 99 maxAlignment: 4 100fixedStack: 101 - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default, 102 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 103 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 104stack: 105 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 106 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 107 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 108 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 109 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 110 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 111callSites: [] 112constants: [] 113machineFunctionInfo: {} 114body: | 115 ; CHECK-LABEL: name: test_vmvn 116 ; CHECK: bb.0.entry: 117 ; CHECK-NEXT: successors: %bb.1(0x80000000) 118 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 119 ; CHECK-NEXT: {{ $}} 120 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 121 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 122 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 123 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 124 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 125 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate 126 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 127 ; CHECK-NEXT: {{ $}} 128 ; CHECK-NEXT: bb.1.loop.ph: 129 ; CHECK-NEXT: successors: %bb.2(0x80000000) 130 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 131 ; CHECK-NEXT: {{ $}} 132 ; CHECK-NEXT: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) 133 ; CHECK-NEXT: dead $lr = t2DLS renamable $r4 134 ; CHECK-NEXT: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg 135 ; CHECK-NEXT: {{ $}} 136 ; CHECK-NEXT: bb.2.loop.body: 137 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 138 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12 139 ; CHECK-NEXT: {{ $}} 140 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg 141 ; CHECK-NEXT: $lr = tMOVr $r12, 14 /* CC::al */, $noreg 142 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr 143 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4) 144 ; CHECK-NEXT: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4) 145 ; CHECK-NEXT: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg 146 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg 147 ; CHECK-NEXT: renamable $q1 = MVE_VMVN killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 148 ; CHECK-NEXT: renamable $q0 = MVE_VQSHRNbhs32 killed renamable $q0, killed renamable $q1, 15, 0, $noreg, $noreg 149 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 150 ; CHECK-NEXT: renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4) 151 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 152 ; CHECK-NEXT: {{ $}} 153 ; CHECK-NEXT: bb.3.exit: 154 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 155 bb.0.entry: 156 successors: %bb.1(0x80000000) 157 liveins: $r0, $r1, $r2, $r3, $r4, $lr 158 159 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 160 frame-setup CFI_INSTRUCTION def_cfa_offset 8 161 frame-setup CFI_INSTRUCTION offset $lr, -4 162 frame-setup CFI_INSTRUCTION offset $r4, -8 163 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 164 t2IT 11, 8, implicit-def $itstate 165 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 166 167 bb.1.loop.ph: 168 successors: %bb.2(0x80000000) 169 liveins: $r0, $r1, $r2, $r3, $r4, $lr 170 171 renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) 172 $lr = t2DoLoopStart renamable $r4 173 $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg 174 175 bb.2.loop.body: 176 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 177 liveins: $r0, $r1, $r2, $r3, $r12 178 179 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg 180 $lr = tMOVr $r12, 14 /* CC::al */, $noreg 181 MVE_VPST 4, implicit $vpr 182 renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4) 183 renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4) 184 renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg 185 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg 186 renamable $q1 = MVE_VMVN killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 187 renamable $lr = t2LoopDec killed renamable $lr, 1 188 renamable $q0 = MVE_VQSHRNbhs32 killed renamable $q0, killed renamable $q1, 15, 0, $noreg, $noreg 189 MVE_VPST 8, implicit $vpr 190 renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4) 191 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 192 tB %bb.3, 14 /* CC::al */, $noreg 193 194 bb.3.exit: 195 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 196 197... 198--- 199name: test_vorn 200alignment: 2 201tracksRegLiveness: true 202registers: [] 203liveins: 204 - { reg: '$r0', virtual-reg: '' } 205 - { reg: '$r1', virtual-reg: '' } 206 - { reg: '$r2', virtual-reg: '' } 207 - { reg: '$r3', virtual-reg: '' } 208frameInfo: 209 stackSize: 8 210 offsetAdjustment: 0 211 maxAlignment: 4 212fixedStack: 213 - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default, 214 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 215 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 216stack: 217 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 218 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 219 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 220 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 221 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 222 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 223callSites: [] 224constants: [] 225machineFunctionInfo: {} 226body: | 227 ; CHECK-LABEL: name: test_vorn 228 ; CHECK: bb.0.entry: 229 ; CHECK-NEXT: successors: %bb.1(0x80000000) 230 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 231 ; CHECK-NEXT: {{ $}} 232 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 233 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 234 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 235 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 236 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 237 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate 238 ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 239 ; CHECK-NEXT: {{ $}} 240 ; CHECK-NEXT: bb.1.loop.ph: 241 ; CHECK-NEXT: successors: %bb.2(0x80000000) 242 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 243 ; CHECK-NEXT: {{ $}} 244 ; CHECK-NEXT: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) 245 ; CHECK-NEXT: dead $lr = t2DLS renamable $r4 246 ; CHECK-NEXT: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg 247 ; CHECK-NEXT: {{ $}} 248 ; CHECK-NEXT: bb.2.loop.body: 249 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 250 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12 251 ; CHECK-NEXT: {{ $}} 252 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg 253 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr 254 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4) 255 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4) 256 ; CHECK-NEXT: $lr = tMOVr $r12, 14 /* CC::al */, $noreg 257 ; CHECK-NEXT: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg 258 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg 259 ; CHECK-NEXT: renamable $q0 = MVE_VORN renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 260 ; CHECK-NEXT: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg 261 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 262 ; CHECK-NEXT: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4) 263 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 264 ; CHECK-NEXT: {{ $}} 265 ; CHECK-NEXT: bb.3.exit: 266 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 267 bb.0.entry: 268 successors: %bb.1(0x80000000) 269 liveins: $r0, $r1, $r2, $r3, $r4, $lr 270 271 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 272 frame-setup CFI_INSTRUCTION def_cfa_offset 8 273 frame-setup CFI_INSTRUCTION offset $lr, -4 274 frame-setup CFI_INSTRUCTION offset $r4, -8 275 tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 276 t2IT 11, 8, implicit-def $itstate 277 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 278 279 bb.1.loop.ph: 280 successors: %bb.2(0x80000000) 281 liveins: $r0, $r1, $r2, $r3, $r4, $lr 282 283 renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) 284 $lr = t2DoLoopStart renamable $r4 285 $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg 286 287 bb.2.loop.body: 288 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 289 liveins: $r0, $r1, $r2, $r3, $r12 290 291 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg 292 MVE_VPST 4, implicit $vpr 293 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4) 294 renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4) 295 $lr = tMOVr $r12, 14 /* CC::al */, $noreg 296 renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg 297 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg 298 renamable $q0 = MVE_VORN renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 299 renamable $lr = t2LoopDec killed renamable $lr, 1 300 renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg 301 MVE_VPST 8, implicit $vpr 302 renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4) 303 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 304 tB %bb.3, 14 /* CC::al */, $noreg 305 306 bb.3.exit: 307 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 308 309... 310