1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops -verify-machineinstrs %s -o - | FileCheck %s 3# Check that subs isn't used during the revert because there's a cpsr use after it. 4 5--- | 6 define i32 @do_copy(i32 %n, ptr nocapture %p, ptr nocapture readonly %q) { 7 entry: 8 %scevgep = getelementptr i32, ptr %q, i32 -1 9 %scevgep3 = getelementptr i32, ptr %p, i32 -1 10 %start = call i32 @llvm.start.loop.iterations.i32(i32 %n) 11 %limit = lshr i32 %n, 1 12 br label %while.body 13 14 while.body: ; preds = %while.body, %entry 15 %lsr.iv4 = phi ptr [ %scevgep5, %while.body ], [ %scevgep3, %entry ] 16 %lsr.iv = phi ptr [ %scevgep1, %while.body ], [ %scevgep, %entry ] 17 %tmp = phi i32 [ %start, %entry ], [ %tmp2, %while.body ] 18 %scevgep7 = getelementptr i32, ptr %lsr.iv, i32 1 19 %scevgep4 = getelementptr i32, ptr %lsr.iv4, i32 1 20 %tmp1 = load i32, ptr %scevgep7, align 4 21 %tmp2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp, i32 1) 22 %half = lshr i32 %tmp1, 1 23 %cmp = icmp ult i32 %tmp, %limit 24 %res = select i1 %cmp, i32 %tmp1, i32 %half 25 store i32 %res, ptr %scevgep4, align 4 26 %scevgep1 = getelementptr i32, ptr %lsr.iv, i32 1 27 %scevgep5 = getelementptr i32, ptr %lsr.iv4, i32 1 28 %tmp3 = icmp ne i32 %tmp2, 0 29 br i1 %tmp3, label %while.body, label %while.end 30 31 while.end: ; preds = %while.body 32 ret i32 0 33 } 34 35 declare i32 @llvm.start.loop.iterations.i32(i32) #0 36 37 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0 38 39 declare void @llvm.stackprotector(ptr, ptr) #1 40 41 attributes #0 = { noduplicate nounwind } 42 attributes #1 = { nounwind } 43 44... 45--- 46name: do_copy 47alignment: 2 48exposesReturnsTwice: false 49legalized: false 50regBankSelected: false 51selected: false 52failedISel: false 53tracksRegLiveness: true 54hasWinCFI: false 55registers: [] 56liveins: 57 - { reg: '$r0', virtual-reg: '' } 58 - { reg: '$r1', virtual-reg: '' } 59 - { reg: '$r2', virtual-reg: '' } 60frameInfo: 61 isFrameAddressTaken: false 62 isReturnAddressTaken: false 63 hasStackMap: false 64 hasPatchPoint: false 65 stackSize: 8 66 offsetAdjustment: 0 67 maxAlignment: 4 68 adjustsStack: false 69 hasCalls: false 70 stackProtector: '' 71 maxCallFrameSize: 0 72 cvBytesOfCalleeSavedRegisters: 0 73 hasOpaqueSPAdjustment: false 74 hasVAStart: false 75 hasMustTailInVarArgFunc: false 76 localFrameSize: 0 77 savePoint: '' 78 restorePoint: '' 79fixedStack: [] 80stack: 81 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 82 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 83 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 84 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 85 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 86 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 87callSites: [] 88constants: [] 89machineFunctionInfo: {} 90body: | 91 ; CHECK-LABEL: name: do_copy 92 ; CHECK: bb.0.entry: 93 ; CHECK-NEXT: successors: %bb.1(0x80000000) 94 ; CHECK-NEXT: liveins: $lr, $r1, $r2, $r7 95 ; CHECK-NEXT: {{ $}} 96 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 97 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 98 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 99 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 100 ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 /* CC::al */, $noreg 101 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg 102 ; CHECK-NEXT: dead $lr = tMOVr renamable $r0, 14 /* CC::al */, $noreg 103 ; CHECK-NEXT: renamable $r2 = t2LSRri renamable $r0, 1, 14 /* CC::al */, $noreg, $noreg 104 ; CHECK-NEXT: $lr = tMOVr $r0, 14 /* CC::al */, $noreg 105 ; CHECK-NEXT: {{ $}} 106 ; CHECK-NEXT: bb.1.while.body: 107 ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000) 108 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 109 ; CHECK-NEXT: {{ $}} 110 ; CHECK-NEXT: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) 111 ; CHECK-NEXT: tCMPhir renamable $lr, renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr 112 ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg 113 ; CHECK-NEXT: t2IT 2, 8, implicit-def $itstate 114 ; CHECK-NEXT: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2 /* CC::hs */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate 115 ; CHECK-NEXT: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep4) 116 ; CHECK-NEXT: renamable $lr = tMOVr killed $lr, 14 /* CC::al */, $noreg 117 ; CHECK-NEXT: t2CMPri renamable $lr, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 118 ; CHECK-NEXT: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr 119 ; CHECK-NEXT: tB %bb.2, 14 /* CC::al */, $noreg 120 ; CHECK-NEXT: {{ $}} 121 ; CHECK-NEXT: bb.2.while.end: 122 ; CHECK-NEXT: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 123 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 124 bb.0.entry: 125 successors: %bb.1(0x80000000) 126 liveins: $r0, $r1, $r2, $r7, $lr 127 128 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 129 frame-setup CFI_INSTRUCTION def_cfa_offset 8 130 frame-setup CFI_INSTRUCTION offset $lr, -4 131 frame-setup CFI_INSTRUCTION offset $r7, -8 132 renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg 133 renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg 134 $lr = t2DoLoopStart renamable $r0 135 renamable $r2 = t2LSRri renamable $r0, 1, 14, $noreg, $noreg 136 $lr = tMOVr $r0, 14, $noreg 137 138 bb.1.while.body: 139 successors: %bb.1(0x7c000000), %bb.2(0x04000000) 140 liveins: $lr, $r0, $r1, $r2 141 142 renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load (s32) from %ir.scevgep7) 143 tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr 144 renamable $lr = t2LoopDec killed renamable $lr, 1 145 t2IT 2, 8, implicit-def $itstate 146 renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate 147 early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store (s32) into %ir.scevgep4) 148 renamable $lr = tMOVr $lr, 14, $noreg 149 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr 150 tB %bb.2, 14, $noreg 151 152 bb.2.while.end: 153 $r0, dead $cpsr = tMOVi8 0, 14, $noreg 154 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 155 156... 157