1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve %s -run-pass=arm-low-overhead-loops -o - | FileCheck %s 3 4--- | 5 define dso_local void @variant_max_use(ptr nocapture readonly %a, ptr %c, i32 %N) #0 { 6 entry: 7 %cmp9 = icmp eq i32 %N, 0 8 %tmp = add i32 %N, 3 9 %tmp1 = lshr i32 %tmp, 2 10 %tmp2 = shl nuw i32 %tmp1, 2 11 %tmp3 = add i32 %tmp2, -4 12 %tmp4 = lshr i32 %tmp3, 2 13 %tmp5 = add nuw nsw i32 %tmp4, 1 14 br i1 %cmp9, label %exit, label %vector.ph 15 16 vector.ph: ; preds = %entry 17 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 18 br label %vector.body 19 20 vector.body: ; preds = %vector.body, %vector.ph 21 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 22 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 23 %lsr.iv.2 = phi ptr [ %scevgep.2, %vector.body ], [ %c, %vector.ph ] 24 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 25 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 26 %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7) 27 %tmp9 = sub i32 %tmp7, 8 28 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef) 29 %min = tail call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %wide.masked.load) 30 store i16 %min, ptr %lsr.iv.2 31 %scevgep = getelementptr i16, ptr %lsr.iv, i32 8 32 %scevgep.2 = getelementptr i16, ptr %lsr.iv.2, i32 1 33 %tmp10 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 34 %tmp11 = icmp ne i32 %tmp10, 0 35 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 36 br i1 %tmp11, label %vector.body, label %exit 37 38 exit: ; preds = %vector.body, %entry 39 ret void 40 } 41 42 declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32 immarg, <8 x i1>, <8 x i16>) 43 declare i32 @llvm.start.loop.iterations.i32(i32) 44 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 45 declare <8 x i1> @llvm.arm.mve.vctp16(i32) 46 declare i16 @llvm.vector.reduce.smax.v8i16(<8 x i16>) 47 48... 49--- 50name: variant_max_use 51alignment: 2 52tracksRegLiveness: true 53registers: [] 54liveins: 55 - { reg: '$r0', virtual-reg: '' } 56 - { reg: '$r1', virtual-reg: '' } 57 - { reg: '$r2', virtual-reg: '' } 58frameInfo: 59 stackSize: 8 60 offsetAdjustment: 0 61 maxAlignment: 4 62fixedStack: [] 63stack: 64 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 65 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 66 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 67 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 68 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 69 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 70callSites: [] 71constants: [] 72machineFunctionInfo: {} 73body: | 74 ; CHECK-LABEL: name: variant_max_use 75 ; CHECK: bb.0.entry: 76 ; CHECK-NEXT: successors: %bb.1(0x80000000) 77 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r5 78 ; CHECK-NEXT: {{ $}} 79 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r5, killed $lr, implicit-def $sp, implicit $sp 80 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 81 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 82 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -8 83 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 84 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 85 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r5, def $pc, implicit killed $itstate 86 ; CHECK-NEXT: {{ $}} 87 ; CHECK-NEXT: bb.1.vector.ph: 88 ; CHECK-NEXT: successors: %bb.2(0x80000000) 89 ; CHECK-NEXT: liveins: $r0, $r1, $r2 90 ; CHECK-NEXT: {{ $}} 91 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 92 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 93 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 94 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 95 ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 96 ; CHECK-NEXT: $r12 = t2MOVi16 32768, 14 /* CC::al */, $noreg 97 ; CHECK-NEXT: $r12 = t2MOVTi16 killed $r12, 65535, 14 /* CC::al */, $noreg 98 ; CHECK-NEXT: dead $lr = t2DLS renamable $r3 99 ; CHECK-NEXT: $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg 100 ; CHECK-NEXT: {{ $}} 101 ; CHECK-NEXT: bb.2.vector.body: 102 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 103 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r5, $r12 104 ; CHECK-NEXT: {{ $}} 105 ; CHECK-NEXT: $r3 = tMOVr $r12, 14 /* CC::al */, $noreg 106 ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg 107 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 108 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2) 109 ; CHECK-NEXT: renamable $r3 = MVE_VMAXVs16 killed renamable $r3, killed renamable $q0, 0, $noreg, $noreg 110 ; CHECK-NEXT: $lr = tMOVr $r5, 14 /* CC::al */, $noreg 111 ; CHECK-NEXT: early-clobber renamable $r1 = t2STRH_POST killed renamable $r3, killed renamable $r1, 2, 14 /* CC::al */, $noreg :: (store (s16) into %ir.lsr.iv.2) 112 ; CHECK-NEXT: renamable $r5, dead $cpsr = nsw tSUBi8 killed $r5, 1, 14 /* CC::al */, $noreg 113 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg 114 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 115 ; CHECK-NEXT: {{ $}} 116 ; CHECK-NEXT: bb.3.exit: 117 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r5, def $pc 118 bb.0.entry: 119 successors: %bb.1(0x80000000) 120 liveins: $r0, $r1, $r2, $r5, $lr 121 122 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r5, killed $lr, implicit-def $sp, implicit $sp 123 frame-setup CFI_INSTRUCTION def_cfa_offset 8 124 frame-setup CFI_INSTRUCTION offset $lr, -4 125 frame-setup CFI_INSTRUCTION offset $r5, -8 126 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 127 t2IT 0, 8, implicit-def $itstate 128 tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r5, def $pc, implicit killed $itstate 129 130 bb.1.vector.ph: 131 successors: %bb.2(0x80000000) 132 liveins: $r0, $r1, $r2, $r5, $lr 133 134 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 135 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 136 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 137 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 138 renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 139 $r12 = t2MOVi16 32768, 14 /* CC::al */, $noreg 140 $r12 = t2MOVTi16 killed $r12, 65535, 14 /* CC::al */, $noreg 141 $lr = t2DoLoopStart renamable $r3 142 $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg 143 144 bb.2.vector.body: 145 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 146 liveins: $r0, $r1, $r2, $r5, $r12 147 148 $r3 = tMOVr $r12, 14 /* CC::al */, $noreg 149 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg 150 MVE_VPST 8, implicit $vpr 151 renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2) 152 renamable $r3 = MVE_VMAXVs16 killed renamable $r3, killed renamable $q0, 0, $noreg, $noreg 153 $lr = tMOVr $r5, 14 /* CC::al */, $noreg 154 early-clobber renamable $r1 = t2STRH_POST killed renamable $r3, killed renamable $r1, 2, 14 /* CC::al */, $noreg :: (store (s16) into %ir.lsr.iv.2) 155 renamable $r5, dead $cpsr = nsw tSUBi8 killed $r5, 1, 14 /* CC::al */, $noreg 156 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg 157 renamable $lr = t2LoopDec killed renamable $lr, 1 158 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 159 tB %bb.3, 14 /* CC::al */, $noreg 160 161 bb.3.exit: 162 tPOP_RET 14 /* CC::al */, $noreg, def $r5, def $pc 163 164... 165