1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs -tail-predication=enabled -o - %s | FileCheck %s 3 4define arm_aapcs_vfpcc void @usub_sat(ptr noalias nocapture readonly %pSrcA, ptr noalias nocapture readonly %pSrcB, ptr noalias nocapture %pDst, i32 %blockSize) { 5; CHECK-LABEL: usub_sat: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: .save {r7, lr} 8; CHECK-NEXT: push {r7, lr} 9; CHECK-NEXT: cmp r3, #0 10; CHECK-NEXT: it eq 11; CHECK-NEXT: popeq {r7, pc} 12; CHECK-NEXT: .LBB0_1: @ %vector.ph 13; CHECK-NEXT: dlstp.16 lr, r3 14; CHECK-NEXT: .LBB0_2: @ %vector.body 15; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 16; CHECK-NEXT: vldrh.u16 q0, [r1], #16 17; CHECK-NEXT: vldrh.u16 q1, [r0], #16 18; CHECK-NEXT: vqsub.u16 q0, q1, q0 19; CHECK-NEXT: vstrh.16 q0, [r2], #16 20; CHECK-NEXT: letp lr, .LBB0_2 21; CHECK-NEXT: @ %bb.3: @ %while.end 22; CHECK-NEXT: pop {r7, pc} 23entry: 24 %cmp7 = icmp eq i32 %blockSize, 0 25 br i1 %cmp7, label %while.end, label %vector.ph 26 27vector.ph: ; preds = %entry 28 %n.rnd.up = add i32 %blockSize, 7 29 %n.vec = and i32 %n.rnd.up, -8 30 br label %vector.body 31 32vector.body: ; preds = %vector.body, %vector.ph 33 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] 34 %next.gep = getelementptr i16, ptr %pSrcA, i32 %index 35 %next.gep20 = getelementptr i16, ptr %pDst, i32 %index 36 %next.gep21 = getelementptr i16, ptr %pSrcB, i32 %index 37 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize) 38 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %next.gep, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef) 39 %wide.masked.load24 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %next.gep21, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef) 40 %0 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %wide.masked.load, <8 x i16> %wide.masked.load24) 41 call void @llvm.masked.store.v8i16.p0(<8 x i16> %0, ptr %next.gep20, i32 2, <8 x i1> %active.lane.mask) 42 %index.next = add i32 %index, 8 43 %1 = icmp eq i32 %index.next, %n.vec 44 br i1 %1, label %while.end, label %vector.body 45 46while.end: ; preds = %vector.body, %entry 47 ret void 48} 49 50define arm_aapcs_vfpcc void @ssub_sat(ptr noalias nocapture readonly %pSrcA, ptr noalias nocapture readonly %pSrcB, ptr noalias nocapture %pDst, i32 %blockSize) { 51; CHECK-LABEL: ssub_sat: 52; CHECK: @ %bb.0: @ %entry 53; CHECK-NEXT: .save {r7, lr} 54; CHECK-NEXT: push {r7, lr} 55; CHECK-NEXT: cmp r3, #0 56; CHECK-NEXT: it eq 57; CHECK-NEXT: popeq {r7, pc} 58; CHECK-NEXT: .LBB1_1: @ %vector.ph 59; CHECK-NEXT: dlstp.16 lr, r3 60; CHECK-NEXT: .LBB1_2: @ %vector.body 61; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 62; CHECK-NEXT: vldrh.u16 q0, [r1], #16 63; CHECK-NEXT: vldrh.u16 q1, [r0], #16 64; CHECK-NEXT: vqsub.s16 q0, q1, q0 65; CHECK-NEXT: vstrh.16 q0, [r2], #16 66; CHECK-NEXT: letp lr, .LBB1_2 67; CHECK-NEXT: @ %bb.3: @ %while.end 68; CHECK-NEXT: pop {r7, pc} 69entry: 70 %cmp7 = icmp eq i32 %blockSize, 0 71 br i1 %cmp7, label %while.end, label %vector.ph 72 73vector.ph: ; preds = %entry 74 %n.rnd.up = add i32 %blockSize, 7 75 %n.vec = and i32 %n.rnd.up, -8 76 br label %vector.body 77 78vector.body: ; preds = %vector.body, %vector.ph 79 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] 80 %next.gep = getelementptr i16, ptr %pSrcA, i32 %index 81 %next.gep20 = getelementptr i16, ptr %pDst, i32 %index 82 %next.gep21 = getelementptr i16, ptr %pSrcB, i32 %index 83 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize) 84 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %next.gep, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef) 85 %wide.masked.load24 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %next.gep21, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef) 86 %0 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %wide.masked.load, <8 x i16> %wide.masked.load24) 87 call void @llvm.masked.store.v8i16.p0(<8 x i16> %0, ptr %next.gep20, i32 2, <8 x i1> %active.lane.mask) 88 %index.next = add i32 %index, 8 89 %1 = icmp eq i32 %index.next, %n.vec 90 br i1 %1, label %while.end, label %vector.body 91 92while.end: ; preds = %vector.body, %entry 93 ret void 94} 95 96declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32) 97 98declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32 immarg, <8 x i1>, <8 x i16>) 99 100declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) 101 102declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>) 103 104declare void @llvm.masked.store.v8i16.p0(<8 x i16>, ptr, i32 immarg, <8 x i1>) 105